| Tony Lindgren | fc44046 | 2010-07-05 16:31:36 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2009 Nokia |
| 3 | * Copyright (C) 2009 Texas Instruments |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | */ |
| 9 | |
| 10 | #define OMAP2420_CONTROL_PADCONF_MUX_PBASE 0x48000030LU |
| 11 | |
| 12 | #define OMAP2420_MUX(mode0, mux_value) \ |
| 13 | { \ |
| 14 | .reg_offset = (OMAP2420_CONTROL_PADCONF_##mode0##_OFFSET), \ |
| 15 | .value = (mux_value), \ |
| 16 | } |
| 17 | |
| 18 | /* |
| 19 | * OMAP2420 CONTROL_PADCONF* register offsets for pin-muxing |
| 20 | * |
| 21 | * Extracted from the TRM. Add 0x48000030 to these values to get the |
| 22 | * absolute addresses. The name in the macro is the mode-0 name of |
| 23 | * the pin. NOTE: These registers are 8-bits wide. |
| 24 | */ |
| 25 | #define OMAP2420_CONTROL_PADCONF_SDRC_A14_OFFSET 0x000 |
| 26 | #define OMAP2420_CONTROL_PADCONF_SDRC_A13_OFFSET 0x001 |
| 27 | #define OMAP2420_CONTROL_PADCONF_SDRC_A12_OFFSET 0x002 |
| 28 | #define OMAP2420_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x003 |
| 29 | #define OMAP2420_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x004 |
| 30 | #define OMAP2420_CONTROL_PADCONF_SDRC_A11_OFFSET 0x005 |
| 31 | #define OMAP2420_CONTROL_PADCONF_SDRC_A10_OFFSET 0x006 |
| 32 | #define OMAP2420_CONTROL_PADCONF_SDRC_A9_OFFSET 0x007 |
| 33 | #define OMAP2420_CONTROL_PADCONF_SDRC_A8_OFFSET 0x008 |
| 34 | #define OMAP2420_CONTROL_PADCONF_SDRC_A7_OFFSET 0x009 |
| 35 | #define OMAP2420_CONTROL_PADCONF_SDRC_A6_OFFSET 0x00a |
| 36 | #define OMAP2420_CONTROL_PADCONF_SDRC_A5_OFFSET 0x00b |
| 37 | #define OMAP2420_CONTROL_PADCONF_SDRC_A4_OFFSET 0x00c |
| 38 | #define OMAP2420_CONTROL_PADCONF_SDRC_A3_OFFSET 0x00d |
| 39 | #define OMAP2420_CONTROL_PADCONF_SDRC_A2_OFFSET 0x00e |
| 40 | #define OMAP2420_CONTROL_PADCONF_SDRC_A1_OFFSET 0x00f |
| 41 | #define OMAP2420_CONTROL_PADCONF_SDRC_A0_OFFSET 0x010 |
| 42 | #define OMAP2420_CONTROL_PADCONF_SDRC_D31_OFFSET 0x021 |
| 43 | #define OMAP2420_CONTROL_PADCONF_SDRC_D30_OFFSET 0x022 |
| 44 | #define OMAP2420_CONTROL_PADCONF_SDRC_D29_OFFSET 0x023 |
| 45 | #define OMAP2420_CONTROL_PADCONF_SDRC_D28_OFFSET 0x024 |
| 46 | #define OMAP2420_CONTROL_PADCONF_SDRC_D27_OFFSET 0x025 |
| 47 | #define OMAP2420_CONTROL_PADCONF_SDRC_D26_OFFSET 0x026 |
| 48 | #define OMAP2420_CONTROL_PADCONF_SDRC_D25_OFFSET 0x027 |
| 49 | #define OMAP2420_CONTROL_PADCONF_SDRC_D24_OFFSET 0x028 |
| 50 | #define OMAP2420_CONTROL_PADCONF_SDRC_D23_OFFSET 0x029 |
| 51 | #define OMAP2420_CONTROL_PADCONF_SDRC_D22_OFFSET 0x02a |
| 52 | #define OMAP2420_CONTROL_PADCONF_SDRC_D21_OFFSET 0x02b |
| 53 | #define OMAP2420_CONTROL_PADCONF_SDRC_D20_OFFSET 0x02c |
| 54 | #define OMAP2420_CONTROL_PADCONF_SDRC_D19_OFFSET 0x02d |
| 55 | #define OMAP2420_CONTROL_PADCONF_SDRC_D18_OFFSET 0x02e |
| 56 | #define OMAP2420_CONTROL_PADCONF_SDRC_D17_OFFSET 0x02f |
| 57 | #define OMAP2420_CONTROL_PADCONF_SDRC_D16_OFFSET 0x030 |
| 58 | #define OMAP2420_CONTROL_PADCONF_SDRC_D15_OFFSET 0x031 |
| 59 | #define OMAP2420_CONTROL_PADCONF_SDRC_D14_OFFSET 0x032 |
| 60 | #define OMAP2420_CONTROL_PADCONF_SDRC_D13_OFFSET 0x033 |
| 61 | #define OMAP2420_CONTROL_PADCONF_SDRC_D12_OFFSET 0x034 |
| 62 | #define OMAP2420_CONTROL_PADCONF_SDRC_D11_OFFSET 0x035 |
| 63 | #define OMAP2420_CONTROL_PADCONF_SDRC_D10_OFFSET 0x036 |
| 64 | #define OMAP2420_CONTROL_PADCONF_SDRC_D9_OFFSET 0x037 |
| 65 | #define OMAP2420_CONTROL_PADCONF_SDRC_D8_OFFSET 0x038 |
| 66 | #define OMAP2420_CONTROL_PADCONF_SDRC_D7_OFFSET 0x039 |
| 67 | #define OMAP2420_CONTROL_PADCONF_SDRC_D6_OFFSET 0x03a |
| 68 | #define OMAP2420_CONTROL_PADCONF_SDRC_D5_OFFSET 0x03b |
| 69 | #define OMAP2420_CONTROL_PADCONF_SDRC_D4_OFFSET 0x03c |
| 70 | #define OMAP2420_CONTROL_PADCONF_SDRC_D3_OFFSET 0x03d |
| 71 | #define OMAP2420_CONTROL_PADCONF_SDRC_D2_OFFSET 0x03e |
| 72 | #define OMAP2420_CONTROL_PADCONF_SDRC_D1_OFFSET 0x03f |
| 73 | #define OMAP2420_CONTROL_PADCONF_SDRC_D0_OFFSET 0x040 |
| 74 | #define OMAP2420_CONTROL_PADCONF_GPMC_A10_OFFSET 0x041 |
| 75 | #define OMAP2420_CONTROL_PADCONF_GPMC_A9_OFFSET 0x042 |
| 76 | #define OMAP2420_CONTROL_PADCONF_GPMC_A8_OFFSET 0x043 |
| 77 | #define OMAP2420_CONTROL_PADCONF_GPMC_A7_OFFSET 0x044 |
| 78 | #define OMAP2420_CONTROL_PADCONF_GPMC_A6_OFFSET 0x045 |
| 79 | #define OMAP2420_CONTROL_PADCONF_GPMC_A5_OFFSET 0x046 |
| 80 | #define OMAP2420_CONTROL_PADCONF_GPMC_A4_OFFSET 0x047 |
| 81 | #define OMAP2420_CONTROL_PADCONF_GPMC_A3_OFFSET 0x048 |
| 82 | #define OMAP2420_CONTROL_PADCONF_GPMC_A2_OFFSET 0x049 |
| 83 | #define OMAP2420_CONTROL_PADCONF_GPMC_A1_OFFSET 0x04a |
| 84 | #define OMAP2420_CONTROL_PADCONF_GPMC_D15_OFFSET 0x04b |
| 85 | #define OMAP2420_CONTROL_PADCONF_GPMC_D14_OFFSET 0x04c |
| 86 | #define OMAP2420_CONTROL_PADCONF_GPMC_D13_OFFSET 0x04d |
| 87 | #define OMAP2420_CONTROL_PADCONF_GPMC_D12_OFFSET 0x04e |
| 88 | #define OMAP2420_CONTROL_PADCONF_GPMC_D11_OFFSET 0x04f |
| 89 | #define OMAP2420_CONTROL_PADCONF_GPMC_D10_OFFSET 0x050 |
| 90 | #define OMAP2420_CONTROL_PADCONF_GPMC_D9_OFFSET 0x051 |
| 91 | #define OMAP2420_CONTROL_PADCONF_GPMC_D8_OFFSET 0x052 |
| 92 | #define OMAP2420_CONTROL_PADCONF_GPMC_D7_OFFSET 0x053 |
| 93 | #define OMAP2420_CONTROL_PADCONF_GPMC_D6_OFFSET 0x054 |
| 94 | #define OMAP2420_CONTROL_PADCONF_GPMC_D5_OFFSET 0x055 |
| 95 | #define OMAP2420_CONTROL_PADCONF_GPMC_D4_OFFSET 0x056 |
| 96 | #define OMAP2420_CONTROL_PADCONF_GPMC_D3_OFFSET 0x057 |
| 97 | #define OMAP2420_CONTROL_PADCONF_GPMC_D2_OFFSET 0x058 |
| 98 | #define OMAP2420_CONTROL_PADCONF_GPMC_D1_OFFSET 0x059 |
| 99 | #define OMAP2420_CONTROL_PADCONF_GPMC_D0_OFFSET 0x05a |
| 100 | #define OMAP2420_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x05b |
| 101 | #define OMAP2420_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x05c |
| 102 | #define OMAP2420_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x05d |
| 103 | #define OMAP2420_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x05e |
| 104 | #define OMAP2420_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x05f |
| 105 | #define OMAP2420_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x060 |
| 106 | #define OMAP2420_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x061 |
| 107 | #define OMAP2420_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x062 |
| 108 | #define OMAP2420_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x063 |
| 109 | #define OMAP2420_CONTROL_PADCONF_GPMC_NALE_ALE_OFFSET 0x064 |
| 110 | #define OMAP2420_CONTROL_PADCONF_GPMC_NOE_OFFSET 0x065 |
| 111 | #define OMAP2420_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x066 |
| 112 | #define OMAP2420_CONTROL_PADCONF_GPMC_NBE0_OFFSET 0x067 |
| 113 | #define OMAP2420_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x068 |
| 114 | #define OMAP2420_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x069 |
| 115 | #define OMAP2420_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x06a |
| 116 | #define OMAP2420_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x06b |
| 117 | #define OMAP2420_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x06c |
| 118 | #define OMAP2420_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x06d |
| 119 | #define OMAP2420_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x06e |
| 120 | #define OMAP2420_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x06f |
| 121 | #define OMAP2420_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x070 |
| 122 | #define OMAP2420_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x071 |
| 123 | #define OMAP2420_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x072 |
| 124 | #define OMAP2420_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x073 |
| 125 | #define OMAP2420_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x074 |
| 126 | #define OMAP2420_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x075 |
| 127 | #define OMAP2420_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x076 |
| 128 | #define OMAP2420_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x077 |
| 129 | #define OMAP2420_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x078 |
| 130 | #define OMAP2420_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x079 |
| 131 | #define OMAP2420_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x07a |
| 132 | #define OMAP2420_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x07f |
| 133 | #define OMAP2420_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x080 |
| 134 | #define OMAP2420_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x081 |
| 135 | #define OMAP2420_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x082 |
| 136 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x083 |
| 137 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x084 |
| 138 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x085 |
| 139 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x086 |
| 140 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x087 |
| 141 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x088 |
| 142 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x089 |
| 143 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x08a |
| 144 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x08b |
| 145 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x08c |
| 146 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x08d |
| 147 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x08e |
| 148 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x08f |
| 149 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x090 |
| 150 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x091 |
| 151 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x092 |
| 152 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x093 |
| 153 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x094 |
| 154 | #define OMAP2420_CONTROL_PADCONF_UART1_CTS_OFFSET 0x095 |
| 155 | #define OMAP2420_CONTROL_PADCONF_UART1_RTS_OFFSET 0x096 |
| 156 | #define OMAP2420_CONTROL_PADCONF_UART1_TX_OFFSET 0x097 |
| 157 | #define OMAP2420_CONTROL_PADCONF_UART1_RX_OFFSET 0x098 |
| 158 | #define OMAP2420_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x099 |
| 159 | #define OMAP2420_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x09a |
| 160 | #define OMAP2420_CONTROL_PADCONF_DSS_PCL_OFFSET 0x09b |
| 161 | #define OMAP2420_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x09c |
| 162 | #define OMAP2420_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x09d |
| 163 | #define OMAP2420_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x09e |
| 164 | #define OMAP2420_CONTROL_PADCONF_CAM_D9_OFFSET 0x09f |
| 165 | #define OMAP2420_CONTROL_PADCONF_CAM_D8_OFFSET 0x0a0 |
| 166 | #define OMAP2420_CONTROL_PADCONF_CAM_D7_OFFSET 0x0a1 |
| 167 | #define OMAP2420_CONTROL_PADCONF_CAM_D6_OFFSET 0x0a2 |
| 168 | #define OMAP2420_CONTROL_PADCONF_CAM_D5_OFFSET 0x0a3 |
| 169 | #define OMAP2420_CONTROL_PADCONF_CAM_D4_OFFSET 0x0a4 |
| 170 | #define OMAP2420_CONTROL_PADCONF_CAM_D3_OFFSET 0x0a5 |
| 171 | #define OMAP2420_CONTROL_PADCONF_CAM_D2_OFFSET 0x0a6 |
| 172 | #define OMAP2420_CONTROL_PADCONF_CAM_D1_OFFSET 0x0a7 |
| 173 | #define OMAP2420_CONTROL_PADCONF_CAM_D0_OFFSET 0x0a8 |
| 174 | #define OMAP2420_CONTROL_PADCONF_CAM_HS_OFFSET 0x0a9 |
| 175 | #define OMAP2420_CONTROL_PADCONF_CAM_VS_OFFSET 0x0aa |
| 176 | #define OMAP2420_CONTROL_PADCONF_CAM_LCLK_OFFSET 0x0ab |
| 177 | #define OMAP2420_CONTROL_PADCONF_CAM_XCLK_OFFSET 0x0ac |
| 178 | #define OMAP2420_CONTROL_PADCONF_SSI1_DAT_TX_OFFSET 0x0ad |
| 179 | #define OMAP2420_CONTROL_PADCONF_SSI1_FLAG_TX_OFFSET 0x0ae |
| 180 | #define OMAP2420_CONTROL_PADCONF_SSI1_RDY_TX_OFFSET 0x0af |
| 181 | #define OMAP2420_CONTROL_PADCONF_GPIO_62_OFFSET 0x0b0 |
| 182 | #define OMAP2420_CONTROL_PADCONF_SSI1_DAT_RX_OFFSET 0x0b1 |
| 183 | #define OMAP2420_CONTROL_PADCONF_SSI1_FLAG_RX_OFFSET 0x0b2 |
| 184 | #define OMAP2420_CONTROL_PADCONF_SSI1_RDY_RX_OFFSET 0x0b3 |
| 185 | #define OMAP2420_CONTROL_PADCONF_SSI1_WAKE_OFFSET 0x0b4 |
| 186 | #define OMAP2420_CONTROL_PADCONF_VLYNQ_CLK_OFFSET 0x0b5 |
| 187 | #define OMAP2420_CONTROL_PADCONF_VLYNQ_RX1_OFFSET 0x0b6 |
| 188 | #define OMAP2420_CONTROL_PADCONF_VLYNQ_RX0_OFFSET 0x0b7 |
| 189 | #define OMAP2420_CONTROL_PADCONF_VLYNQ_TX1_OFFSET 0x0b8 |
| 190 | #define OMAP2420_CONTROL_PADCONF_VLYNQ_TX0_OFFSET 0x0b9 |
| 191 | #define OMAP2420_CONTROL_PADCONF_VLYNQ_NLA_OFFSET 0x0ba |
| 192 | #define OMAP2420_CONTROL_PADCONF_UART2_CTS_OFFSET 0x0bb |
| 193 | #define OMAP2420_CONTROL_PADCONF_UART2_RTS_OFFSET 0x0bc |
| 194 | #define OMAP2420_CONTROL_PADCONF_UART2_TX_OFFSET 0x0bd |
| 195 | #define OMAP2420_CONTROL_PADCONF_UART2_RX_OFFSET 0x0be |
| 196 | #define OMAP2420_CONTROL_PADCONF_EAC_BT_SCLK_OFFSET 0x0bf |
| 197 | #define OMAP2420_CONTROL_PADCONF_EAC_BT_FS_OFFSET 0x0c0 |
| 198 | #define OMAP2420_CONTROL_PADCONF_EAC_BT_DIN_OFFSET 0x0c1 |
| 199 | #define OMAP2420_CONTROL_PADCONF_EAC_BT_DOUT_OFFSET 0x0c2 |
| 200 | #define OMAP2420_CONTROL_PADCONF_MMC_CLKO_OFFSET 0x0c3 |
| 201 | #define OMAP2420_CONTROL_PADCONF_MMC_CMD_OFFSET 0x0c4 |
| 202 | #define OMAP2420_CONTROL_PADCONF_MMC_DAT0_OFFSET 0x0c5 |
| 203 | #define OMAP2420_CONTROL_PADCONF_MMC_DAT1_OFFSET 0x0c6 |
| 204 | #define OMAP2420_CONTROL_PADCONF_MMC_DAT2_OFFSET 0x0c7 |
| 205 | #define OMAP2420_CONTROL_PADCONF_MMC_DAT3_OFFSET 0x0c8 |
| 206 | #define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR0_OFFSET 0x0c9 |
| 207 | #define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR1_OFFSET 0x0ca |
| 208 | #define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR2_OFFSET 0x0cb |
| 209 | #define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR3_OFFSET 0x0cc |
| 210 | #define OMAP2420_CONTROL_PADCONF_MMC_CMD_DIR_OFFSET 0x0cd |
| 211 | #define OMAP2420_CONTROL_PADCONF_MMC_CLKI_OFFSET 0x0ce |
| 212 | #define OMAP2420_CONTROL_PADCONF_SPI1_CLK_OFFSET 0x0cf |
| 213 | #define OMAP2420_CONTROL_PADCONF_SPI1_SIMO_OFFSET 0x0d0 |
| 214 | #define OMAP2420_CONTROL_PADCONF_SPI1_SOMI_OFFSET 0x0d1 |
| 215 | #define OMAP2420_CONTROL_PADCONF_SPI1_NCS0_OFFSET 0x0d2 |
| 216 | #define OMAP2420_CONTROL_PADCONF_SPI1_NCS1_OFFSET 0x0d3 |
| 217 | #define OMAP2420_CONTROL_PADCONF_SPI1_NCS2_OFFSET 0x0d4 |
| 218 | #define OMAP2420_CONTROL_PADCONF_SPI1_NCS3_OFFSET 0x0d5 |
| 219 | #define OMAP2420_CONTROL_PADCONF_SPI2_CLK_OFFSET 0x0d6 |
| 220 | #define OMAP2420_CONTROL_PADCONF_SPI2_SIMO_OFFSET 0x0d7 |
| 221 | #define OMAP2420_CONTROL_PADCONF_SPI2_SOMI_OFFSET 0x0d8 |
| 222 | #define OMAP2420_CONTROL_PADCONF_SPI2_NCS0_OFFSET 0x0d9 |
| 223 | #define OMAP2420_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x0da |
| 224 | #define OMAP2420_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x0db |
| 225 | #define OMAP2420_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x0dc |
| 226 | #define OMAP2420_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x0dd |
| 227 | #define OMAP2420_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x0de |
| 228 | #define OMAP2420_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x0df |
| 229 | #define OMAP2420_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x0e0 |
| 230 | #define OMAP2420_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x0e1 |
| 231 | #define OMAP2420_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x0e2 |
| 232 | #define OMAP2420_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x0e3 |
| 233 | #define OMAP2420_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x0e4 |
| 234 | #define OMAP2420_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x0e5 |
| 235 | #define OMAP2420_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x0e6 |
| 236 | #define OMAP2420_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x0e7 |
| 237 | #define OMAP2420_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x0e8 |
| 238 | #define OMAP2420_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x0e9 |
| 239 | #define OMAP2420_CONTROL_PADCONF_TV_CVBS_OFFSET 0x0ea |
| 240 | #define OMAP2420_CONTROL_PADCONF_TV_VREF_OFFSET 0x0eb |
| 241 | #define OMAP2420_CONTROL_PADCONF_TV_RREF_OFFSET 0x0ec |
| 242 | #define OMAP2420_CONTROL_PADCONF_USB0_PUEN_OFFSET 0x0ed |
| 243 | #define OMAP2420_CONTROL_PADCONF_USB0_VP_OFFSET 0x0ee |
| 244 | #define OMAP2420_CONTROL_PADCONF_USB0_VM_OFFSET 0x0ef |
| 245 | #define OMAP2420_CONTROL_PADCONF_USB0_RCV_OFFSET 0x0f0 |
| 246 | #define OMAP2420_CONTROL_PADCONF_USB0_TXEN_OFFSET 0x0f1 |
| 247 | #define OMAP2420_CONTROL_PADCONF_USB0_SE0_OFFSET 0x0f2 |
| 248 | #define OMAP2420_CONTROL_PADCONF_USB0_DAT_OFFSET 0x0f3 |
| 249 | #define OMAP2420_CONTROL_PADCONF_EAC_AC_SCLK_OFFSET 0x0f4 |
| 250 | #define OMAP2420_CONTROL_PADCONF_EAC_AC_FS_OFFSET 0x0f5 |
| 251 | #define OMAP2420_CONTROL_PADCONF_EAC_AC_DIN_OFFSET 0x0f6 |
| 252 | #define OMAP2420_CONTROL_PADCONF_EAC_AC_DOUT_OFFSET 0x0f7 |
| 253 | #define OMAP2420_CONTROL_PADCONF_EAC_AC_MCLK_OFFSET 0x0f8 |
| 254 | #define OMAP2420_CONTROL_PADCONF_EAC_AC_RST_OFFSET 0x0f9 |
| 255 | #define OMAP2420_CONTROL_PADCONF_SYS_NRESPWRON_OFFSET 0x0fa |
| 256 | #define OMAP2420_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x0fb |
| 257 | #define OMAP2420_CONTROL_PADCONF_SYS_NIRQ_OFFSET 0x0fc |
| 258 | #define OMAP2420_CONTROL_PADCONF_SYS_NV_OFFSET 0x0fd |
| 259 | #define OMAP2420_CONTROL_PADCONF_GPIO_119_OFFSET 0x0fe |
| 260 | #define OMAP2420_CONTROL_PADCONF_GPIO_120_OFFSET 0x0ff |
| 261 | #define OMAP2420_CONTROL_PADCONF_GPIO_121_OFFSET 0x100 |
| 262 | #define OMAP2420_CONTROL_PADCONF_GPIO_122_OFFSET 0x101 |
| 263 | #define OMAP2420_CONTROL_PADCONF_SYS_32K_OFFSET 0x102 |
| 264 | #define OMAP2420_CONTROL_PADCONF_SYS_XTALIN_OFFSET 0x103 |
| 265 | #define OMAP2420_CONTROL_PADCONF_SYS_XTALOUT_OFFSET 0x104 |
| 266 | #define OMAP2420_CONTROL_PADCONF_GPIO_36_OFFSET 0x105 |
| 267 | #define OMAP2420_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x106 |
| 268 | #define OMAP2420_CONTROL_PADCONF_SYS_CLKOUT_OFFSET 0x107 |
| 269 | #define OMAP2420_CONTROL_PADCONF_GPIO_6_OFFSET 0x108 |
| 270 | #define OMAP2420_CONTROL_PADCONF_GPIO_124_OFFSET 0x109 |
| 271 | #define OMAP2420_CONTROL_PADCONF_GPIO_125_OFFSET 0x10a |
| 272 | #define OMAP2420_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x10b |
| 273 | #define OMAP2420_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x10c |
| 274 | #define OMAP2420_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x10d |
| 275 | #define OMAP2420_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x10e |
| 276 | #define OMAP2420_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0x10f |
| 277 | #define OMAP2420_CONTROL_PADCONF_JTAG_TMS_OFFSET 0x110 |
| 278 | #define OMAP2420_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x111 |
| 279 | #define OMAP2420_CONTROL_PADCONF_JTAG_TDO_OFFSET 0x112 |
| 280 | |
| 281 | #define OMAP2420_CONTROL_PADCONF_MUX_SIZE \ |
| 282 | (OMAP2420_CONTROL_PADCONF_JTAG_TDO_OFFSET + 0x1) |