blob: c8bca7776b4381b6c58c0959e90a4f487c4922ae [file] [log] [blame]
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001/* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
3 *
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
6 * this source tree.
7 */
8
9#include <linux/types.h>
10#include <asm/byteorder.h>
11#include <linux/io.h>
12#include <linux/bitops.h>
13#include <linux/delay.h>
14#include <linux/dma-mapping.h>
15#include <linux/errno.h>
16#include <linux/interrupt.h>
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/slab.h>
20#include <linux/string.h>
21#include "qed.h"
22#include "qed_hsi.h"
23#include "qed_hw.h"
24#include "qed_init_ops.h"
25#include "qed_int.h"
26#include "qed_mcp.h"
27#include "qed_reg_addr.h"
28#include "qed_sp.h"
29
30struct qed_pi_info {
31 qed_int_comp_cb_t comp_cb;
32 void *cookie;
33};
34
35struct qed_sb_sp_info {
36 struct qed_sb_info sb_info;
37
38 /* per protocol index data */
39 struct qed_pi_info pi_info_arr[PIS_PER_SB];
40};
41
Yuval Mintzff385772016-02-28 12:26:54 +020042enum qed_attention_type {
43 QED_ATTN_TYPE_ATTN,
44 QED_ATTN_TYPE_PARITY,
45};
46
Yuval Mintzcc875c22015-10-26 11:02:31 +020047#define SB_ATTN_ALIGNED_SIZE(p_hwfn) \
48 ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn)
49
Yuval Mintz0d956e82016-02-28 12:26:53 +020050struct aeu_invert_reg_bit {
51 char bit_name[30];
52
53#define ATTENTION_PARITY (1 << 0)
54
55#define ATTENTION_LENGTH_MASK (0x00000ff0)
56#define ATTENTION_LENGTH_SHIFT (4)
57#define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \
58 ATTENTION_LENGTH_SHIFT)
59#define ATTENTION_SINGLE (1 << ATTENTION_LENGTH_SHIFT)
60#define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY)
61#define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \
62 ATTENTION_PARITY)
63
64/* Multiple bits start with this offset */
65#define ATTENTION_OFFSET_MASK (0x000ff000)
66#define ATTENTION_OFFSET_SHIFT (12)
67 unsigned int flags;
Yuval Mintzff385772016-02-28 12:26:54 +020068
69 enum block_id block_index;
Yuval Mintz0d956e82016-02-28 12:26:53 +020070};
71
72struct aeu_invert_reg {
73 struct aeu_invert_reg_bit bits[32];
74};
75
76#define MAX_ATTN_GRPS (8)
77#define NUM_ATTN_REGS (9)
78
Yuval Mintzff385772016-02-28 12:26:54 +020079/* HW Attention register */
80struct attn_hw_reg {
81 u16 reg_idx; /* Index of this register in its block */
82 u16 num_of_bits; /* number of valid attention bits */
83 u32 sts_addr; /* Address of the STS register */
84 u32 sts_clr_addr; /* Address of the STS_CLR register */
85 u32 sts_wr_addr; /* Address of the STS_WR register */
86 u32 mask_addr; /* Address of the MASK register */
87};
88
89/* HW block attention registers */
90struct attn_hw_regs {
91 u16 num_of_int_regs; /* Number of interrupt regs */
92 u16 num_of_prty_regs; /* Number of parity regs */
93 struct attn_hw_reg **int_regs; /* interrupt regs */
94 struct attn_hw_reg **prty_regs; /* parity regs */
95};
96
97/* HW block attention registers */
98struct attn_hw_block {
99 const char *name; /* Block name */
100 struct attn_hw_regs chip_regs[1];
101};
102
103static struct attn_hw_reg grc_int0_bb_b0 = {
104 0, 4, 0x50180, 0x5018c, 0x50188, 0x50184};
105
106static struct attn_hw_reg *grc_int_bb_b0_regs[1] = {
107 &grc_int0_bb_b0};
108
109static struct attn_hw_reg grc_prty1_bb_b0 = {
110 0, 2, 0x50200, 0x5020c, 0x50208, 0x50204};
111
112static struct attn_hw_reg *grc_prty_bb_b0_regs[1] = {
113 &grc_prty1_bb_b0};
114
115static struct attn_hw_reg miscs_int0_bb_b0 = {
116 0, 3, 0x9180, 0x918c, 0x9188, 0x9184};
117
118static struct attn_hw_reg miscs_int1_bb_b0 = {
119 1, 11, 0x9190, 0x919c, 0x9198, 0x9194};
120
121static struct attn_hw_reg *miscs_int_bb_b0_regs[2] = {
122 &miscs_int0_bb_b0, &miscs_int1_bb_b0};
123
124static struct attn_hw_reg miscs_prty0_bb_b0 = {
125 0, 1, 0x91a0, 0x91ac, 0x91a8, 0x91a4};
126
127static struct attn_hw_reg *miscs_prty_bb_b0_regs[1] = {
128 &miscs_prty0_bb_b0};
129
130static struct attn_hw_reg misc_int0_bb_b0 = {
131 0, 1, 0x8180, 0x818c, 0x8188, 0x8184};
132
133static struct attn_hw_reg *misc_int_bb_b0_regs[1] = {
134 &misc_int0_bb_b0};
135
136static struct attn_hw_reg pglue_b_int0_bb_b0 = {
137 0, 23, 0x2a8180, 0x2a818c, 0x2a8188, 0x2a8184};
138
139static struct attn_hw_reg *pglue_b_int_bb_b0_regs[1] = {
140 &pglue_b_int0_bb_b0};
141
142static struct attn_hw_reg pglue_b_prty0_bb_b0 = {
143 0, 1, 0x2a8190, 0x2a819c, 0x2a8198, 0x2a8194};
144
145static struct attn_hw_reg pglue_b_prty1_bb_b0 = {
146 1, 22, 0x2a8200, 0x2a820c, 0x2a8208, 0x2a8204};
147
148static struct attn_hw_reg *pglue_b_prty_bb_b0_regs[2] = {
149 &pglue_b_prty0_bb_b0, &pglue_b_prty1_bb_b0};
150
151static struct attn_hw_reg cnig_int0_bb_b0 = {
152 0, 6, 0x2182e8, 0x2182f4, 0x2182f0, 0x2182ec};
153
154static struct attn_hw_reg *cnig_int_bb_b0_regs[1] = {
155 &cnig_int0_bb_b0};
156
157static struct attn_hw_reg cnig_prty0_bb_b0 = {
158 0, 2, 0x218348, 0x218354, 0x218350, 0x21834c};
159
160static struct attn_hw_reg *cnig_prty_bb_b0_regs[1] = {
161 &cnig_prty0_bb_b0};
162
163static struct attn_hw_reg cpmu_int0_bb_b0 = {
164 0, 1, 0x303e0, 0x303ec, 0x303e8, 0x303e4};
165
166static struct attn_hw_reg *cpmu_int_bb_b0_regs[1] = {
167 &cpmu_int0_bb_b0};
168
169static struct attn_hw_reg ncsi_int0_bb_b0 = {
170 0, 1, 0x404cc, 0x404d8, 0x404d4, 0x404d0};
171
172static struct attn_hw_reg *ncsi_int_bb_b0_regs[1] = {
173 &ncsi_int0_bb_b0};
174
175static struct attn_hw_reg ncsi_prty1_bb_b0 = {
176 0, 1, 0x40000, 0x4000c, 0x40008, 0x40004};
177
178static struct attn_hw_reg *ncsi_prty_bb_b0_regs[1] = {
179 &ncsi_prty1_bb_b0};
180
181static struct attn_hw_reg opte_prty1_bb_b0 = {
182 0, 11, 0x53000, 0x5300c, 0x53008, 0x53004};
183
184static struct attn_hw_reg opte_prty0_bb_b0 = {
185 1, 1, 0x53208, 0x53214, 0x53210, 0x5320c};
186
187static struct attn_hw_reg *opte_prty_bb_b0_regs[2] = {
188 &opte_prty1_bb_b0, &opte_prty0_bb_b0};
189
190static struct attn_hw_reg bmb_int0_bb_b0 = {
191 0, 16, 0x5400c0, 0x5400cc, 0x5400c8, 0x5400c4};
192
193static struct attn_hw_reg bmb_int1_bb_b0 = {
194 1, 28, 0x5400d8, 0x5400e4, 0x5400e0, 0x5400dc};
195
196static struct attn_hw_reg bmb_int2_bb_b0 = {
197 2, 26, 0x5400f0, 0x5400fc, 0x5400f8, 0x5400f4};
198
199static struct attn_hw_reg bmb_int3_bb_b0 = {
200 3, 31, 0x540108, 0x540114, 0x540110, 0x54010c};
201
202static struct attn_hw_reg bmb_int4_bb_b0 = {
203 4, 27, 0x540120, 0x54012c, 0x540128, 0x540124};
204
205static struct attn_hw_reg bmb_int5_bb_b0 = {
206 5, 29, 0x540138, 0x540144, 0x540140, 0x54013c};
207
208static struct attn_hw_reg bmb_int6_bb_b0 = {
209 6, 30, 0x540150, 0x54015c, 0x540158, 0x540154};
210
211static struct attn_hw_reg bmb_int7_bb_b0 = {
212 7, 32, 0x540168, 0x540174, 0x540170, 0x54016c};
213
214static struct attn_hw_reg bmb_int8_bb_b0 = {
215 8, 32, 0x540184, 0x540190, 0x54018c, 0x540188};
216
217static struct attn_hw_reg bmb_int9_bb_b0 = {
218 9, 32, 0x54019c, 0x5401a8, 0x5401a4, 0x5401a0};
219
220static struct attn_hw_reg bmb_int10_bb_b0 = {
221 10, 3, 0x5401b4, 0x5401c0, 0x5401bc, 0x5401b8};
222
223static struct attn_hw_reg bmb_int11_bb_b0 = {
224 11, 4, 0x5401cc, 0x5401d8, 0x5401d4, 0x5401d0};
225
226static struct attn_hw_reg *bmb_int_bb_b0_regs[12] = {
227 &bmb_int0_bb_b0, &bmb_int1_bb_b0, &bmb_int2_bb_b0, &bmb_int3_bb_b0,
228 &bmb_int4_bb_b0, &bmb_int5_bb_b0, &bmb_int6_bb_b0, &bmb_int7_bb_b0,
229 &bmb_int8_bb_b0, &bmb_int9_bb_b0, &bmb_int10_bb_b0, &bmb_int11_bb_b0};
230
231static struct attn_hw_reg bmb_prty0_bb_b0 = {
232 0, 5, 0x5401dc, 0x5401e8, 0x5401e4, 0x5401e0};
233
234static struct attn_hw_reg bmb_prty1_bb_b0 = {
235 1, 31, 0x540400, 0x54040c, 0x540408, 0x540404};
236
237static struct attn_hw_reg bmb_prty2_bb_b0 = {
238 2, 15, 0x540410, 0x54041c, 0x540418, 0x540414};
239
240static struct attn_hw_reg *bmb_prty_bb_b0_regs[3] = {
241 &bmb_prty0_bb_b0, &bmb_prty1_bb_b0, &bmb_prty2_bb_b0};
242
243static struct attn_hw_reg pcie_prty1_bb_b0 = {
244 0, 17, 0x54000, 0x5400c, 0x54008, 0x54004};
245
246static struct attn_hw_reg *pcie_prty_bb_b0_regs[1] = {
247 &pcie_prty1_bb_b0};
248
249static struct attn_hw_reg mcp2_prty0_bb_b0 = {
250 0, 1, 0x52040, 0x5204c, 0x52048, 0x52044};
251
252static struct attn_hw_reg mcp2_prty1_bb_b0 = {
253 1, 12, 0x52204, 0x52210, 0x5220c, 0x52208};
254
255static struct attn_hw_reg *mcp2_prty_bb_b0_regs[2] = {
256 &mcp2_prty0_bb_b0, &mcp2_prty1_bb_b0};
257
258static struct attn_hw_reg pswhst_int0_bb_b0 = {
259 0, 18, 0x2a0180, 0x2a018c, 0x2a0188, 0x2a0184};
260
261static struct attn_hw_reg *pswhst_int_bb_b0_regs[1] = {
262 &pswhst_int0_bb_b0};
263
264static struct attn_hw_reg pswhst_prty0_bb_b0 = {
265 0, 1, 0x2a0190, 0x2a019c, 0x2a0198, 0x2a0194};
266
267static struct attn_hw_reg pswhst_prty1_bb_b0 = {
268 1, 17, 0x2a0200, 0x2a020c, 0x2a0208, 0x2a0204};
269
270static struct attn_hw_reg *pswhst_prty_bb_b0_regs[2] = {
271 &pswhst_prty0_bb_b0, &pswhst_prty1_bb_b0};
272
273static struct attn_hw_reg pswhst2_int0_bb_b0 = {
274 0, 5, 0x29e180, 0x29e18c, 0x29e188, 0x29e184};
275
276static struct attn_hw_reg *pswhst2_int_bb_b0_regs[1] = {
277 &pswhst2_int0_bb_b0};
278
279static struct attn_hw_reg pswhst2_prty0_bb_b0 = {
280 0, 1, 0x29e190, 0x29e19c, 0x29e198, 0x29e194};
281
282static struct attn_hw_reg *pswhst2_prty_bb_b0_regs[1] = {
283 &pswhst2_prty0_bb_b0};
284
285static struct attn_hw_reg pswrd_int0_bb_b0 = {
286 0, 3, 0x29c180, 0x29c18c, 0x29c188, 0x29c184};
287
288static struct attn_hw_reg *pswrd_int_bb_b0_regs[1] = {
289 &pswrd_int0_bb_b0};
290
291static struct attn_hw_reg pswrd_prty0_bb_b0 = {
292 0, 1, 0x29c190, 0x29c19c, 0x29c198, 0x29c194};
293
294static struct attn_hw_reg *pswrd_prty_bb_b0_regs[1] = {
295 &pswrd_prty0_bb_b0};
296
297static struct attn_hw_reg pswrd2_int0_bb_b0 = {
298 0, 5, 0x29d180, 0x29d18c, 0x29d188, 0x29d184};
299
300static struct attn_hw_reg *pswrd2_int_bb_b0_regs[1] = {
301 &pswrd2_int0_bb_b0};
302
303static struct attn_hw_reg pswrd2_prty0_bb_b0 = {
304 0, 1, 0x29d190, 0x29d19c, 0x29d198, 0x29d194};
305
306static struct attn_hw_reg pswrd2_prty1_bb_b0 = {
307 1, 31, 0x29d200, 0x29d20c, 0x29d208, 0x29d204};
308
309static struct attn_hw_reg pswrd2_prty2_bb_b0 = {
310 2, 3, 0x29d210, 0x29d21c, 0x29d218, 0x29d214};
311
312static struct attn_hw_reg *pswrd2_prty_bb_b0_regs[3] = {
313 &pswrd2_prty0_bb_b0, &pswrd2_prty1_bb_b0, &pswrd2_prty2_bb_b0};
314
315static struct attn_hw_reg pswwr_int0_bb_b0 = {
316 0, 16, 0x29a180, 0x29a18c, 0x29a188, 0x29a184};
317
318static struct attn_hw_reg *pswwr_int_bb_b0_regs[1] = {
319 &pswwr_int0_bb_b0};
320
321static struct attn_hw_reg pswwr_prty0_bb_b0 = {
322 0, 1, 0x29a190, 0x29a19c, 0x29a198, 0x29a194};
323
324static struct attn_hw_reg *pswwr_prty_bb_b0_regs[1] = {
325 &pswwr_prty0_bb_b0};
326
327static struct attn_hw_reg pswwr2_int0_bb_b0 = {
328 0, 19, 0x29b180, 0x29b18c, 0x29b188, 0x29b184};
329
330static struct attn_hw_reg *pswwr2_int_bb_b0_regs[1] = {
331 &pswwr2_int0_bb_b0};
332
333static struct attn_hw_reg pswwr2_prty0_bb_b0 = {
334 0, 1, 0x29b190, 0x29b19c, 0x29b198, 0x29b194};
335
336static struct attn_hw_reg pswwr2_prty1_bb_b0 = {
337 1, 31, 0x29b200, 0x29b20c, 0x29b208, 0x29b204};
338
339static struct attn_hw_reg pswwr2_prty2_bb_b0 = {
340 2, 31, 0x29b210, 0x29b21c, 0x29b218, 0x29b214};
341
342static struct attn_hw_reg pswwr2_prty3_bb_b0 = {
343 3, 31, 0x29b220, 0x29b22c, 0x29b228, 0x29b224};
344
345static struct attn_hw_reg pswwr2_prty4_bb_b0 = {
346 4, 20, 0x29b230, 0x29b23c, 0x29b238, 0x29b234};
347
348static struct attn_hw_reg *pswwr2_prty_bb_b0_regs[5] = {
349 &pswwr2_prty0_bb_b0, &pswwr2_prty1_bb_b0, &pswwr2_prty2_bb_b0,
350 &pswwr2_prty3_bb_b0, &pswwr2_prty4_bb_b0};
351
352static struct attn_hw_reg pswrq_int0_bb_b0 = {
353 0, 21, 0x280180, 0x28018c, 0x280188, 0x280184};
354
355static struct attn_hw_reg *pswrq_int_bb_b0_regs[1] = {
356 &pswrq_int0_bb_b0};
357
358static struct attn_hw_reg pswrq_prty0_bb_b0 = {
359 0, 1, 0x280190, 0x28019c, 0x280198, 0x280194};
360
361static struct attn_hw_reg *pswrq_prty_bb_b0_regs[1] = {
362 &pswrq_prty0_bb_b0};
363
364static struct attn_hw_reg pswrq2_int0_bb_b0 = {
365 0, 15, 0x240180, 0x24018c, 0x240188, 0x240184};
366
367static struct attn_hw_reg *pswrq2_int_bb_b0_regs[1] = {
368 &pswrq2_int0_bb_b0};
369
370static struct attn_hw_reg pswrq2_prty1_bb_b0 = {
371 0, 9, 0x240200, 0x24020c, 0x240208, 0x240204};
372
373static struct attn_hw_reg *pswrq2_prty_bb_b0_regs[1] = {
374 &pswrq2_prty1_bb_b0};
375
376static struct attn_hw_reg pglcs_int0_bb_b0 = {
377 0, 1, 0x1d00, 0x1d0c, 0x1d08, 0x1d04};
378
379static struct attn_hw_reg *pglcs_int_bb_b0_regs[1] = {
380 &pglcs_int0_bb_b0};
381
382static struct attn_hw_reg dmae_int0_bb_b0 = {
383 0, 2, 0xc180, 0xc18c, 0xc188, 0xc184};
384
385static struct attn_hw_reg *dmae_int_bb_b0_regs[1] = {
386 &dmae_int0_bb_b0};
387
388static struct attn_hw_reg dmae_prty1_bb_b0 = {
389 0, 3, 0xc200, 0xc20c, 0xc208, 0xc204};
390
391static struct attn_hw_reg *dmae_prty_bb_b0_regs[1] = {
392 &dmae_prty1_bb_b0};
393
394static struct attn_hw_reg ptu_int0_bb_b0 = {
395 0, 8, 0x560180, 0x56018c, 0x560188, 0x560184};
396
397static struct attn_hw_reg *ptu_int_bb_b0_regs[1] = {
398 &ptu_int0_bb_b0};
399
400static struct attn_hw_reg ptu_prty1_bb_b0 = {
401 0, 18, 0x560200, 0x56020c, 0x560208, 0x560204};
402
403static struct attn_hw_reg *ptu_prty_bb_b0_regs[1] = {
404 &ptu_prty1_bb_b0};
405
406static struct attn_hw_reg tcm_int0_bb_b0 = {
407 0, 8, 0x1180180, 0x118018c, 0x1180188, 0x1180184};
408
409static struct attn_hw_reg tcm_int1_bb_b0 = {
410 1, 32, 0x1180190, 0x118019c, 0x1180198, 0x1180194};
411
412static struct attn_hw_reg tcm_int2_bb_b0 = {
413 2, 1, 0x11801a0, 0x11801ac, 0x11801a8, 0x11801a4};
414
415static struct attn_hw_reg *tcm_int_bb_b0_regs[3] = {
416 &tcm_int0_bb_b0, &tcm_int1_bb_b0, &tcm_int2_bb_b0};
417
418static struct attn_hw_reg tcm_prty1_bb_b0 = {
419 0, 31, 0x1180200, 0x118020c, 0x1180208, 0x1180204};
420
421static struct attn_hw_reg tcm_prty2_bb_b0 = {
422 1, 2, 0x1180210, 0x118021c, 0x1180218, 0x1180214};
423
424static struct attn_hw_reg *tcm_prty_bb_b0_regs[2] = {
425 &tcm_prty1_bb_b0, &tcm_prty2_bb_b0};
426
427static struct attn_hw_reg mcm_int0_bb_b0 = {
428 0, 14, 0x1200180, 0x120018c, 0x1200188, 0x1200184};
429
430static struct attn_hw_reg mcm_int1_bb_b0 = {
431 1, 26, 0x1200190, 0x120019c, 0x1200198, 0x1200194};
432
433static struct attn_hw_reg mcm_int2_bb_b0 = {
434 2, 1, 0x12001a0, 0x12001ac, 0x12001a8, 0x12001a4};
435
436static struct attn_hw_reg *mcm_int_bb_b0_regs[3] = {
437 &mcm_int0_bb_b0, &mcm_int1_bb_b0, &mcm_int2_bb_b0};
438
439static struct attn_hw_reg mcm_prty1_bb_b0 = {
440 0, 31, 0x1200200, 0x120020c, 0x1200208, 0x1200204};
441
442static struct attn_hw_reg mcm_prty2_bb_b0 = {
443 1, 4, 0x1200210, 0x120021c, 0x1200218, 0x1200214};
444
445static struct attn_hw_reg *mcm_prty_bb_b0_regs[2] = {
446 &mcm_prty1_bb_b0, &mcm_prty2_bb_b0};
447
448static struct attn_hw_reg ucm_int0_bb_b0 = {
449 0, 17, 0x1280180, 0x128018c, 0x1280188, 0x1280184};
450
451static struct attn_hw_reg ucm_int1_bb_b0 = {
452 1, 29, 0x1280190, 0x128019c, 0x1280198, 0x1280194};
453
454static struct attn_hw_reg ucm_int2_bb_b0 = {
455 2, 1, 0x12801a0, 0x12801ac, 0x12801a8, 0x12801a4};
456
457static struct attn_hw_reg *ucm_int_bb_b0_regs[3] = {
458 &ucm_int0_bb_b0, &ucm_int1_bb_b0, &ucm_int2_bb_b0};
459
460static struct attn_hw_reg ucm_prty1_bb_b0 = {
461 0, 31, 0x1280200, 0x128020c, 0x1280208, 0x1280204};
462
463static struct attn_hw_reg ucm_prty2_bb_b0 = {
464 1, 7, 0x1280210, 0x128021c, 0x1280218, 0x1280214};
465
466static struct attn_hw_reg *ucm_prty_bb_b0_regs[2] = {
467 &ucm_prty1_bb_b0, &ucm_prty2_bb_b0};
468
469static struct attn_hw_reg xcm_int0_bb_b0 = {
470 0, 16, 0x1000180, 0x100018c, 0x1000188, 0x1000184};
471
472static struct attn_hw_reg xcm_int1_bb_b0 = {
473 1, 25, 0x1000190, 0x100019c, 0x1000198, 0x1000194};
474
475static struct attn_hw_reg xcm_int2_bb_b0 = {
476 2, 8, 0x10001a0, 0x10001ac, 0x10001a8, 0x10001a4};
477
478static struct attn_hw_reg *xcm_int_bb_b0_regs[3] = {
479 &xcm_int0_bb_b0, &xcm_int1_bb_b0, &xcm_int2_bb_b0};
480
481static struct attn_hw_reg xcm_prty1_bb_b0 = {
482 0, 31, 0x1000200, 0x100020c, 0x1000208, 0x1000204};
483
484static struct attn_hw_reg xcm_prty2_bb_b0 = {
485 1, 11, 0x1000210, 0x100021c, 0x1000218, 0x1000214};
486
487static struct attn_hw_reg *xcm_prty_bb_b0_regs[2] = {
488 &xcm_prty1_bb_b0, &xcm_prty2_bb_b0};
489
490static struct attn_hw_reg ycm_int0_bb_b0 = {
491 0, 13, 0x1080180, 0x108018c, 0x1080188, 0x1080184};
492
493static struct attn_hw_reg ycm_int1_bb_b0 = {
494 1, 23, 0x1080190, 0x108019c, 0x1080198, 0x1080194};
495
496static struct attn_hw_reg ycm_int2_bb_b0 = {
497 2, 1, 0x10801a0, 0x10801ac, 0x10801a8, 0x10801a4};
498
499static struct attn_hw_reg *ycm_int_bb_b0_regs[3] = {
500 &ycm_int0_bb_b0, &ycm_int1_bb_b0, &ycm_int2_bb_b0};
501
502static struct attn_hw_reg ycm_prty1_bb_b0 = {
503 0, 31, 0x1080200, 0x108020c, 0x1080208, 0x1080204};
504
505static struct attn_hw_reg ycm_prty2_bb_b0 = {
506 1, 3, 0x1080210, 0x108021c, 0x1080218, 0x1080214};
507
508static struct attn_hw_reg *ycm_prty_bb_b0_regs[2] = {
509 &ycm_prty1_bb_b0, &ycm_prty2_bb_b0};
510
511static struct attn_hw_reg pcm_int0_bb_b0 = {
512 0, 5, 0x1100180, 0x110018c, 0x1100188, 0x1100184};
513
514static struct attn_hw_reg pcm_int1_bb_b0 = {
515 1, 14, 0x1100190, 0x110019c, 0x1100198, 0x1100194};
516
517static struct attn_hw_reg pcm_int2_bb_b0 = {
518 2, 1, 0x11001a0, 0x11001ac, 0x11001a8, 0x11001a4};
519
520static struct attn_hw_reg *pcm_int_bb_b0_regs[3] = {
521 &pcm_int0_bb_b0, &pcm_int1_bb_b0, &pcm_int2_bb_b0};
522
523static struct attn_hw_reg pcm_prty1_bb_b0 = {
524 0, 11, 0x1100200, 0x110020c, 0x1100208, 0x1100204};
525
526static struct attn_hw_reg *pcm_prty_bb_b0_regs[1] = {
527 &pcm_prty1_bb_b0};
528
529static struct attn_hw_reg qm_int0_bb_b0 = {
530 0, 22, 0x2f0180, 0x2f018c, 0x2f0188, 0x2f0184};
531
532static struct attn_hw_reg *qm_int_bb_b0_regs[1] = {
533 &qm_int0_bb_b0};
534
535static struct attn_hw_reg qm_prty0_bb_b0 = {
536 0, 11, 0x2f0190, 0x2f019c, 0x2f0198, 0x2f0194};
537
538static struct attn_hw_reg qm_prty1_bb_b0 = {
539 1, 31, 0x2f0200, 0x2f020c, 0x2f0208, 0x2f0204};
540
541static struct attn_hw_reg qm_prty2_bb_b0 = {
542 2, 31, 0x2f0210, 0x2f021c, 0x2f0218, 0x2f0214};
543
544static struct attn_hw_reg qm_prty3_bb_b0 = {
545 3, 11, 0x2f0220, 0x2f022c, 0x2f0228, 0x2f0224};
546
547static struct attn_hw_reg *qm_prty_bb_b0_regs[4] = {
548 &qm_prty0_bb_b0, &qm_prty1_bb_b0, &qm_prty2_bb_b0, &qm_prty3_bb_b0};
549
550static struct attn_hw_reg tm_int0_bb_b0 = {
551 0, 32, 0x2c0180, 0x2c018c, 0x2c0188, 0x2c0184};
552
553static struct attn_hw_reg tm_int1_bb_b0 = {
554 1, 11, 0x2c0190, 0x2c019c, 0x2c0198, 0x2c0194};
555
556static struct attn_hw_reg *tm_int_bb_b0_regs[2] = {
557 &tm_int0_bb_b0, &tm_int1_bb_b0};
558
559static struct attn_hw_reg tm_prty1_bb_b0 = {
560 0, 17, 0x2c0200, 0x2c020c, 0x2c0208, 0x2c0204};
561
562static struct attn_hw_reg *tm_prty_bb_b0_regs[1] = {
563 &tm_prty1_bb_b0};
564
565static struct attn_hw_reg dorq_int0_bb_b0 = {
566 0, 9, 0x100180, 0x10018c, 0x100188, 0x100184};
567
568static struct attn_hw_reg *dorq_int_bb_b0_regs[1] = {
569 &dorq_int0_bb_b0};
570
571static struct attn_hw_reg dorq_prty0_bb_b0 = {
572 0, 1, 0x100190, 0x10019c, 0x100198, 0x100194};
573
574static struct attn_hw_reg dorq_prty1_bb_b0 = {
575 1, 6, 0x100200, 0x10020c, 0x100208, 0x100204};
576
577static struct attn_hw_reg *dorq_prty_bb_b0_regs[2] = {
578 &dorq_prty0_bb_b0, &dorq_prty1_bb_b0};
579
580static struct attn_hw_reg brb_int0_bb_b0 = {
581 0, 32, 0x3400c0, 0x3400cc, 0x3400c8, 0x3400c4};
582
583static struct attn_hw_reg brb_int1_bb_b0 = {
584 1, 30, 0x3400d8, 0x3400e4, 0x3400e0, 0x3400dc};
585
586static struct attn_hw_reg brb_int2_bb_b0 = {
587 2, 28, 0x3400f0, 0x3400fc, 0x3400f8, 0x3400f4};
588
589static struct attn_hw_reg brb_int3_bb_b0 = {
590 3, 31, 0x340108, 0x340114, 0x340110, 0x34010c};
591
592static struct attn_hw_reg brb_int4_bb_b0 = {
593 4, 27, 0x340120, 0x34012c, 0x340128, 0x340124};
594
595static struct attn_hw_reg brb_int5_bb_b0 = {
596 5, 1, 0x340138, 0x340144, 0x340140, 0x34013c};
597
598static struct attn_hw_reg brb_int6_bb_b0 = {
599 6, 8, 0x340150, 0x34015c, 0x340158, 0x340154};
600
601static struct attn_hw_reg brb_int7_bb_b0 = {
602 7, 32, 0x340168, 0x340174, 0x340170, 0x34016c};
603
604static struct attn_hw_reg brb_int8_bb_b0 = {
605 8, 17, 0x340184, 0x340190, 0x34018c, 0x340188};
606
607static struct attn_hw_reg brb_int9_bb_b0 = {
608 9, 1, 0x34019c, 0x3401a8, 0x3401a4, 0x3401a0};
609
610static struct attn_hw_reg brb_int10_bb_b0 = {
611 10, 14, 0x3401b4, 0x3401c0, 0x3401bc, 0x3401b8};
612
613static struct attn_hw_reg brb_int11_bb_b0 = {
614 11, 8, 0x3401cc, 0x3401d8, 0x3401d4, 0x3401d0};
615
616static struct attn_hw_reg *brb_int_bb_b0_regs[12] = {
617 &brb_int0_bb_b0, &brb_int1_bb_b0, &brb_int2_bb_b0, &brb_int3_bb_b0,
618 &brb_int4_bb_b0, &brb_int5_bb_b0, &brb_int6_bb_b0, &brb_int7_bb_b0,
619 &brb_int8_bb_b0, &brb_int9_bb_b0, &brb_int10_bb_b0, &brb_int11_bb_b0};
620
621static struct attn_hw_reg brb_prty0_bb_b0 = {
622 0, 5, 0x3401dc, 0x3401e8, 0x3401e4, 0x3401e0};
623
624static struct attn_hw_reg brb_prty1_bb_b0 = {
625 1, 31, 0x340400, 0x34040c, 0x340408, 0x340404};
626
627static struct attn_hw_reg brb_prty2_bb_b0 = {
628 2, 14, 0x340410, 0x34041c, 0x340418, 0x340414};
629
630static struct attn_hw_reg *brb_prty_bb_b0_regs[3] = {
631 &brb_prty0_bb_b0, &brb_prty1_bb_b0, &brb_prty2_bb_b0};
632
633static struct attn_hw_reg src_int0_bb_b0 = {
634 0, 1, 0x2381d8, 0x2381dc, 0x2381e0, 0x2381e4};
635
636static struct attn_hw_reg *src_int_bb_b0_regs[1] = {
637 &src_int0_bb_b0};
638
639static struct attn_hw_reg prs_int0_bb_b0 = {
640 0, 2, 0x1f0040, 0x1f004c, 0x1f0048, 0x1f0044};
641
642static struct attn_hw_reg *prs_int_bb_b0_regs[1] = {
643 &prs_int0_bb_b0};
644
645static struct attn_hw_reg prs_prty0_bb_b0 = {
646 0, 2, 0x1f0050, 0x1f005c, 0x1f0058, 0x1f0054};
647
648static struct attn_hw_reg prs_prty1_bb_b0 = {
649 1, 31, 0x1f0204, 0x1f0210, 0x1f020c, 0x1f0208};
650
651static struct attn_hw_reg prs_prty2_bb_b0 = {
652 2, 5, 0x1f0214, 0x1f0220, 0x1f021c, 0x1f0218};
653
654static struct attn_hw_reg *prs_prty_bb_b0_regs[3] = {
655 &prs_prty0_bb_b0, &prs_prty1_bb_b0, &prs_prty2_bb_b0};
656
657static struct attn_hw_reg tsdm_int0_bb_b0 = {
658 0, 26, 0xfb0040, 0xfb004c, 0xfb0048, 0xfb0044};
659
660static struct attn_hw_reg *tsdm_int_bb_b0_regs[1] = {
661 &tsdm_int0_bb_b0};
662
663static struct attn_hw_reg tsdm_prty1_bb_b0 = {
664 0, 10, 0xfb0200, 0xfb020c, 0xfb0208, 0xfb0204};
665
666static struct attn_hw_reg *tsdm_prty_bb_b0_regs[1] = {
667 &tsdm_prty1_bb_b0};
668
669static struct attn_hw_reg msdm_int0_bb_b0 = {
670 0, 26, 0xfc0040, 0xfc004c, 0xfc0048, 0xfc0044};
671
672static struct attn_hw_reg *msdm_int_bb_b0_regs[1] = {
673 &msdm_int0_bb_b0};
674
675static struct attn_hw_reg msdm_prty1_bb_b0 = {
676 0, 11, 0xfc0200, 0xfc020c, 0xfc0208, 0xfc0204};
677
678static struct attn_hw_reg *msdm_prty_bb_b0_regs[1] = {
679 &msdm_prty1_bb_b0};
680
681static struct attn_hw_reg usdm_int0_bb_b0 = {
682 0, 26, 0xfd0040, 0xfd004c, 0xfd0048, 0xfd0044};
683
684static struct attn_hw_reg *usdm_int_bb_b0_regs[1] = {
685 &usdm_int0_bb_b0};
686
687static struct attn_hw_reg usdm_prty1_bb_b0 = {
688 0, 10, 0xfd0200, 0xfd020c, 0xfd0208, 0xfd0204};
689
690static struct attn_hw_reg *usdm_prty_bb_b0_regs[1] = {
691 &usdm_prty1_bb_b0};
692
693static struct attn_hw_reg xsdm_int0_bb_b0 = {
694 0, 26, 0xf80040, 0xf8004c, 0xf80048, 0xf80044};
695
696static struct attn_hw_reg *xsdm_int_bb_b0_regs[1] = {
697 &xsdm_int0_bb_b0};
698
699static struct attn_hw_reg xsdm_prty1_bb_b0 = {
700 0, 10, 0xf80200, 0xf8020c, 0xf80208, 0xf80204};
701
702static struct attn_hw_reg *xsdm_prty_bb_b0_regs[1] = {
703 &xsdm_prty1_bb_b0};
704
705static struct attn_hw_reg ysdm_int0_bb_b0 = {
706 0, 26, 0xf90040, 0xf9004c, 0xf90048, 0xf90044};
707
708static struct attn_hw_reg *ysdm_int_bb_b0_regs[1] = {
709 &ysdm_int0_bb_b0};
710
711static struct attn_hw_reg ysdm_prty1_bb_b0 = {
712 0, 9, 0xf90200, 0xf9020c, 0xf90208, 0xf90204};
713
714static struct attn_hw_reg *ysdm_prty_bb_b0_regs[1] = {
715 &ysdm_prty1_bb_b0};
716
717static struct attn_hw_reg psdm_int0_bb_b0 = {
718 0, 26, 0xfa0040, 0xfa004c, 0xfa0048, 0xfa0044};
719
720static struct attn_hw_reg *psdm_int_bb_b0_regs[1] = {
721 &psdm_int0_bb_b0};
722
723static struct attn_hw_reg psdm_prty1_bb_b0 = {
724 0, 9, 0xfa0200, 0xfa020c, 0xfa0208, 0xfa0204};
725
726static struct attn_hw_reg *psdm_prty_bb_b0_regs[1] = {
727 &psdm_prty1_bb_b0};
728
729static struct attn_hw_reg tsem_int0_bb_b0 = {
730 0, 32, 0x1700040, 0x170004c, 0x1700048, 0x1700044};
731
732static struct attn_hw_reg tsem_int1_bb_b0 = {
733 1, 13, 0x1700050, 0x170005c, 0x1700058, 0x1700054};
734
735static struct attn_hw_reg tsem_fast_memory_int0_bb_b0 = {
736 2, 1, 0x1740040, 0x174004c, 0x1740048, 0x1740044};
737
738static struct attn_hw_reg *tsem_int_bb_b0_regs[3] = {
739 &tsem_int0_bb_b0, &tsem_int1_bb_b0, &tsem_fast_memory_int0_bb_b0};
740
741static struct attn_hw_reg tsem_prty0_bb_b0 = {
742 0, 3, 0x17000c8, 0x17000d4, 0x17000d0, 0x17000cc};
743
744static struct attn_hw_reg tsem_prty1_bb_b0 = {
745 1, 6, 0x1700200, 0x170020c, 0x1700208, 0x1700204};
746
747static struct attn_hw_reg tsem_fast_memory_vfc_config_prty1_bb_b0 = {
748 2, 6, 0x174a200, 0x174a20c, 0x174a208, 0x174a204};
749
750static struct attn_hw_reg *tsem_prty_bb_b0_regs[3] = {
751 &tsem_prty0_bb_b0, &tsem_prty1_bb_b0,
752 &tsem_fast_memory_vfc_config_prty1_bb_b0};
753
754static struct attn_hw_reg msem_int0_bb_b0 = {
755 0, 32, 0x1800040, 0x180004c, 0x1800048, 0x1800044};
756
757static struct attn_hw_reg msem_int1_bb_b0 = {
758 1, 13, 0x1800050, 0x180005c, 0x1800058, 0x1800054};
759
760static struct attn_hw_reg msem_fast_memory_int0_bb_b0 = {
761 2, 1, 0x1840040, 0x184004c, 0x1840048, 0x1840044};
762
763static struct attn_hw_reg *msem_int_bb_b0_regs[3] = {
764 &msem_int0_bb_b0, &msem_int1_bb_b0, &msem_fast_memory_int0_bb_b0};
765
766static struct attn_hw_reg msem_prty0_bb_b0 = {
767 0, 3, 0x18000c8, 0x18000d4, 0x18000d0, 0x18000cc};
768
769static struct attn_hw_reg msem_prty1_bb_b0 = {
770 1, 6, 0x1800200, 0x180020c, 0x1800208, 0x1800204};
771
772static struct attn_hw_reg *msem_prty_bb_b0_regs[2] = {
773 &msem_prty0_bb_b0, &msem_prty1_bb_b0};
774
775static struct attn_hw_reg usem_int0_bb_b0 = {
776 0, 32, 0x1900040, 0x190004c, 0x1900048, 0x1900044};
777
778static struct attn_hw_reg usem_int1_bb_b0 = {
779 1, 13, 0x1900050, 0x190005c, 0x1900058, 0x1900054};
780
781static struct attn_hw_reg usem_fast_memory_int0_bb_b0 = {
782 2, 1, 0x1940040, 0x194004c, 0x1940048, 0x1940044};
783
784static struct attn_hw_reg *usem_int_bb_b0_regs[3] = {
785 &usem_int0_bb_b0, &usem_int1_bb_b0, &usem_fast_memory_int0_bb_b0};
786
787static struct attn_hw_reg usem_prty0_bb_b0 = {
788 0, 3, 0x19000c8, 0x19000d4, 0x19000d0, 0x19000cc};
789
790static struct attn_hw_reg usem_prty1_bb_b0 = {
791 1, 6, 0x1900200, 0x190020c, 0x1900208, 0x1900204};
792
793static struct attn_hw_reg *usem_prty_bb_b0_regs[2] = {
794 &usem_prty0_bb_b0, &usem_prty1_bb_b0};
795
796static struct attn_hw_reg xsem_int0_bb_b0 = {
797 0, 32, 0x1400040, 0x140004c, 0x1400048, 0x1400044};
798
799static struct attn_hw_reg xsem_int1_bb_b0 = {
800 1, 13, 0x1400050, 0x140005c, 0x1400058, 0x1400054};
801
802static struct attn_hw_reg xsem_fast_memory_int0_bb_b0 = {
803 2, 1, 0x1440040, 0x144004c, 0x1440048, 0x1440044};
804
805static struct attn_hw_reg *xsem_int_bb_b0_regs[3] = {
806 &xsem_int0_bb_b0, &xsem_int1_bb_b0, &xsem_fast_memory_int0_bb_b0};
807
808static struct attn_hw_reg xsem_prty0_bb_b0 = {
809 0, 3, 0x14000c8, 0x14000d4, 0x14000d0, 0x14000cc};
810
811static struct attn_hw_reg xsem_prty1_bb_b0 = {
812 1, 7, 0x1400200, 0x140020c, 0x1400208, 0x1400204};
813
814static struct attn_hw_reg *xsem_prty_bb_b0_regs[2] = {
815 &xsem_prty0_bb_b0, &xsem_prty1_bb_b0};
816
817static struct attn_hw_reg ysem_int0_bb_b0 = {
818 0, 32, 0x1500040, 0x150004c, 0x1500048, 0x1500044};
819
820static struct attn_hw_reg ysem_int1_bb_b0 = {
821 1, 13, 0x1500050, 0x150005c, 0x1500058, 0x1500054};
822
823static struct attn_hw_reg ysem_fast_memory_int0_bb_b0 = {
824 2, 1, 0x1540040, 0x154004c, 0x1540048, 0x1540044};
825
826static struct attn_hw_reg *ysem_int_bb_b0_regs[3] = {
827 &ysem_int0_bb_b0, &ysem_int1_bb_b0, &ysem_fast_memory_int0_bb_b0};
828
829static struct attn_hw_reg ysem_prty0_bb_b0 = {
830 0, 3, 0x15000c8, 0x15000d4, 0x15000d0, 0x15000cc};
831
832static struct attn_hw_reg ysem_prty1_bb_b0 = {
833 1, 7, 0x1500200, 0x150020c, 0x1500208, 0x1500204};
834
835static struct attn_hw_reg *ysem_prty_bb_b0_regs[2] = {
836 &ysem_prty0_bb_b0, &ysem_prty1_bb_b0};
837
838static struct attn_hw_reg psem_int0_bb_b0 = {
839 0, 32, 0x1600040, 0x160004c, 0x1600048, 0x1600044};
840
841static struct attn_hw_reg psem_int1_bb_b0 = {
842 1, 13, 0x1600050, 0x160005c, 0x1600058, 0x1600054};
843
844static struct attn_hw_reg psem_fast_memory_int0_bb_b0 = {
845 2, 1, 0x1640040, 0x164004c, 0x1640048, 0x1640044};
846
847static struct attn_hw_reg *psem_int_bb_b0_regs[3] = {
848 &psem_int0_bb_b0, &psem_int1_bb_b0, &psem_fast_memory_int0_bb_b0};
849
850static struct attn_hw_reg psem_prty0_bb_b0 = {
851 0, 3, 0x16000c8, 0x16000d4, 0x16000d0, 0x16000cc};
852
853static struct attn_hw_reg psem_prty1_bb_b0 = {
854 1, 6, 0x1600200, 0x160020c, 0x1600208, 0x1600204};
855
856static struct attn_hw_reg psem_fast_memory_vfc_config_prty1_bb_b0 = {
857 2, 6, 0x164a200, 0x164a20c, 0x164a208, 0x164a204};
858
859static struct attn_hw_reg *psem_prty_bb_b0_regs[3] = {
860 &psem_prty0_bb_b0, &psem_prty1_bb_b0,
861 &psem_fast_memory_vfc_config_prty1_bb_b0};
862
863static struct attn_hw_reg rss_int0_bb_b0 = {
864 0, 12, 0x238980, 0x23898c, 0x238988, 0x238984};
865
866static struct attn_hw_reg *rss_int_bb_b0_regs[1] = {
867 &rss_int0_bb_b0};
868
869static struct attn_hw_reg rss_prty1_bb_b0 = {
870 0, 4, 0x238a00, 0x238a0c, 0x238a08, 0x238a04};
871
872static struct attn_hw_reg *rss_prty_bb_b0_regs[1] = {
873 &rss_prty1_bb_b0};
874
875static struct attn_hw_reg tmld_int0_bb_b0 = {
876 0, 6, 0x4d0180, 0x4d018c, 0x4d0188, 0x4d0184};
877
878static struct attn_hw_reg *tmld_int_bb_b0_regs[1] = {
879 &tmld_int0_bb_b0};
880
881static struct attn_hw_reg tmld_prty1_bb_b0 = {
882 0, 8, 0x4d0200, 0x4d020c, 0x4d0208, 0x4d0204};
883
884static struct attn_hw_reg *tmld_prty_bb_b0_regs[1] = {
885 &tmld_prty1_bb_b0};
886
887static struct attn_hw_reg muld_int0_bb_b0 = {
888 0, 6, 0x4e0180, 0x4e018c, 0x4e0188, 0x4e0184};
889
890static struct attn_hw_reg *muld_int_bb_b0_regs[1] = {
891 &muld_int0_bb_b0};
892
893static struct attn_hw_reg muld_prty1_bb_b0 = {
894 0, 10, 0x4e0200, 0x4e020c, 0x4e0208, 0x4e0204};
895
896static struct attn_hw_reg *muld_prty_bb_b0_regs[1] = {
897 &muld_prty1_bb_b0};
898
899static struct attn_hw_reg yuld_int0_bb_b0 = {
900 0, 6, 0x4c8180, 0x4c818c, 0x4c8188, 0x4c8184};
901
902static struct attn_hw_reg *yuld_int_bb_b0_regs[1] = {
903 &yuld_int0_bb_b0};
904
905static struct attn_hw_reg yuld_prty1_bb_b0 = {
906 0, 6, 0x4c8200, 0x4c820c, 0x4c8208, 0x4c8204};
907
908static struct attn_hw_reg *yuld_prty_bb_b0_regs[1] = {
909 &yuld_prty1_bb_b0};
910
911static struct attn_hw_reg xyld_int0_bb_b0 = {
912 0, 6, 0x4c0180, 0x4c018c, 0x4c0188, 0x4c0184};
913
914static struct attn_hw_reg *xyld_int_bb_b0_regs[1] = {
915 &xyld_int0_bb_b0};
916
917static struct attn_hw_reg xyld_prty1_bb_b0 = {
918 0, 9, 0x4c0200, 0x4c020c, 0x4c0208, 0x4c0204};
919
920static struct attn_hw_reg *xyld_prty_bb_b0_regs[1] = {
921 &xyld_prty1_bb_b0};
922
923static struct attn_hw_reg prm_int0_bb_b0 = {
924 0, 11, 0x230040, 0x23004c, 0x230048, 0x230044};
925
926static struct attn_hw_reg *prm_int_bb_b0_regs[1] = {
927 &prm_int0_bb_b0};
928
929static struct attn_hw_reg prm_prty0_bb_b0 = {
930 0, 1, 0x230050, 0x23005c, 0x230058, 0x230054};
931
932static struct attn_hw_reg prm_prty1_bb_b0 = {
933 1, 24, 0x230200, 0x23020c, 0x230208, 0x230204};
934
935static struct attn_hw_reg *prm_prty_bb_b0_regs[2] = {
936 &prm_prty0_bb_b0, &prm_prty1_bb_b0};
937
938static struct attn_hw_reg pbf_pb1_int0_bb_b0 = {
939 0, 9, 0xda0040, 0xda004c, 0xda0048, 0xda0044};
940
941static struct attn_hw_reg *pbf_pb1_int_bb_b0_regs[1] = {
942 &pbf_pb1_int0_bb_b0};
943
944static struct attn_hw_reg pbf_pb1_prty0_bb_b0 = {
945 0, 1, 0xda0050, 0xda005c, 0xda0058, 0xda0054};
946
947static struct attn_hw_reg *pbf_pb1_prty_bb_b0_regs[1] = {
948 &pbf_pb1_prty0_bb_b0};
949
950static struct attn_hw_reg pbf_pb2_int0_bb_b0 = {
951 0, 9, 0xda4040, 0xda404c, 0xda4048, 0xda4044};
952
953static struct attn_hw_reg *pbf_pb2_int_bb_b0_regs[1] = {
954 &pbf_pb2_int0_bb_b0};
955
956static struct attn_hw_reg pbf_pb2_prty0_bb_b0 = {
957 0, 1, 0xda4050, 0xda405c, 0xda4058, 0xda4054};
958
959static struct attn_hw_reg *pbf_pb2_prty_bb_b0_regs[1] = {
960 &pbf_pb2_prty0_bb_b0};
961
962static struct attn_hw_reg rpb_int0_bb_b0 = {
963 0, 9, 0x23c040, 0x23c04c, 0x23c048, 0x23c044};
964
965static struct attn_hw_reg *rpb_int_bb_b0_regs[1] = {
966 &rpb_int0_bb_b0};
967
968static struct attn_hw_reg rpb_prty0_bb_b0 = {
969 0, 1, 0x23c050, 0x23c05c, 0x23c058, 0x23c054};
970
971static struct attn_hw_reg *rpb_prty_bb_b0_regs[1] = {
972 &rpb_prty0_bb_b0};
973
974static struct attn_hw_reg btb_int0_bb_b0 = {
975 0, 16, 0xdb00c0, 0xdb00cc, 0xdb00c8, 0xdb00c4};
976
977static struct attn_hw_reg btb_int1_bb_b0 = {
978 1, 16, 0xdb00d8, 0xdb00e4, 0xdb00e0, 0xdb00dc};
979
980static struct attn_hw_reg btb_int2_bb_b0 = {
981 2, 4, 0xdb00f0, 0xdb00fc, 0xdb00f8, 0xdb00f4};
982
983static struct attn_hw_reg btb_int3_bb_b0 = {
984 3, 32, 0xdb0108, 0xdb0114, 0xdb0110, 0xdb010c};
985
986static struct attn_hw_reg btb_int4_bb_b0 = {
987 4, 23, 0xdb0120, 0xdb012c, 0xdb0128, 0xdb0124};
988
989static struct attn_hw_reg btb_int5_bb_b0 = {
990 5, 32, 0xdb0138, 0xdb0144, 0xdb0140, 0xdb013c};
991
992static struct attn_hw_reg btb_int6_bb_b0 = {
993 6, 1, 0xdb0150, 0xdb015c, 0xdb0158, 0xdb0154};
994
995static struct attn_hw_reg btb_int8_bb_b0 = {
996 7, 1, 0xdb0184, 0xdb0190, 0xdb018c, 0xdb0188};
997
998static struct attn_hw_reg btb_int9_bb_b0 = {
999 8, 1, 0xdb019c, 0xdb01a8, 0xdb01a4, 0xdb01a0};
1000
1001static struct attn_hw_reg btb_int10_bb_b0 = {
1002 9, 1, 0xdb01b4, 0xdb01c0, 0xdb01bc, 0xdb01b8};
1003
1004static struct attn_hw_reg btb_int11_bb_b0 = {
1005 10, 2, 0xdb01cc, 0xdb01d8, 0xdb01d4, 0xdb01d0};
1006
1007static struct attn_hw_reg *btb_int_bb_b0_regs[11] = {
1008 &btb_int0_bb_b0, &btb_int1_bb_b0, &btb_int2_bb_b0, &btb_int3_bb_b0,
1009 &btb_int4_bb_b0, &btb_int5_bb_b0, &btb_int6_bb_b0, &btb_int8_bb_b0,
1010 &btb_int9_bb_b0, &btb_int10_bb_b0, &btb_int11_bb_b0};
1011
1012static struct attn_hw_reg btb_prty0_bb_b0 = {
1013 0, 5, 0xdb01dc, 0xdb01e8, 0xdb01e4, 0xdb01e0};
1014
1015static struct attn_hw_reg btb_prty1_bb_b0 = {
1016 1, 23, 0xdb0400, 0xdb040c, 0xdb0408, 0xdb0404};
1017
1018static struct attn_hw_reg *btb_prty_bb_b0_regs[2] = {
1019 &btb_prty0_bb_b0, &btb_prty1_bb_b0};
1020
1021static struct attn_hw_reg pbf_int0_bb_b0 = {
1022 0, 1, 0xd80180, 0xd8018c, 0xd80188, 0xd80184};
1023
1024static struct attn_hw_reg *pbf_int_bb_b0_regs[1] = {
1025 &pbf_int0_bb_b0};
1026
1027static struct attn_hw_reg pbf_prty0_bb_b0 = {
1028 0, 1, 0xd80190, 0xd8019c, 0xd80198, 0xd80194};
1029
1030static struct attn_hw_reg pbf_prty1_bb_b0 = {
1031 1, 31, 0xd80200, 0xd8020c, 0xd80208, 0xd80204};
1032
1033static struct attn_hw_reg pbf_prty2_bb_b0 = {
1034 2, 27, 0xd80210, 0xd8021c, 0xd80218, 0xd80214};
1035
1036static struct attn_hw_reg *pbf_prty_bb_b0_regs[3] = {
1037 &pbf_prty0_bb_b0, &pbf_prty1_bb_b0, &pbf_prty2_bb_b0};
1038
1039static struct attn_hw_reg rdif_int0_bb_b0 = {
1040 0, 8, 0x300180, 0x30018c, 0x300188, 0x300184};
1041
1042static struct attn_hw_reg *rdif_int_bb_b0_regs[1] = {
1043 &rdif_int0_bb_b0};
1044
1045static struct attn_hw_reg rdif_prty0_bb_b0 = {
1046 0, 1, 0x300190, 0x30019c, 0x300198, 0x300194};
1047
1048static struct attn_hw_reg *rdif_prty_bb_b0_regs[1] = {
1049 &rdif_prty0_bb_b0};
1050
1051static struct attn_hw_reg tdif_int0_bb_b0 = {
1052 0, 8, 0x310180, 0x31018c, 0x310188, 0x310184};
1053
1054static struct attn_hw_reg *tdif_int_bb_b0_regs[1] = {
1055 &tdif_int0_bb_b0};
1056
1057static struct attn_hw_reg tdif_prty0_bb_b0 = {
1058 0, 1, 0x310190, 0x31019c, 0x310198, 0x310194};
1059
1060static struct attn_hw_reg tdif_prty1_bb_b0 = {
1061 1, 11, 0x310200, 0x31020c, 0x310208, 0x310204};
1062
1063static struct attn_hw_reg *tdif_prty_bb_b0_regs[2] = {
1064 &tdif_prty0_bb_b0, &tdif_prty1_bb_b0};
1065
1066static struct attn_hw_reg cdu_int0_bb_b0 = {
1067 0, 8, 0x5801c0, 0x5801c4, 0x5801c8, 0x5801cc};
1068
1069static struct attn_hw_reg *cdu_int_bb_b0_regs[1] = {
1070 &cdu_int0_bb_b0};
1071
1072static struct attn_hw_reg cdu_prty1_bb_b0 = {
1073 0, 5, 0x580200, 0x58020c, 0x580208, 0x580204};
1074
1075static struct attn_hw_reg *cdu_prty_bb_b0_regs[1] = {
1076 &cdu_prty1_bb_b0};
1077
1078static struct attn_hw_reg ccfc_int0_bb_b0 = {
1079 0, 2, 0x2e0180, 0x2e018c, 0x2e0188, 0x2e0184};
1080
1081static struct attn_hw_reg *ccfc_int_bb_b0_regs[1] = {
1082 &ccfc_int0_bb_b0};
1083
1084static struct attn_hw_reg ccfc_prty1_bb_b0 = {
1085 0, 2, 0x2e0200, 0x2e020c, 0x2e0208, 0x2e0204};
1086
1087static struct attn_hw_reg ccfc_prty0_bb_b0 = {
1088 1, 6, 0x2e05e4, 0x2e05f0, 0x2e05ec, 0x2e05e8};
1089
1090static struct attn_hw_reg *ccfc_prty_bb_b0_regs[2] = {
1091 &ccfc_prty1_bb_b0, &ccfc_prty0_bb_b0};
1092
1093static struct attn_hw_reg tcfc_int0_bb_b0 = {
1094 0, 2, 0x2d0180, 0x2d018c, 0x2d0188, 0x2d0184};
1095
1096static struct attn_hw_reg *tcfc_int_bb_b0_regs[1] = {
1097 &tcfc_int0_bb_b0};
1098
1099static struct attn_hw_reg tcfc_prty1_bb_b0 = {
1100 0, 2, 0x2d0200, 0x2d020c, 0x2d0208, 0x2d0204};
1101
1102static struct attn_hw_reg tcfc_prty0_bb_b0 = {
1103 1, 6, 0x2d05e4, 0x2d05f0, 0x2d05ec, 0x2d05e8};
1104
1105static struct attn_hw_reg *tcfc_prty_bb_b0_regs[2] = {
1106 &tcfc_prty1_bb_b0, &tcfc_prty0_bb_b0};
1107
1108static struct attn_hw_reg igu_int0_bb_b0 = {
1109 0, 11, 0x180180, 0x18018c, 0x180188, 0x180184};
1110
1111static struct attn_hw_reg *igu_int_bb_b0_regs[1] = {
1112 &igu_int0_bb_b0};
1113
1114static struct attn_hw_reg igu_prty0_bb_b0 = {
1115 0, 1, 0x180190, 0x18019c, 0x180198, 0x180194};
1116
1117static struct attn_hw_reg igu_prty1_bb_b0 = {
1118 1, 31, 0x180200, 0x18020c, 0x180208, 0x180204};
1119
1120static struct attn_hw_reg igu_prty2_bb_b0 = {
1121 2, 1, 0x180210, 0x18021c, 0x180218, 0x180214};
1122
1123static struct attn_hw_reg *igu_prty_bb_b0_regs[3] = {
1124 &igu_prty0_bb_b0, &igu_prty1_bb_b0, &igu_prty2_bb_b0};
1125
1126static struct attn_hw_reg cau_int0_bb_b0 = {
1127 0, 11, 0x1c00d4, 0x1c00d8, 0x1c00dc, 0x1c00e0};
1128
1129static struct attn_hw_reg *cau_int_bb_b0_regs[1] = {
1130 &cau_int0_bb_b0};
1131
1132static struct attn_hw_reg cau_prty1_bb_b0 = {
1133 0, 13, 0x1c0200, 0x1c020c, 0x1c0208, 0x1c0204};
1134
1135static struct attn_hw_reg *cau_prty_bb_b0_regs[1] = {
1136 &cau_prty1_bb_b0};
1137
1138static struct attn_hw_reg dbg_int0_bb_b0 = {
1139 0, 1, 0x10180, 0x1018c, 0x10188, 0x10184};
1140
1141static struct attn_hw_reg *dbg_int_bb_b0_regs[1] = {
1142 &dbg_int0_bb_b0};
1143
1144static struct attn_hw_reg dbg_prty1_bb_b0 = {
1145 0, 1, 0x10200, 0x1020c, 0x10208, 0x10204};
1146
1147static struct attn_hw_reg *dbg_prty_bb_b0_regs[1] = {
1148 &dbg_prty1_bb_b0};
1149
1150static struct attn_hw_reg nig_int0_bb_b0 = {
1151 0, 12, 0x500040, 0x50004c, 0x500048, 0x500044};
1152
1153static struct attn_hw_reg nig_int1_bb_b0 = {
1154 1, 32, 0x500050, 0x50005c, 0x500058, 0x500054};
1155
1156static struct attn_hw_reg nig_int2_bb_b0 = {
1157 2, 20, 0x500060, 0x50006c, 0x500068, 0x500064};
1158
1159static struct attn_hw_reg nig_int3_bb_b0 = {
1160 3, 18, 0x500070, 0x50007c, 0x500078, 0x500074};
1161
1162static struct attn_hw_reg nig_int4_bb_b0 = {
1163 4, 20, 0x500080, 0x50008c, 0x500088, 0x500084};
1164
1165static struct attn_hw_reg nig_int5_bb_b0 = {
1166 5, 18, 0x500090, 0x50009c, 0x500098, 0x500094};
1167
1168static struct attn_hw_reg *nig_int_bb_b0_regs[6] = {
1169 &nig_int0_bb_b0, &nig_int1_bb_b0, &nig_int2_bb_b0, &nig_int3_bb_b0,
1170 &nig_int4_bb_b0, &nig_int5_bb_b0};
1171
1172static struct attn_hw_reg nig_prty0_bb_b0 = {
1173 0, 1, 0x5000a0, 0x5000ac, 0x5000a8, 0x5000a4};
1174
1175static struct attn_hw_reg nig_prty1_bb_b0 = {
1176 1, 31, 0x500200, 0x50020c, 0x500208, 0x500204};
1177
1178static struct attn_hw_reg nig_prty2_bb_b0 = {
1179 2, 31, 0x500210, 0x50021c, 0x500218, 0x500214};
1180
1181static struct attn_hw_reg nig_prty3_bb_b0 = {
1182 3, 31, 0x500220, 0x50022c, 0x500228, 0x500224};
1183
1184static struct attn_hw_reg nig_prty4_bb_b0 = {
1185 4, 17, 0x500230, 0x50023c, 0x500238, 0x500234};
1186
1187static struct attn_hw_reg *nig_prty_bb_b0_regs[5] = {
1188 &nig_prty0_bb_b0, &nig_prty1_bb_b0, &nig_prty2_bb_b0,
1189 &nig_prty3_bb_b0, &nig_prty4_bb_b0};
1190
1191static struct attn_hw_reg ipc_int0_bb_b0 = {
1192 0, 13, 0x2050c, 0x20518, 0x20514, 0x20510};
1193
1194static struct attn_hw_reg *ipc_int_bb_b0_regs[1] = {
1195 &ipc_int0_bb_b0};
1196
1197static struct attn_hw_reg ipc_prty0_bb_b0 = {
1198 0, 1, 0x2051c, 0x20528, 0x20524, 0x20520};
1199
1200static struct attn_hw_reg *ipc_prty_bb_b0_regs[1] = {
1201 &ipc_prty0_bb_b0};
1202
1203static struct attn_hw_block attn_blocks[] = {
1204 {"grc", {{1, 1, grc_int_bb_b0_regs, grc_prty_bb_b0_regs} } },
1205 {"miscs", {{2, 1, miscs_int_bb_b0_regs, miscs_prty_bb_b0_regs} } },
1206 {"misc", {{1, 0, misc_int_bb_b0_regs, NULL} } },
1207 {"dbu", {{0, 0, NULL, NULL} } },
1208 {"pglue_b", {{1, 2, pglue_b_int_bb_b0_regs,
1209 pglue_b_prty_bb_b0_regs} } },
1210 {"cnig", {{1, 1, cnig_int_bb_b0_regs, cnig_prty_bb_b0_regs} } },
1211 {"cpmu", {{1, 0, cpmu_int_bb_b0_regs, NULL} } },
1212 {"ncsi", {{1, 1, ncsi_int_bb_b0_regs, ncsi_prty_bb_b0_regs} } },
1213 {"opte", {{0, 2, NULL, opte_prty_bb_b0_regs} } },
1214 {"bmb", {{12, 3, bmb_int_bb_b0_regs, bmb_prty_bb_b0_regs} } },
1215 {"pcie", {{0, 1, NULL, pcie_prty_bb_b0_regs} } },
1216 {"mcp", {{0, 0, NULL, NULL} } },
1217 {"mcp2", {{0, 2, NULL, mcp2_prty_bb_b0_regs} } },
1218 {"pswhst", {{1, 2, pswhst_int_bb_b0_regs, pswhst_prty_bb_b0_regs} } },
1219 {"pswhst2", {{1, 1, pswhst2_int_bb_b0_regs,
1220 pswhst2_prty_bb_b0_regs} } },
1221 {"pswrd", {{1, 1, pswrd_int_bb_b0_regs, pswrd_prty_bb_b0_regs} } },
1222 {"pswrd2", {{1, 3, pswrd2_int_bb_b0_regs, pswrd2_prty_bb_b0_regs} } },
1223 {"pswwr", {{1, 1, pswwr_int_bb_b0_regs, pswwr_prty_bb_b0_regs} } },
1224 {"pswwr2", {{1, 5, pswwr2_int_bb_b0_regs, pswwr2_prty_bb_b0_regs} } },
1225 {"pswrq", {{1, 1, pswrq_int_bb_b0_regs, pswrq_prty_bb_b0_regs} } },
1226 {"pswrq2", {{1, 1, pswrq2_int_bb_b0_regs, pswrq2_prty_bb_b0_regs} } },
1227 {"pglcs", {{1, 0, pglcs_int_bb_b0_regs, NULL} } },
1228 {"dmae", {{1, 1, dmae_int_bb_b0_regs, dmae_prty_bb_b0_regs} } },
1229 {"ptu", {{1, 1, ptu_int_bb_b0_regs, ptu_prty_bb_b0_regs} } },
1230 {"tcm", {{3, 2, tcm_int_bb_b0_regs, tcm_prty_bb_b0_regs} } },
1231 {"mcm", {{3, 2, mcm_int_bb_b0_regs, mcm_prty_bb_b0_regs} } },
1232 {"ucm", {{3, 2, ucm_int_bb_b0_regs, ucm_prty_bb_b0_regs} } },
1233 {"xcm", {{3, 2, xcm_int_bb_b0_regs, xcm_prty_bb_b0_regs} } },
1234 {"ycm", {{3, 2, ycm_int_bb_b0_regs, ycm_prty_bb_b0_regs} } },
1235 {"pcm", {{3, 1, pcm_int_bb_b0_regs, pcm_prty_bb_b0_regs} } },
1236 {"qm", {{1, 4, qm_int_bb_b0_regs, qm_prty_bb_b0_regs} } },
1237 {"tm", {{2, 1, tm_int_bb_b0_regs, tm_prty_bb_b0_regs} } },
1238 {"dorq", {{1, 2, dorq_int_bb_b0_regs, dorq_prty_bb_b0_regs} } },
1239 {"brb", {{12, 3, brb_int_bb_b0_regs, brb_prty_bb_b0_regs} } },
1240 {"src", {{1, 0, src_int_bb_b0_regs, NULL} } },
1241 {"prs", {{1, 3, prs_int_bb_b0_regs, prs_prty_bb_b0_regs} } },
1242 {"tsdm", {{1, 1, tsdm_int_bb_b0_regs, tsdm_prty_bb_b0_regs} } },
1243 {"msdm", {{1, 1, msdm_int_bb_b0_regs, msdm_prty_bb_b0_regs} } },
1244 {"usdm", {{1, 1, usdm_int_bb_b0_regs, usdm_prty_bb_b0_regs} } },
1245 {"xsdm", {{1, 1, xsdm_int_bb_b0_regs, xsdm_prty_bb_b0_regs} } },
1246 {"ysdm", {{1, 1, ysdm_int_bb_b0_regs, ysdm_prty_bb_b0_regs} } },
1247 {"psdm", {{1, 1, psdm_int_bb_b0_regs, psdm_prty_bb_b0_regs} } },
1248 {"tsem", {{3, 3, tsem_int_bb_b0_regs, tsem_prty_bb_b0_regs} } },
1249 {"msem", {{3, 2, msem_int_bb_b0_regs, msem_prty_bb_b0_regs} } },
1250 {"usem", {{3, 2, usem_int_bb_b0_regs, usem_prty_bb_b0_regs} } },
1251 {"xsem", {{3, 2, xsem_int_bb_b0_regs, xsem_prty_bb_b0_regs} } },
1252 {"ysem", {{3, 2, ysem_int_bb_b0_regs, ysem_prty_bb_b0_regs} } },
1253 {"psem", {{3, 3, psem_int_bb_b0_regs, psem_prty_bb_b0_regs} } },
1254 {"rss", {{1, 1, rss_int_bb_b0_regs, rss_prty_bb_b0_regs} } },
1255 {"tmld", {{1, 1, tmld_int_bb_b0_regs, tmld_prty_bb_b0_regs} } },
1256 {"muld", {{1, 1, muld_int_bb_b0_regs, muld_prty_bb_b0_regs} } },
1257 {"yuld", {{1, 1, yuld_int_bb_b0_regs, yuld_prty_bb_b0_regs} } },
1258 {"xyld", {{1, 1, xyld_int_bb_b0_regs, xyld_prty_bb_b0_regs} } },
1259 {"prm", {{1, 2, prm_int_bb_b0_regs, prm_prty_bb_b0_regs} } },
1260 {"pbf_pb1", {{1, 1, pbf_pb1_int_bb_b0_regs,
1261 pbf_pb1_prty_bb_b0_regs} } },
1262 {"pbf_pb2", {{1, 1, pbf_pb2_int_bb_b0_regs,
1263 pbf_pb2_prty_bb_b0_regs} } },
1264 {"rpb", { {1, 1, rpb_int_bb_b0_regs, rpb_prty_bb_b0_regs} } },
1265 {"btb", { {11, 2, btb_int_bb_b0_regs, btb_prty_bb_b0_regs} } },
1266 {"pbf", { {1, 3, pbf_int_bb_b0_regs, pbf_prty_bb_b0_regs} } },
1267 {"rdif", { {1, 1, rdif_int_bb_b0_regs, rdif_prty_bb_b0_regs} } },
1268 {"tdif", { {1, 2, tdif_int_bb_b0_regs, tdif_prty_bb_b0_regs} } },
1269 {"cdu", { {1, 1, cdu_int_bb_b0_regs, cdu_prty_bb_b0_regs} } },
1270 {"ccfc", { {1, 2, ccfc_int_bb_b0_regs, ccfc_prty_bb_b0_regs} } },
1271 {"tcfc", { {1, 2, tcfc_int_bb_b0_regs, tcfc_prty_bb_b0_regs} } },
1272 {"igu", { {1, 3, igu_int_bb_b0_regs, igu_prty_bb_b0_regs} } },
1273 {"cau", { {1, 1, cau_int_bb_b0_regs, cau_prty_bb_b0_regs} } },
1274 {"umac", { {0, 0, NULL, NULL} } },
1275 {"xmac", { {0, 0, NULL, NULL} } },
1276 {"dbg", { {1, 1, dbg_int_bb_b0_regs, dbg_prty_bb_b0_regs} } },
1277 {"nig", { {6, 5, nig_int_bb_b0_regs, nig_prty_bb_b0_regs} } },
1278 {"wol", { {0, 0, NULL, NULL} } },
1279 {"bmbn", { {0, 0, NULL, NULL} } },
1280 {"ipc", { {1, 1, ipc_int_bb_b0_regs, ipc_prty_bb_b0_regs} } },
1281 {"nwm", { {0, 0, NULL, NULL} } },
1282 {"nws", { {0, 0, NULL, NULL} } },
1283 {"ms", { {0, 0, NULL, NULL} } },
1284 {"phy_pcie", { {0, 0, NULL, NULL} } },
1285 {"misc_aeu", { {0, 0, NULL, NULL} } },
1286 {"bar0_map", { {0, 0, NULL, NULL} } },};
1287
Yuval Mintz0d956e82016-02-28 12:26:53 +02001288/* Notice aeu_invert_reg must be defined in the same order of bits as HW; */
1289static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = {
1290 {
1291 { /* After Invert 1 */
1292 {"GPIO0 function%d",
Yuval Mintzff385772016-02-28 12:26:54 +02001293 (32 << ATTENTION_LENGTH_SHIFT), MAX_BLOCK_ID},
Yuval Mintz0d956e82016-02-28 12:26:53 +02001294 }
1295 },
1296
1297 {
1298 { /* After Invert 2 */
Yuval Mintzff385772016-02-28 12:26:54 +02001299 {"PGLUE config_space", ATTENTION_SINGLE, MAX_BLOCK_ID},
1300 {"PGLUE misc_flr", ATTENTION_SINGLE, MAX_BLOCK_ID},
1301 {"PGLUE B RBC", ATTENTION_PAR_INT, BLOCK_PGLUE_B},
1302 {"PGLUE misc_mctp", ATTENTION_SINGLE, MAX_BLOCK_ID},
1303 {"Flash event", ATTENTION_SINGLE, MAX_BLOCK_ID},
1304 {"SMB event", ATTENTION_SINGLE, MAX_BLOCK_ID},
1305 {"Main Power", ATTENTION_SINGLE, MAX_BLOCK_ID},
Yuval Mintz0d956e82016-02-28 12:26:53 +02001306 {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) |
Yuval Mintzff385772016-02-28 12:26:54 +02001307 (1 << ATTENTION_OFFSET_SHIFT),
1308 MAX_BLOCK_ID},
Yuval Mintz0d956e82016-02-28 12:26:53 +02001309 {"PCIE glue/PXP VPD %d",
Yuval Mintzff385772016-02-28 12:26:54 +02001310 (16 << ATTENTION_LENGTH_SHIFT), BLOCK_PGLCS},
Yuval Mintz0d956e82016-02-28 12:26:53 +02001311 }
1312 },
1313
1314 {
1315 { /* After Invert 3 */
1316 {"General Attention %d",
Yuval Mintzff385772016-02-28 12:26:54 +02001317 (32 << ATTENTION_LENGTH_SHIFT), MAX_BLOCK_ID},
Yuval Mintz0d956e82016-02-28 12:26:53 +02001318 }
1319 },
1320
1321 {
1322 { /* After Invert 4 */
Yuval Mintzff385772016-02-28 12:26:54 +02001323 {"General Attention 32", ATTENTION_SINGLE,
1324 MAX_BLOCK_ID},
Yuval Mintz0d956e82016-02-28 12:26:53 +02001325 {"General Attention %d",
1326 (2 << ATTENTION_LENGTH_SHIFT) |
Yuval Mintzff385772016-02-28 12:26:54 +02001327 (33 << ATTENTION_OFFSET_SHIFT), MAX_BLOCK_ID},
1328 {"General Attention 35", ATTENTION_SINGLE,
1329 MAX_BLOCK_ID},
1330 {"CNIG port %d", (4 << ATTENTION_LENGTH_SHIFT),
1331 BLOCK_CNIG},
1332 {"MCP CPU", ATTENTION_SINGLE, MAX_BLOCK_ID},
1333 {"MCP Watchdog timer", ATTENTION_SINGLE, MAX_BLOCK_ID},
1334 {"MCP M2P", ATTENTION_SINGLE, MAX_BLOCK_ID},
1335 {"AVS stop status ready", ATTENTION_SINGLE,
1336 MAX_BLOCK_ID},
1337 {"MSTAT", ATTENTION_PAR_INT, MAX_BLOCK_ID},
1338 {"MSTAT per-path", ATTENTION_PAR_INT, MAX_BLOCK_ID},
1339 {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT),
1340 MAX_BLOCK_ID},
1341 {"NIG", ATTENTION_PAR_INT, BLOCK_NIG},
1342 {"BMB/OPTE/MCP", ATTENTION_PAR_INT, BLOCK_BMB},
1343 {"BTB", ATTENTION_PAR_INT, BLOCK_BTB},
1344 {"BRB", ATTENTION_PAR_INT, BLOCK_BRB},
1345 {"PRS", ATTENTION_PAR_INT, BLOCK_PRS},
Yuval Mintz0d956e82016-02-28 12:26:53 +02001346 }
1347 },
1348
1349 {
1350 { /* After Invert 5 */
Yuval Mintzff385772016-02-28 12:26:54 +02001351 {"SRC", ATTENTION_PAR_INT, BLOCK_SRC},
1352 {"PB Client1", ATTENTION_PAR_INT, BLOCK_PBF_PB1},
1353 {"PB Client2", ATTENTION_PAR_INT, BLOCK_PBF_PB2},
1354 {"RPB", ATTENTION_PAR_INT, BLOCK_RPB},
1355 {"PBF", ATTENTION_PAR_INT, BLOCK_PBF},
1356 {"QM", ATTENTION_PAR_INT, BLOCK_QM},
1357 {"TM", ATTENTION_PAR_INT, BLOCK_TM},
1358 {"MCM", ATTENTION_PAR_INT, BLOCK_MCM},
1359 {"MSDM", ATTENTION_PAR_INT, BLOCK_MSDM},
1360 {"MSEM", ATTENTION_PAR_INT, BLOCK_MSEM},
1361 {"PCM", ATTENTION_PAR_INT, BLOCK_PCM},
1362 {"PSDM", ATTENTION_PAR_INT, BLOCK_PSDM},
1363 {"PSEM", ATTENTION_PAR_INT, BLOCK_PSEM},
1364 {"TCM", ATTENTION_PAR_INT, BLOCK_TCM},
1365 {"TSDM", ATTENTION_PAR_INT, BLOCK_TSDM},
1366 {"TSEM", ATTENTION_PAR_INT, BLOCK_TSEM},
Yuval Mintz0d956e82016-02-28 12:26:53 +02001367 }
1368 },
1369
1370 {
1371 { /* After Invert 6 */
Yuval Mintzff385772016-02-28 12:26:54 +02001372 {"UCM", ATTENTION_PAR_INT, BLOCK_UCM},
1373 {"USDM", ATTENTION_PAR_INT, BLOCK_USDM},
1374 {"USEM", ATTENTION_PAR_INT, BLOCK_USEM},
1375 {"XCM", ATTENTION_PAR_INT, BLOCK_XCM},
1376 {"XSDM", ATTENTION_PAR_INT, BLOCK_XSDM},
1377 {"XSEM", ATTENTION_PAR_INT, BLOCK_XSEM},
1378 {"YCM", ATTENTION_PAR_INT, BLOCK_YCM},
1379 {"YSDM", ATTENTION_PAR_INT, BLOCK_YSDM},
1380 {"YSEM", ATTENTION_PAR_INT, BLOCK_YSEM},
1381 {"XYLD", ATTENTION_PAR_INT, BLOCK_XYLD},
1382 {"TMLD", ATTENTION_PAR_INT, BLOCK_TMLD},
1383 {"MYLD", ATTENTION_PAR_INT, BLOCK_MULD},
1384 {"YULD", ATTENTION_PAR_INT, BLOCK_YULD},
1385 {"DORQ", ATTENTION_PAR_INT, BLOCK_DORQ},
1386 {"DBG", ATTENTION_PAR_INT, BLOCK_DBG},
1387 {"IPC", ATTENTION_PAR_INT, BLOCK_IPC},
Yuval Mintz0d956e82016-02-28 12:26:53 +02001388 }
1389 },
1390
1391 {
1392 { /* After Invert 7 */
Yuval Mintzff385772016-02-28 12:26:54 +02001393 {"CCFC", ATTENTION_PAR_INT, BLOCK_CCFC},
1394 {"CDU", ATTENTION_PAR_INT, BLOCK_CDU},
1395 {"DMAE", ATTENTION_PAR_INT, BLOCK_DMAE},
1396 {"IGU", ATTENTION_PAR_INT, BLOCK_IGU},
1397 {"ATC", ATTENTION_PAR_INT, MAX_BLOCK_ID},
1398 {"CAU", ATTENTION_PAR_INT, BLOCK_CAU},
1399 {"PTU", ATTENTION_PAR_INT, BLOCK_PTU},
1400 {"PRM", ATTENTION_PAR_INT, BLOCK_PRM},
1401 {"TCFC", ATTENTION_PAR_INT, BLOCK_TCFC},
1402 {"RDIF", ATTENTION_PAR_INT, BLOCK_RDIF},
1403 {"TDIF", ATTENTION_PAR_INT, BLOCK_TDIF},
1404 {"RSS", ATTENTION_PAR_INT, BLOCK_RSS},
1405 {"MISC", ATTENTION_PAR_INT, BLOCK_MISC},
1406 {"MISCS", ATTENTION_PAR_INT, BLOCK_MISCS},
1407 {"PCIE", ATTENTION_PAR, BLOCK_PCIE},
1408 {"Vaux PCI core", ATTENTION_SINGLE, BLOCK_PGLCS},
1409 {"PSWRQ", ATTENTION_PAR_INT, BLOCK_PSWRQ},
Yuval Mintz0d956e82016-02-28 12:26:53 +02001410 }
1411 },
1412
1413 {
1414 { /* After Invert 8 */
Yuval Mintzff385772016-02-28 12:26:54 +02001415 {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, BLOCK_PSWRQ2},
1416 {"PSWWR", ATTENTION_PAR_INT, BLOCK_PSWWR},
1417 {"PSWWR (pci_clk)", ATTENTION_PAR_INT, BLOCK_PSWWR2},
1418 {"PSWRD", ATTENTION_PAR_INT, BLOCK_PSWRD},
1419 {"PSWRD (pci_clk)", ATTENTION_PAR_INT, BLOCK_PSWRD2},
1420 {"PSWHST", ATTENTION_PAR_INT, BLOCK_PSWHST},
1421 {"PSWHST (pci_clk)", ATTENTION_PAR_INT, BLOCK_PSWHST2},
1422 {"GRC", ATTENTION_PAR_INT, BLOCK_GRC},
1423 {"CPMU", ATTENTION_PAR_INT, BLOCK_CPMU},
1424 {"NCSI", ATTENTION_PAR_INT, BLOCK_NCSI},
1425 {"MSEM PRAM", ATTENTION_PAR, MAX_BLOCK_ID},
1426 {"PSEM PRAM", ATTENTION_PAR, MAX_BLOCK_ID},
1427 {"TSEM PRAM", ATTENTION_PAR, MAX_BLOCK_ID},
1428 {"USEM PRAM", ATTENTION_PAR, MAX_BLOCK_ID},
1429 {"XSEM PRAM", ATTENTION_PAR, MAX_BLOCK_ID},
1430 {"YSEM PRAM", ATTENTION_PAR, MAX_BLOCK_ID},
1431 {"pxp_misc_mps", ATTENTION_PAR, BLOCK_PGLCS},
1432 {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE,
1433 BLOCK_PGLCS},
1434 {"PERST_B assertion", ATTENTION_SINGLE, MAX_BLOCK_ID},
1435 {"PERST_B deassertion", ATTENTION_SINGLE,
1436 MAX_BLOCK_ID},
1437 {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT),
1438 MAX_BLOCK_ID},
Yuval Mintz0d956e82016-02-28 12:26:53 +02001439 }
1440 },
1441
1442 {
1443 { /* After Invert 9 */
Yuval Mintzff385772016-02-28 12:26:54 +02001444 {"MCP Latched memory", ATTENTION_PAR, MAX_BLOCK_ID},
1445 {"MCP Latched scratchpad cache", ATTENTION_SINGLE,
1446 MAX_BLOCK_ID},
1447 {"MCP Latched ump_tx", ATTENTION_PAR, MAX_BLOCK_ID},
1448 {"MCP Latched scratchpad", ATTENTION_PAR,
1449 MAX_BLOCK_ID},
1450 {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT),
1451 MAX_BLOCK_ID},
Yuval Mintz0d956e82016-02-28 12:26:53 +02001452 }
1453 },
1454};
1455
1456#define ATTN_STATE_BITS (0xfff)
Yuval Mintzcc875c22015-10-26 11:02:31 +02001457#define ATTN_BITS_MASKABLE (0x3ff)
1458struct qed_sb_attn_info {
1459 /* Virtual & Physical address of the SB */
1460 struct atten_status_block *sb_attn;
Yuval Mintz0d956e82016-02-28 12:26:53 +02001461 dma_addr_t sb_phys;
Yuval Mintzcc875c22015-10-26 11:02:31 +02001462
1463 /* Last seen running index */
Yuval Mintz0d956e82016-02-28 12:26:53 +02001464 u16 index;
1465
1466 /* A mask of the AEU bits resulting in a parity error */
1467 u32 parity_mask[NUM_ATTN_REGS];
1468
1469 /* A pointer to the attention description structure */
1470 struct aeu_invert_reg *p_aeu_desc;
Yuval Mintzcc875c22015-10-26 11:02:31 +02001471
1472 /* Previously asserted attentions, which are still unasserted */
Yuval Mintz0d956e82016-02-28 12:26:53 +02001473 u16 known_attn;
Yuval Mintzcc875c22015-10-26 11:02:31 +02001474
1475 /* Cleanup address for the link's general hw attention */
Yuval Mintz0d956e82016-02-28 12:26:53 +02001476 u32 mfw_attn_addr;
Yuval Mintzcc875c22015-10-26 11:02:31 +02001477};
1478
1479static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn,
1480 struct qed_sb_attn_info *p_sb_desc)
1481{
1482 u16 rc = 0;
1483 u16 index;
1484
1485 /* Make certain HW write took affect */
1486 mmiowb();
1487
1488 index = le16_to_cpu(p_sb_desc->sb_attn->sb_index);
1489 if (p_sb_desc->index != index) {
1490 p_sb_desc->index = index;
1491 rc = QED_SB_ATT_IDX;
1492 }
1493
1494 /* Make certain we got a consistent view with HW */
1495 mmiowb();
1496
1497 return rc;
1498}
1499
1500/**
1501 * @brief qed_int_assertion - handles asserted attention bits
1502 *
1503 * @param p_hwfn
1504 * @param asserted_bits newly asserted bits
1505 * @return int
1506 */
1507static int qed_int_assertion(struct qed_hwfn *p_hwfn,
1508 u16 asserted_bits)
1509{
1510 struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
1511 u32 igu_mask;
1512
1513 /* Mask the source of the attention in the IGU */
1514 igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1515 IGU_REG_ATTENTION_ENABLE);
1516 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n",
1517 igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE));
1518 igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE);
1519 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask);
1520
1521 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1522 "inner known ATTN state: 0x%04x --> 0x%04x\n",
1523 sb_attn_sw->known_attn,
1524 sb_attn_sw->known_attn | asserted_bits);
1525 sb_attn_sw->known_attn |= asserted_bits;
1526
1527 /* Handle MCP events */
1528 if (asserted_bits & 0x100) {
1529 qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt);
1530 /* Clean the MCP attention */
1531 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,
1532 sb_attn_sw->mfw_attn_addr, 0);
1533 }
1534
1535 DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview +
1536 GTT_BAR0_MAP_REG_IGU_CMD +
1537 ((IGU_CMD_ATTN_BIT_SET_UPPER -
1538 IGU_CMD_INT_ACK_BASE) << 3),
1539 (u32)asserted_bits);
1540
1541 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "set cmd IGU: 0x%04x\n",
1542 asserted_bits);
1543
1544 return 0;
1545}
1546
Yuval Mintzff385772016-02-28 12:26:54 +02001547static void qed_int_deassertion_print_bit(struct qed_hwfn *p_hwfn,
1548 struct attn_hw_reg *p_reg_desc,
1549 struct attn_hw_block *p_block,
1550 enum qed_attention_type type,
1551 u32 val, u32 mask)
1552{
1553 int j;
1554
1555 for (j = 0; j < p_reg_desc->num_of_bits; j++) {
1556 if (!(val & (1 << j)))
1557 continue;
1558
1559 DP_NOTICE(p_hwfn,
1560 "%s (%s): reg %d [0x%08x], bit %d [%s]\n",
1561 p_block->name,
1562 type == QED_ATTN_TYPE_ATTN ? "Interrupt" :
1563 "Parity",
1564 p_reg_desc->reg_idx, p_reg_desc->sts_addr,
1565 j, (mask & (1 << j)) ? " [MASKED]" : "");
1566 }
1567}
1568
Yuval Mintzcc875c22015-10-26 11:02:31 +02001569/**
Yuval Mintz0d956e82016-02-28 12:26:53 +02001570 * @brief qed_int_deassertion_aeu_bit - handles the effects of a single
1571 * cause of the attention
1572 *
1573 * @param p_hwfn
1574 * @param p_aeu - descriptor of an AEU bit which caused the attention
1575 * @param aeu_en_reg - register offset of the AEU enable reg. which configured
1576 * this bit to this group.
1577 * @param bit_index - index of this bit in the aeu_en_reg
1578 *
1579 * @return int
1580 */
1581static int
1582qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn,
1583 struct aeu_invert_reg_bit *p_aeu,
1584 u32 aeu_en_reg,
1585 u32 bitmask)
1586{
1587 int rc = -EINVAL;
1588 u32 val, mask = ~bitmask;
1589
1590 DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n",
1591 p_aeu->bit_name, bitmask);
1592
Yuval Mintzff385772016-02-28 12:26:54 +02001593 /* Handle HW block interrupt registers */
1594 if (p_aeu->block_index != MAX_BLOCK_ID) {
1595 struct attn_hw_block *p_block;
1596 int i;
1597
1598 p_block = &attn_blocks[p_aeu->block_index];
1599
1600 /* Handle each interrupt register */
1601 for (i = 0; i < p_block->chip_regs[0].num_of_int_regs; i++) {
1602 struct attn_hw_reg *p_reg_desc;
1603 u32 sts_addr;
1604
1605 p_reg_desc = p_block->chip_regs[0].int_regs[i];
1606 sts_addr = p_reg_desc->sts_addr;
1607
1608 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, sts_addr);
1609 mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1610 p_reg_desc->mask_addr);
1611 qed_int_deassertion_print_bit(p_hwfn, p_reg_desc,
1612 p_block,
1613 QED_ATTN_TYPE_ATTN,
1614 val, mask);
1615 }
1616 }
1617
Yuval Mintz0d956e82016-02-28 12:26:53 +02001618 /* Prevent this Attention from being asserted in the future */
1619 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
1620 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & mask));
1621 DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n",
1622 p_aeu->bit_name);
1623
1624 return rc;
1625}
1626
Yuval Mintzff385772016-02-28 12:26:54 +02001627static void qed_int_parity_print(struct qed_hwfn *p_hwfn,
1628 struct aeu_invert_reg_bit *p_aeu,
1629 struct attn_hw_block *p_block,
1630 u8 bit_index)
1631{
1632 int i;
1633
1634 for (i = 0; i < p_block->chip_regs[0].num_of_prty_regs; i++) {
1635 struct attn_hw_reg *p_reg_desc;
1636 u32 val, mask;
1637
1638 p_reg_desc = p_block->chip_regs[0].prty_regs[i];
1639
1640 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1641 p_reg_desc->sts_clr_addr);
1642 mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1643 p_reg_desc->mask_addr);
1644 qed_int_deassertion_print_bit(p_hwfn, p_reg_desc,
1645 p_block,
1646 QED_ATTN_TYPE_PARITY,
1647 val, mask);
1648 }
1649}
1650
1651/**
1652 * @brief qed_int_deassertion_parity - handle a single parity AEU source
1653 *
1654 * @param p_hwfn
1655 * @param p_aeu - descriptor of an AEU bit which caused the parity
1656 * @param bit_index
1657 */
1658static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn,
1659 struct aeu_invert_reg_bit *p_aeu,
1660 u8 bit_index)
1661{
1662 u32 block_id = p_aeu->block_index;
1663
1664 DP_INFO(p_hwfn->cdev, "%s[%d] parity attention is set\n",
1665 p_aeu->bit_name, bit_index);
1666
1667 if (block_id != MAX_BLOCK_ID) {
1668 qed_int_parity_print(p_hwfn, p_aeu, &attn_blocks[block_id],
1669 bit_index);
1670
1671 /* In BB, there's a single parity bit for several blocks */
1672 if (block_id == BLOCK_BTB) {
1673 qed_int_parity_print(p_hwfn, p_aeu,
1674 &attn_blocks[BLOCK_OPTE],
1675 bit_index);
1676 qed_int_parity_print(p_hwfn, p_aeu,
1677 &attn_blocks[BLOCK_MCP],
1678 bit_index);
1679 }
1680 }
1681}
1682
Yuval Mintz0d956e82016-02-28 12:26:53 +02001683/**
Yuval Mintzcc875c22015-10-26 11:02:31 +02001684 * @brief - handles deassertion of previously asserted attentions.
1685 *
1686 * @param p_hwfn
1687 * @param deasserted_bits - newly deasserted bits
1688 * @return int
1689 *
1690 */
1691static int qed_int_deassertion(struct qed_hwfn *p_hwfn,
1692 u16 deasserted_bits)
1693{
1694 struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
Yuval Mintz0d956e82016-02-28 12:26:53 +02001695 u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask;
1696 u8 i, j, k, bit_idx;
1697 int rc = 0;
Yuval Mintzcc875c22015-10-26 11:02:31 +02001698
Yuval Mintz0d956e82016-02-28 12:26:53 +02001699 /* Read the attention registers in the AEU */
1700 for (i = 0; i < NUM_ATTN_REGS; i++) {
1701 aeu_inv_arr[i] = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1702 MISC_REG_AEU_AFTER_INVERT_1_IGU +
1703 i * 0x4);
1704 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1705 "Deasserted bits [%d]: %08x\n",
1706 i, aeu_inv_arr[i]);
1707 }
1708
1709 /* Find parity attentions first */
1710 for (i = 0; i < NUM_ATTN_REGS; i++) {
1711 struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i];
1712 u32 en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1713 MISC_REG_AEU_ENABLE1_IGU_OUT_0 +
1714 i * sizeof(u32));
1715 u32 parities;
1716
1717 /* Skip register in which no parity bit is currently set */
1718 parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en;
1719 if (!parities)
1720 continue;
1721
1722 for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
1723 struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j];
1724
1725 if ((p_bit->flags & ATTENTION_PARITY) &&
Yuval Mintzff385772016-02-28 12:26:54 +02001726 !!(parities & (1 << bit_idx)))
1727 qed_int_deassertion_parity(p_hwfn, p_bit,
1728 bit_idx);
Yuval Mintz0d956e82016-02-28 12:26:53 +02001729
1730 bit_idx += ATTENTION_LENGTH(p_bit->flags);
1731 }
1732 }
1733
1734 /* Find non-parity cause for attention and act */
1735 for (k = 0; k < MAX_ATTN_GRPS; k++) {
1736 struct aeu_invert_reg_bit *p_aeu;
1737
1738 /* Handle only groups whose attention is currently deasserted */
1739 if (!(deasserted_bits & (1 << k)))
1740 continue;
1741
1742 for (i = 0; i < NUM_ATTN_REGS; i++) {
1743 u32 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 +
1744 i * sizeof(u32) +
1745 k * sizeof(u32) * NUM_ATTN_REGS;
1746 u32 en, bits;
1747
1748 en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
1749 bits = aeu_inv_arr[i] & en;
1750
1751 /* Skip if no bit from this group is currently set */
1752 if (!bits)
1753 continue;
1754
1755 /* Find all set bits from current register which belong
1756 * to current group, making them responsible for the
1757 * previous assertion.
1758 */
1759 for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
1760 u8 bit, bit_len;
1761 u32 bitmask;
1762
1763 p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j];
1764
1765 /* No need to handle parity-only bits */
1766 if (p_aeu->flags == ATTENTION_PAR)
1767 continue;
1768
1769 bit = bit_idx;
1770 bit_len = ATTENTION_LENGTH(p_aeu->flags);
1771 if (p_aeu->flags & ATTENTION_PAR_INT) {
1772 /* Skip Parity */
1773 bit++;
1774 bit_len--;
1775 }
1776
1777 bitmask = bits & (((1 << bit_len) - 1) << bit);
1778 if (bitmask) {
1779 /* Handle source of the attention */
1780 qed_int_deassertion_aeu_bit(p_hwfn,
1781 p_aeu,
1782 aeu_en,
1783 bitmask);
1784 }
1785
1786 bit_idx += ATTENTION_LENGTH(p_aeu->flags);
1787 }
1788 }
1789 }
Yuval Mintzcc875c22015-10-26 11:02:31 +02001790
1791 /* Clear IGU indication for the deasserted bits */
1792 DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview +
Yuval Mintz0d956e82016-02-28 12:26:53 +02001793 GTT_BAR0_MAP_REG_IGU_CMD +
1794 ((IGU_CMD_ATTN_BIT_CLR_UPPER -
1795 IGU_CMD_INT_ACK_BASE) << 3),
1796 ~((u32)deasserted_bits));
Yuval Mintzcc875c22015-10-26 11:02:31 +02001797
1798 /* Unmask deasserted attentions in IGU */
1799 aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1800 IGU_REG_ATTENTION_ENABLE);
1801 aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE);
1802 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask);
1803
1804 /* Clear deassertion from inner state */
1805 sb_attn_sw->known_attn &= ~deasserted_bits;
1806
Yuval Mintz0d956e82016-02-28 12:26:53 +02001807 return rc;
Yuval Mintzcc875c22015-10-26 11:02:31 +02001808}
1809
1810static int qed_int_attentions(struct qed_hwfn *p_hwfn)
1811{
1812 struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn;
1813 struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn;
1814 u32 attn_bits = 0, attn_acks = 0;
1815 u16 asserted_bits, deasserted_bits;
1816 __le16 index;
1817 int rc = 0;
1818
1819 /* Read current attention bits/acks - safeguard against attentions
1820 * by guaranting work on a synchronized timeframe
1821 */
1822 do {
1823 index = p_sb_attn->sb_index;
1824 attn_bits = le32_to_cpu(p_sb_attn->atten_bits);
1825 attn_acks = le32_to_cpu(p_sb_attn->atten_ack);
1826 } while (index != p_sb_attn->sb_index);
1827 p_sb_attn->sb_index = index;
1828
1829 /* Attention / Deassertion are meaningful (and in correct state)
1830 * only when they differ and consistent with known state - deassertion
1831 * when previous attention & current ack, and assertion when current
1832 * attention with no previous attention
1833 */
1834 asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) &
1835 ~p_sb_attn_sw->known_attn;
1836 deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) &
1837 p_sb_attn_sw->known_attn;
1838
1839 if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100)) {
1840 DP_INFO(p_hwfn,
1841 "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n",
1842 index, attn_bits, attn_acks, asserted_bits,
1843 deasserted_bits, p_sb_attn_sw->known_attn);
1844 } else if (asserted_bits == 0x100) {
1845 DP_INFO(p_hwfn,
1846 "MFW indication via attention\n");
1847 } else {
1848 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1849 "MFW indication [deassertion]\n");
1850 }
1851
1852 if (asserted_bits) {
1853 rc = qed_int_assertion(p_hwfn, asserted_bits);
1854 if (rc)
1855 return rc;
1856 }
1857
1858 if (deasserted_bits) {
1859 rc = qed_int_deassertion(p_hwfn, deasserted_bits);
1860 if (rc)
1861 return rc;
1862 }
1863
1864 return rc;
1865}
1866
1867static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn,
1868 void __iomem *igu_addr,
1869 u32 ack_cons)
1870{
1871 struct igu_prod_cons_update igu_ack = { 0 };
1872
1873 igu_ack.sb_id_and_flags =
1874 ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1875 (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1876 (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1877 (IGU_SEG_ACCESS_ATTN <<
1878 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1879
1880 DIRECT_REG_WR(igu_addr, igu_ack.sb_id_and_flags);
1881
1882 /* Both segments (interrupts & acks) are written to same place address;
1883 * Need to guarantee all commands will be received (in-order) by HW.
1884 */
1885 mmiowb();
1886 barrier();
1887}
1888
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001889void qed_int_sp_dpc(unsigned long hwfn_cookie)
1890{
1891 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)hwfn_cookie;
1892 struct qed_pi_info *pi_info = NULL;
Yuval Mintzcc875c22015-10-26 11:02:31 +02001893 struct qed_sb_attn_info *sb_attn;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001894 struct qed_sb_info *sb_info;
1895 int arr_size;
1896 u16 rc = 0;
1897
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001898 if (!p_hwfn->p_sp_sb) {
1899 DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n");
1900 return;
1901 }
1902
1903 sb_info = &p_hwfn->p_sp_sb->sb_info;
1904 arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr);
1905 if (!sb_info) {
1906 DP_ERR(p_hwfn->cdev,
1907 "Status block is NULL - cannot ack interrupts\n");
1908 return;
1909 }
1910
Yuval Mintzcc875c22015-10-26 11:02:31 +02001911 if (!p_hwfn->p_sb_attn) {
1912 DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn");
1913 return;
1914 }
1915 sb_attn = p_hwfn->p_sb_attn;
1916
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001917 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n",
1918 p_hwfn, p_hwfn->my_id);
1919
1920 /* Disable ack for def status block. Required both for msix +
1921 * inta in non-mask mode, in inta does no harm.
1922 */
1923 qed_sb_ack(sb_info, IGU_INT_DISABLE, 0);
1924
1925 /* Gather Interrupts/Attentions information */
1926 if (!sb_info->sb_virt) {
1927 DP_ERR(
1928 p_hwfn->cdev,
1929 "Interrupt Status block is NULL - cannot check for new interrupts!\n");
1930 } else {
1931 u32 tmp_index = sb_info->sb_ack;
1932
1933 rc = qed_sb_update_sb_idx(sb_info);
1934 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR,
1935 "Interrupt indices: 0x%08x --> 0x%08x\n",
1936 tmp_index, sb_info->sb_ack);
1937 }
1938
Yuval Mintzcc875c22015-10-26 11:02:31 +02001939 if (!sb_attn || !sb_attn->sb_attn) {
1940 DP_ERR(
1941 p_hwfn->cdev,
1942 "Attentions Status block is NULL - cannot check for new attentions!\n");
1943 } else {
1944 u16 tmp_index = sb_attn->index;
1945
1946 rc |= qed_attn_update_idx(p_hwfn, sb_attn);
1947 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR,
1948 "Attention indices: 0x%08x --> 0x%08x\n",
1949 tmp_index, sb_attn->index);
1950 }
1951
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001952 /* Check if we expect interrupts at this time. if not just ack them */
1953 if (!(rc & QED_SB_EVENT_MASK)) {
1954 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1955 return;
1956 }
1957
1958 /* Check the validity of the DPC ptt. If not ack interrupts and fail */
1959 if (!p_hwfn->p_dpc_ptt) {
1960 DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n");
1961 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1962 return;
1963 }
1964
Yuval Mintzcc875c22015-10-26 11:02:31 +02001965 if (rc & QED_SB_ATT_IDX)
1966 qed_int_attentions(p_hwfn);
1967
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001968 if (rc & QED_SB_IDX) {
1969 int pi;
1970
1971 /* Look for a free index */
1972 for (pi = 0; pi < arr_size; pi++) {
1973 pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi];
1974 if (pi_info->comp_cb)
1975 pi_info->comp_cb(p_hwfn, pi_info->cookie);
1976 }
1977 }
1978
Yuval Mintzcc875c22015-10-26 11:02:31 +02001979 if (sb_attn && (rc & QED_SB_ATT_IDX))
1980 /* This should be done before the interrupts are enabled,
1981 * since otherwise a new attention will be generated.
1982 */
1983 qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index);
1984
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001985 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1986}
1987
Yuval Mintzcc875c22015-10-26 11:02:31 +02001988static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn)
1989{
Yuval Mintz4ac801b2016-02-28 12:26:52 +02001990 struct qed_sb_attn_info *p_sb = p_hwfn->p_sb_attn;
Yuval Mintzcc875c22015-10-26 11:02:31 +02001991
Yuval Mintz4ac801b2016-02-28 12:26:52 +02001992 if (!p_sb)
1993 return;
1994
1995 if (p_sb->sb_attn)
1996 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1997 SB_ATTN_ALIGNED_SIZE(p_hwfn),
1998 p_sb->sb_attn,
1999 p_sb->sb_phys);
2000 kfree(p_sb);
Yuval Mintzcc875c22015-10-26 11:02:31 +02002001}
2002
2003static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn,
2004 struct qed_ptt *p_ptt)
2005{
2006 struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
2007
2008 memset(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn));
2009
2010 sb_info->index = 0;
2011 sb_info->known_attn = 0;
2012
2013 /* Configure Attention Status Block in IGU */
2014 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L,
2015 lower_32_bits(p_hwfn->p_sb_attn->sb_phys));
2016 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H,
2017 upper_32_bits(p_hwfn->p_sb_attn->sb_phys));
2018}
2019
2020static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn,
2021 struct qed_ptt *p_ptt,
2022 void *sb_virt_addr,
2023 dma_addr_t sb_phy_addr)
2024{
2025 struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
Yuval Mintz0d956e82016-02-28 12:26:53 +02002026 int i, j, k;
Yuval Mintzcc875c22015-10-26 11:02:31 +02002027
2028 sb_info->sb_attn = sb_virt_addr;
2029 sb_info->sb_phys = sb_phy_addr;
2030
Yuval Mintz0d956e82016-02-28 12:26:53 +02002031 /* Set the pointer to the AEU descriptors */
2032 sb_info->p_aeu_desc = aeu_descs;
2033
2034 /* Calculate Parity Masks */
2035 memset(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS);
2036 for (i = 0; i < NUM_ATTN_REGS; i++) {
2037 /* j is array index, k is bit index */
2038 for (j = 0, k = 0; k < 32; j++) {
2039 unsigned int flags = aeu_descs[i].bits[j].flags;
2040
2041 if (flags & ATTENTION_PARITY)
2042 sb_info->parity_mask[i] |= 1 << k;
2043
2044 k += ATTENTION_LENGTH(flags);
2045 }
2046 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
2047 "Attn Mask [Reg %d]: 0x%08x\n",
2048 i, sb_info->parity_mask[i]);
2049 }
2050
Yuval Mintzcc875c22015-10-26 11:02:31 +02002051 /* Set the address of cleanup for the mcp attention */
2052 sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) +
2053 MISC_REG_AEU_GENERAL_ATTN_0;
2054
2055 qed_int_sb_attn_setup(p_hwfn, p_ptt);
2056}
2057
2058static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn,
2059 struct qed_ptt *p_ptt)
2060{
2061 struct qed_dev *cdev = p_hwfn->cdev;
2062 struct qed_sb_attn_info *p_sb;
2063 void *p_virt;
2064 dma_addr_t p_phys = 0;
2065
2066 /* SB struct */
Yuval Mintz60fffb32016-02-21 11:40:07 +02002067 p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL);
Yuval Mintzcc875c22015-10-26 11:02:31 +02002068 if (!p_sb) {
2069 DP_NOTICE(cdev, "Failed to allocate `struct qed_sb_attn_info'\n");
2070 return -ENOMEM;
2071 }
2072
2073 /* SB ring */
2074 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
2075 SB_ATTN_ALIGNED_SIZE(p_hwfn),
2076 &p_phys, GFP_KERNEL);
2077
2078 if (!p_virt) {
2079 DP_NOTICE(cdev, "Failed to allocate status block (attentions)\n");
2080 kfree(p_sb);
2081 return -ENOMEM;
2082 }
2083
2084 /* Attention setup */
2085 p_hwfn->p_sb_attn = p_sb;
2086 qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys);
2087
2088 return 0;
2089}
2090
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002091/* coalescing timeout = timeset << (timer_res + 1) */
2092#define QED_CAU_DEF_RX_USECS 24
2093#define QED_CAU_DEF_TX_USECS 48
2094
2095void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
2096 struct cau_sb_entry *p_sb_entry,
2097 u8 pf_id,
2098 u16 vf_number,
2099 u8 vf_valid)
2100{
Yuval Mintz4ac801b2016-02-28 12:26:52 +02002101 struct qed_dev *cdev = p_hwfn->cdev;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002102 u32 cau_state;
2103
2104 memset(p_sb_entry, 0, sizeof(*p_sb_entry));
2105
2106 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id);
2107 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number);
2108 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid);
2109 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F);
2110 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F);
2111
2112 /* setting the time resultion to a fixed value ( = 1) */
2113 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0,
2114 QED_CAU_DEF_RX_TIMER_RES);
2115 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1,
2116 QED_CAU_DEF_TX_TIMER_RES);
2117
2118 cau_state = CAU_HC_DISABLE_STATE;
2119
Yuval Mintz4ac801b2016-02-28 12:26:52 +02002120 if (cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) {
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002121 cau_state = CAU_HC_ENABLE_STATE;
Yuval Mintz4ac801b2016-02-28 12:26:52 +02002122 if (!cdev->rx_coalesce_usecs)
2123 cdev->rx_coalesce_usecs = QED_CAU_DEF_RX_USECS;
2124 if (!cdev->tx_coalesce_usecs)
2125 cdev->tx_coalesce_usecs = QED_CAU_DEF_TX_USECS;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002126 }
2127
2128 SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state);
2129 SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state);
2130}
2131
2132void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
2133 struct qed_ptt *p_ptt,
2134 dma_addr_t sb_phys,
2135 u16 igu_sb_id,
2136 u16 vf_number,
2137 u8 vf_valid)
2138{
2139 struct cau_sb_entry sb_entry;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002140
2141 qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id,
2142 vf_number, vf_valid);
2143
2144 if (p_hwfn->hw_init_done) {
Yuval Mintz0a0c5d32016-02-21 11:40:08 +02002145 /* Wide-bus, initialize via DMAE */
2146 u64 phys_addr = (u64)sb_phys;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002147
Yuval Mintz0a0c5d32016-02-21 11:40:08 +02002148 qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&phys_addr,
2149 CAU_REG_SB_ADDR_MEMORY +
2150 igu_sb_id * sizeof(u64), 2, 0);
2151 qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&sb_entry,
2152 CAU_REG_SB_VAR_MEMORY +
2153 igu_sb_id * sizeof(u64), 2, 0);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002154 } else {
2155 /* Initialize Status Block Address */
2156 STORE_RT_REG_AGG(p_hwfn,
2157 CAU_REG_SB_ADDR_MEMORY_RT_OFFSET +
2158 igu_sb_id * 2,
2159 sb_phys);
2160
2161 STORE_RT_REG_AGG(p_hwfn,
2162 CAU_REG_SB_VAR_MEMORY_RT_OFFSET +
2163 igu_sb_id * 2,
2164 sb_entry);
2165 }
2166
2167 /* Configure pi coalescing if set */
2168 if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) {
2169 u8 timeset = p_hwfn->cdev->rx_coalesce_usecs >>
2170 (QED_CAU_DEF_RX_TIMER_RES + 1);
2171 u8 num_tc = 1, i;
2172
2173 qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,
2174 QED_COAL_RX_STATE_MACHINE,
2175 timeset);
2176
2177 timeset = p_hwfn->cdev->tx_coalesce_usecs >>
2178 (QED_CAU_DEF_TX_TIMER_RES + 1);
2179
2180 for (i = 0; i < num_tc; i++) {
2181 qed_int_cau_conf_pi(p_hwfn, p_ptt,
2182 igu_sb_id, TX_PI(i),
2183 QED_COAL_TX_STATE_MACHINE,
2184 timeset);
2185 }
2186 }
2187}
2188
2189void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn,
2190 struct qed_ptt *p_ptt,
2191 u16 igu_sb_id,
2192 u32 pi_index,
2193 enum qed_coalescing_fsm coalescing_fsm,
2194 u8 timeset)
2195{
2196 struct cau_pi_entry pi_entry;
2197 u32 sb_offset;
2198 u32 pi_offset;
2199
2200 sb_offset = igu_sb_id * PIS_PER_SB;
2201 memset(&pi_entry, 0, sizeof(struct cau_pi_entry));
2202
2203 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
2204 if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE)
2205 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0);
2206 else
2207 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1);
2208
2209 pi_offset = sb_offset + pi_index;
2210 if (p_hwfn->hw_init_done) {
2211 qed_wr(p_hwfn, p_ptt,
2212 CAU_REG_PI_MEMORY + pi_offset * sizeof(u32),
2213 *((u32 *)&(pi_entry)));
2214 } else {
2215 STORE_RT_REG(p_hwfn,
2216 CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset,
2217 *((u32 *)&(pi_entry)));
2218 }
2219}
2220
2221void qed_int_sb_setup(struct qed_hwfn *p_hwfn,
2222 struct qed_ptt *p_ptt,
2223 struct qed_sb_info *sb_info)
2224{
2225 /* zero status block and ack counter */
2226 sb_info->sb_ack = 0;
2227 memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
2228
2229 qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys,
2230 sb_info->igu_sb_id, 0, 0);
2231}
2232
2233/**
2234 * @brief qed_get_igu_sb_id - given a sw sb_id return the
2235 * igu_sb_id
2236 *
2237 * @param p_hwfn
2238 * @param sb_id
2239 *
2240 * @return u16
2241 */
2242static u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn,
2243 u16 sb_id)
2244{
2245 u16 igu_sb_id;
2246
2247 /* Assuming continuous set of IGU SBs dedicated for given PF */
2248 if (sb_id == QED_SP_SB_ID)
2249 igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
2250 else
2251 igu_sb_id = sb_id + p_hwfn->hw_info.p_igu_info->igu_base_sb;
2252
2253 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "SB [%s] index is 0x%04x\n",
2254 (sb_id == QED_SP_SB_ID) ? "DSB" : "non-DSB", igu_sb_id);
2255
2256 return igu_sb_id;
2257}
2258
2259int qed_int_sb_init(struct qed_hwfn *p_hwfn,
2260 struct qed_ptt *p_ptt,
2261 struct qed_sb_info *sb_info,
2262 void *sb_virt_addr,
2263 dma_addr_t sb_phy_addr,
2264 u16 sb_id)
2265{
2266 sb_info->sb_virt = sb_virt_addr;
2267 sb_info->sb_phys = sb_phy_addr;
2268
2269 sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id);
2270
2271 if (sb_id != QED_SP_SB_ID) {
2272 p_hwfn->sbs_info[sb_id] = sb_info;
2273 p_hwfn->num_sbs++;
2274 }
2275
2276 sb_info->cdev = p_hwfn->cdev;
2277
2278 /* The igu address will hold the absolute address that needs to be
2279 * written to for a specific status block
2280 */
2281 sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview +
2282 GTT_BAR0_MAP_REG_IGU_CMD +
2283 (sb_info->igu_sb_id << 3);
2284
2285 sb_info->flags |= QED_SB_INFO_INIT;
2286
2287 qed_int_sb_setup(p_hwfn, p_ptt, sb_info);
2288
2289 return 0;
2290}
2291
2292int qed_int_sb_release(struct qed_hwfn *p_hwfn,
2293 struct qed_sb_info *sb_info,
2294 u16 sb_id)
2295{
2296 if (sb_id == QED_SP_SB_ID) {
2297 DP_ERR(p_hwfn, "Do Not free sp sb using this function");
2298 return -EINVAL;
2299 }
2300
2301 /* zero status block and ack counter */
2302 sb_info->sb_ack = 0;
2303 memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
2304
Yuval Mintz4ac801b2016-02-28 12:26:52 +02002305 if (p_hwfn->sbs_info[sb_id] != NULL) {
2306 p_hwfn->sbs_info[sb_id] = NULL;
2307 p_hwfn->num_sbs--;
2308 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002309
2310 return 0;
2311}
2312
2313static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn)
2314{
2315 struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb;
2316
Yuval Mintz4ac801b2016-02-28 12:26:52 +02002317 if (!p_sb)
2318 return;
2319
2320 if (p_sb->sb_info.sb_virt)
2321 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
2322 SB_ALIGNED_SIZE(p_hwfn),
2323 p_sb->sb_info.sb_virt,
2324 p_sb->sb_info.sb_phys);
2325 kfree(p_sb);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002326}
2327
2328static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn,
2329 struct qed_ptt *p_ptt)
2330{
2331 struct qed_sb_sp_info *p_sb;
2332 dma_addr_t p_phys = 0;
2333 void *p_virt;
2334
2335 /* SB struct */
Yuval Mintz60fffb32016-02-21 11:40:07 +02002336 p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002337 if (!p_sb) {
2338 DP_NOTICE(p_hwfn, "Failed to allocate `struct qed_sb_info'\n");
2339 return -ENOMEM;
2340 }
2341
2342 /* SB ring */
2343 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
2344 SB_ALIGNED_SIZE(p_hwfn),
2345 &p_phys, GFP_KERNEL);
2346 if (!p_virt) {
2347 DP_NOTICE(p_hwfn, "Failed to allocate status block\n");
2348 kfree(p_sb);
2349 return -ENOMEM;
2350 }
2351
2352 /* Status Block setup */
2353 p_hwfn->p_sp_sb = p_sb;
2354 qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt,
2355 p_phys, QED_SP_SB_ID);
2356
2357 memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr));
2358
2359 return 0;
2360}
2361
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002362int qed_int_register_cb(struct qed_hwfn *p_hwfn,
2363 qed_int_comp_cb_t comp_cb,
2364 void *cookie,
2365 u8 *sb_idx,
2366 __le16 **p_fw_cons)
2367{
2368 struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
Yuval Mintz4ac801b2016-02-28 12:26:52 +02002369 int rc = -ENOMEM;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002370 u8 pi;
2371
2372 /* Look for a free index */
2373 for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) {
Yuval Mintz4ac801b2016-02-28 12:26:52 +02002374 if (p_sp_sb->pi_info_arr[pi].comp_cb)
2375 continue;
2376
2377 p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb;
2378 p_sp_sb->pi_info_arr[pi].cookie = cookie;
2379 *sb_idx = pi;
2380 *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi];
2381 rc = 0;
2382 break;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002383 }
2384
Yuval Mintz4ac801b2016-02-28 12:26:52 +02002385 return rc;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002386}
2387
2388int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi)
2389{
2390 struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002391
Yuval Mintz4ac801b2016-02-28 12:26:52 +02002392 if (p_sp_sb->pi_info_arr[pi].comp_cb == NULL)
2393 return -ENOMEM;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002394
Yuval Mintz4ac801b2016-02-28 12:26:52 +02002395 p_sp_sb->pi_info_arr[pi].comp_cb = NULL;
2396 p_sp_sb->pi_info_arr[pi].cookie = NULL;
2397
2398 return 0;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002399}
2400
2401u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn)
2402{
2403 return p_hwfn->p_sp_sb->sb_info.igu_sb_id;
2404}
2405
2406void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn,
2407 struct qed_ptt *p_ptt,
2408 enum qed_int_mode int_mode)
2409{
Yuval Mintzcc875c22015-10-26 11:02:31 +02002410 u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002411
2412 p_hwfn->cdev->int_mode = int_mode;
2413 switch (p_hwfn->cdev->int_mode) {
2414 case QED_INT_MODE_INTA:
2415 igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN;
2416 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
2417 break;
2418
2419 case QED_INT_MODE_MSI:
2420 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
2421 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
2422 break;
2423
2424 case QED_INT_MODE_MSIX:
2425 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
2426 break;
2427 case QED_INT_MODE_POLL:
2428 break;
2429 }
2430
2431 qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);
2432}
2433
Sudarsana Kalluru8f16bc92015-12-07 06:25:59 -05002434int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2435 enum qed_int_mode int_mode)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002436{
Yuval Mintz0d956e82016-02-28 12:26:53 +02002437 int rc;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002438
Yuval Mintz0d956e82016-02-28 12:26:53 +02002439 /* Configure AEU signal change to produce attentions */
2440 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0);
Yuval Mintzcc875c22015-10-26 11:02:31 +02002441 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff);
2442 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff);
Yuval Mintz0d956e82016-02-28 12:26:53 +02002443 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff);
Yuval Mintzcc875c22015-10-26 11:02:31 +02002444
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002445 /* Flush the writes to IGU */
2446 mmiowb();
Yuval Mintzcc875c22015-10-26 11:02:31 +02002447
2448 /* Unmask AEU signals toward IGU */
2449 qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff);
Sudarsana Kalluru8f16bc92015-12-07 06:25:59 -05002450 if ((int_mode != QED_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) {
2451 rc = qed_slowpath_irq_req(p_hwfn);
2452 if (rc != 0) {
2453 DP_NOTICE(p_hwfn, "Slowpath IRQ request failed\n");
2454 return -EINVAL;
2455 }
2456 p_hwfn->b_int_requested = true;
2457 }
2458 /* Enable interrupt Generation */
2459 qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode);
2460 p_hwfn->b_int_enabled = 1;
2461
2462 return rc;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002463}
2464
2465void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn,
2466 struct qed_ptt *p_ptt)
2467{
2468 p_hwfn->b_int_enabled = 0;
2469
2470 qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
2471}
2472
2473#define IGU_CLEANUP_SLEEP_LENGTH (1000)
2474void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn,
2475 struct qed_ptt *p_ptt,
2476 u32 sb_id,
2477 bool cleanup_set,
2478 u16 opaque_fid
2479 )
2480{
2481 u32 pxp_addr = IGU_CMD_INT_ACK_BASE + sb_id;
2482 u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH;
2483 u32 data = 0;
2484 u32 cmd_ctrl = 0;
2485 u32 val = 0;
2486 u32 sb_bit = 0;
2487 u32 sb_bit_addr = 0;
2488
2489 /* Set the data field */
2490 SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0);
2491 SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, 0);
2492 SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET);
2493
2494 /* Set the control register */
2495 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr);
2496 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid);
2497 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR);
2498
2499 qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data);
2500
2501 barrier();
2502
2503 qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl);
2504
2505 /* Flush the write to IGU */
2506 mmiowb();
2507
2508 /* calculate where to read the status bit from */
2509 sb_bit = 1 << (sb_id % 32);
2510 sb_bit_addr = sb_id / 32 * sizeof(u32);
2511
2512 sb_bit_addr += IGU_REG_CLEANUP_STATUS_0;
2513
2514 /* Now wait for the command to complete */
2515 do {
2516 val = qed_rd(p_hwfn, p_ptt, sb_bit_addr);
2517
2518 if ((val & sb_bit) == (cleanup_set ? sb_bit : 0))
2519 break;
2520
2521 usleep_range(5000, 10000);
2522 } while (--sleep_cnt);
2523
2524 if (!sleep_cnt)
2525 DP_NOTICE(p_hwfn,
2526 "Timeout waiting for clear status 0x%08x [for sb %d]\n",
2527 val, sb_id);
2528}
2529
2530void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,
2531 struct qed_ptt *p_ptt,
2532 u32 sb_id,
2533 u16 opaque,
2534 bool b_set)
2535{
2536 int pi;
2537
2538 /* Set */
2539 if (b_set)
2540 qed_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 1, opaque);
2541
2542 /* Clear */
2543 qed_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 0, opaque);
2544
2545 /* Clear the CAU for the SB */
2546 for (pi = 0; pi < 12; pi++)
2547 qed_wr(p_hwfn, p_ptt,
2548 CAU_REG_PI_MEMORY + (sb_id * 12 + pi) * 4, 0);
2549}
2550
2551void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn,
2552 struct qed_ptt *p_ptt,
2553 bool b_set,
2554 bool b_slowpath)
2555{
2556 u32 igu_base_sb = p_hwfn->hw_info.p_igu_info->igu_base_sb;
2557 u32 igu_sb_cnt = p_hwfn->hw_info.p_igu_info->igu_sb_cnt;
2558 u32 sb_id = 0;
2559 u32 val = 0;
2560
2561 val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);
2562 val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN;
2563 val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN;
2564 qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val);
2565
2566 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
2567 "IGU cleaning SBs [%d,...,%d]\n",
2568 igu_base_sb, igu_base_sb + igu_sb_cnt - 1);
2569
2570 for (sb_id = igu_base_sb; sb_id < igu_base_sb + igu_sb_cnt; sb_id++)
2571 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id,
2572 p_hwfn->hw_info.opaque_fid,
2573 b_set);
2574
2575 if (b_slowpath) {
2576 sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
2577 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
2578 "IGU cleaning slowpath SB [%d]\n", sb_id);
2579 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id,
2580 p_hwfn->hw_info.opaque_fid,
2581 b_set);
2582 }
2583}
2584
Yuval Mintz4ac801b2016-02-28 12:26:52 +02002585static u32 qed_int_igu_read_cam_block(struct qed_hwfn *p_hwfn,
2586 struct qed_ptt *p_ptt,
2587 u16 sb_id)
2588{
2589 u32 val = qed_rd(p_hwfn, p_ptt,
2590 IGU_REG_MAPPING_MEMORY +
2591 sizeof(u32) * sb_id);
2592 struct qed_igu_block *p_block;
2593
2594 p_block = &p_hwfn->hw_info.p_igu_info->igu_map.igu_blocks[sb_id];
2595
2596 /* stop scanning when hit first invalid PF entry */
2597 if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) &&
2598 GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID))
2599 goto out;
2600
2601 /* Fill the block information */
2602 p_block->status = QED_IGU_STATUS_VALID;
2603 p_block->function_id = GET_FIELD(val,
2604 IGU_MAPPING_LINE_FUNCTION_NUMBER);
2605 p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID);
2606 p_block->vector_number = GET_FIELD(val,
2607 IGU_MAPPING_LINE_VECTOR_NUMBER);
2608
2609 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
2610 "IGU_BLOCK: [SB 0x%04x, Value in CAM 0x%08x] func_id = %d is_pf = %d vector_num = 0x%x\n",
2611 sb_id, val, p_block->function_id,
2612 p_block->is_pf, p_block->vector_number);
2613
2614out:
2615 return val;
2616}
2617
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002618int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn,
2619 struct qed_ptt *p_ptt)
2620{
2621 struct qed_igu_info *p_igu_info;
2622 struct qed_igu_block *blk;
2623 u32 val;
2624 u16 sb_id;
2625 u16 prev_sb_id = 0xFF;
2626
Yuval Mintz60fffb32016-02-21 11:40:07 +02002627 p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_KERNEL);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002628
2629 if (!p_hwfn->hw_info.p_igu_info)
2630 return -ENOMEM;
2631
2632 p_igu_info = p_hwfn->hw_info.p_igu_info;
2633
2634 /* Initialize base sb / sb cnt for PFs */
2635 p_igu_info->igu_base_sb = 0xffff;
2636 p_igu_info->igu_sb_cnt = 0;
2637 p_igu_info->igu_dsb_id = 0xffff;
2638 p_igu_info->igu_base_sb_iov = 0xffff;
2639
2640 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev);
2641 sb_id++) {
2642 blk = &p_igu_info->igu_map.igu_blocks[sb_id];
2643
Yuval Mintz4ac801b2016-02-28 12:26:52 +02002644 val = qed_int_igu_read_cam_block(p_hwfn, p_ptt, sb_id);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002645
2646 /* stop scanning when hit first invalid PF entry */
2647 if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) &&
2648 GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID))
2649 break;
2650
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002651 if (blk->is_pf) {
2652 if (blk->function_id == p_hwfn->rel_pf_id) {
2653 blk->status |= QED_IGU_STATUS_PF;
2654
2655 if (blk->vector_number == 0) {
2656 if (p_igu_info->igu_dsb_id == 0xffff)
2657 p_igu_info->igu_dsb_id = sb_id;
2658 } else {
2659 if (p_igu_info->igu_base_sb ==
2660 0xffff) {
2661 p_igu_info->igu_base_sb = sb_id;
2662 } else if (prev_sb_id != sb_id - 1) {
2663 DP_NOTICE(p_hwfn->cdev,
2664 "consecutive igu vectors for HWFN %x broken",
2665 p_hwfn->rel_pf_id);
2666 break;
2667 }
2668 prev_sb_id = sb_id;
2669 /* we don't count the default */
2670 (p_igu_info->igu_sb_cnt)++;
2671 }
2672 }
2673 }
2674 }
2675
2676 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
2677 "IGU igu_base_sb=0x%x igu_sb_cnt=%d igu_dsb_id=0x%x\n",
2678 p_igu_info->igu_base_sb,
2679 p_igu_info->igu_sb_cnt,
2680 p_igu_info->igu_dsb_id);
2681
2682 if (p_igu_info->igu_base_sb == 0xffff ||
2683 p_igu_info->igu_dsb_id == 0xffff ||
2684 p_igu_info->igu_sb_cnt == 0) {
2685 DP_NOTICE(p_hwfn,
2686 "IGU CAM returned invalid values igu_base_sb=0x%x igu_sb_cnt=%d igu_dsb_id=0x%x\n",
2687 p_igu_info->igu_base_sb,
2688 p_igu_info->igu_sb_cnt,
2689 p_igu_info->igu_dsb_id);
2690 return -EINVAL;
2691 }
2692
2693 return 0;
2694}
2695
2696/**
2697 * @brief Initialize igu runtime registers
2698 *
2699 * @param p_hwfn
2700 */
2701void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn)
2702{
2703 u32 igu_pf_conf = 0;
2704
2705 igu_pf_conf |= IGU_PF_CONF_FUNC_EN;
2706
2707 STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf);
2708}
2709
2710u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn)
2711{
2712 u64 intr_status = 0;
2713 u32 intr_status_lo = 0;
2714 u32 intr_status_hi = 0;
2715 u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER -
2716 IGU_CMD_INT_ACK_BASE;
2717 u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER -
2718 IGU_CMD_INT_ACK_BASE;
2719
2720 intr_status_lo = REG_RD(p_hwfn,
2721 GTT_BAR0_MAP_REG_IGU_CMD +
2722 lsb_igu_cmd_addr * 8);
2723 intr_status_hi = REG_RD(p_hwfn,
2724 GTT_BAR0_MAP_REG_IGU_CMD +
2725 msb_igu_cmd_addr * 8);
2726 intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo;
2727
2728 return intr_status;
2729}
2730
2731static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn)
2732{
2733 tasklet_init(p_hwfn->sp_dpc,
2734 qed_int_sp_dpc, (unsigned long)p_hwfn);
2735 p_hwfn->b_sp_dpc_enabled = true;
2736}
2737
2738static int qed_int_sp_dpc_alloc(struct qed_hwfn *p_hwfn)
2739{
Yuval Mintz60fffb32016-02-21 11:40:07 +02002740 p_hwfn->sp_dpc = kmalloc(sizeof(*p_hwfn->sp_dpc), GFP_KERNEL);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002741 if (!p_hwfn->sp_dpc)
2742 return -ENOMEM;
2743
2744 return 0;
2745}
2746
2747static void qed_int_sp_dpc_free(struct qed_hwfn *p_hwfn)
2748{
2749 kfree(p_hwfn->sp_dpc);
2750}
2751
2752int qed_int_alloc(struct qed_hwfn *p_hwfn,
2753 struct qed_ptt *p_ptt)
2754{
2755 int rc = 0;
2756
2757 rc = qed_int_sp_dpc_alloc(p_hwfn);
2758 if (rc) {
2759 DP_ERR(p_hwfn->cdev, "Failed to allocate sp dpc mem\n");
2760 return rc;
2761 }
2762 rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt);
2763 if (rc) {
2764 DP_ERR(p_hwfn->cdev, "Failed to allocate sp sb mem\n");
2765 return rc;
2766 }
Yuval Mintzcc875c22015-10-26 11:02:31 +02002767 rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt);
2768 if (rc) {
2769 DP_ERR(p_hwfn->cdev, "Failed to allocate sb attn mem\n");
2770 return rc;
2771 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002772 return rc;
2773}
2774
2775void qed_int_free(struct qed_hwfn *p_hwfn)
2776{
2777 qed_int_sp_sb_free(p_hwfn);
Yuval Mintzcc875c22015-10-26 11:02:31 +02002778 qed_int_sb_attn_free(p_hwfn);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002779 qed_int_sp_dpc_free(p_hwfn);
2780}
2781
2782void qed_int_setup(struct qed_hwfn *p_hwfn,
2783 struct qed_ptt *p_ptt)
2784{
Yuval Mintz0d956e82016-02-28 12:26:53 +02002785 qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info);
2786 qed_int_sb_attn_setup(p_hwfn, p_ptt);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002787 qed_int_sp_dpc_setup(p_hwfn);
2788}
2789
Yuval Mintz4ac801b2016-02-28 12:26:52 +02002790void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn,
2791 struct qed_sb_cnt_info *p_sb_cnt_info)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002792{
2793 struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info;
2794
Yuval Mintz4ac801b2016-02-28 12:26:52 +02002795 if (!info || !p_sb_cnt_info)
2796 return;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002797
Yuval Mintz4ac801b2016-02-28 12:26:52 +02002798 p_sb_cnt_info->sb_cnt = info->igu_sb_cnt;
2799 p_sb_cnt_info->sb_iov_cnt = info->igu_sb_cnt_iov;
2800 p_sb_cnt_info->sb_free_blk = info->free_blks;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002801}
Sudarsana Kalluru8f16bc92015-12-07 06:25:59 -05002802
2803void qed_int_disable_post_isr_release(struct qed_dev *cdev)
2804{
2805 int i;
2806
2807 for_each_hwfn(cdev, i)
2808 cdev->hwfns[i].b_int_requested = false;
2809}