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gerrit-public.fairphone.software / kernel / msm-4.9 / ff4b42c7532e6ed6a5ae3c9cb71395b41a0a4022 / . / drivers / gpu / drm / nouveau / core / engine / device / nve0.c
blob: e6254a64e9fb4657468a10859099ae60372aac8e [file] [log] [blame]
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]25#include <subdev/bios.h>
Martin Peresa10220b2012-11-04 01:01:53 +0100[diff] [blame]26#include <subdev/bus.h>
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]27#include <subdev/gpio.h>
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]28#include <subdev/i2c.h>
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]29#include <subdev/clock.h>
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]30#include <subdev/therm.h>
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]31#include <subdev/mxm.h>
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]32#include <subdev/devinit.h>
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]33#include <subdev/mc.h>
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]34#include <subdev/timer.h>
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]35#include <subdev/fb.h>
36#include <subdev/ltcg.h>
Ben Skeggs2c1a4252012-08-22 23:55:42 -0400[diff] [blame]37#include <subdev/ibus.h>
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]38#include <subdev/instmem.h>
39#include <subdev/vm.h>
40#include <subdev/bar.h>
Ben Skeggsff4b42c2013-10-15 09:38:12 +1000[diff] [blame^]41#include <subdev/pwr.h>
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]42
Ben Skeggsdded35d2013-04-25 17:23:43 +1000[diff] [blame]43#include <engine/device.h>
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]44#include <engine/dmaobj.h>
45#include <engine/fifo.h>
46#include <engine/software.h>
47#include <engine/graph.h>
48#include <engine/disp.h>
Ben Skeggs4f326562012-08-06 19:28:02 +1000[diff] [blame]49#include <engine/copy.h>
Ben Skeggsb2f04fc2012-11-22 15:42:23 +1000[diff] [blame]50#include <engine/bsp.h>
Ben Skeggsa7416d02012-11-22 15:48:41 +1000[diff] [blame]51#include <engine/vp.h>
Ben Skeggsfb9bff22012-11-23 11:14:49 +1000[diff] [blame]52#include <engine/ppp.h>
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]53
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]54int
55nve0_identify(struct nouveau_device *device)
56{
57 switch (device->chipset) {
58 case 0xe4:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]59 device->cname = "GK104";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]60 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggsfa531bc2013-02-13 13:34:39 +1000[diff] [blame]61 device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
Ben Skeggs7dcd060c2013-02-16 15:21:58 +1000[diff] [blame]62 device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]63 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Ben Skeggsbc792022012-12-04 09:50:33 +1000[diff] [blame]64 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]65 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggs88524bc2013-03-05 10:53:54 +1000[diff] [blame]66 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
Ben Skeggs1b4fea02013-10-11 15:38:15 +1000[diff] [blame]67 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
Martin Peresa10220b2012-11-04 01:01:53 +0100[diff] [blame]68 device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]69 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame]70 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]71 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
Ben Skeggs2c1a4252012-08-22 23:55:42 -0400[diff] [blame]72 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]73 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
74 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
75 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
Ben Skeggsff4b42c2013-10-15 09:38:12 +1000[diff] [blame^]76 device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
Ben Skeggs344e1072012-10-08 14:11:35 +1000[diff] [blame]77 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]78 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]79 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
Ben Skeggs30f4e082013-06-09 16:08:22 +1000[diff] [blame]80 device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
Ben Skeggs46654062012-08-28 14:10:39 +1000[diff] [blame]81 device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass;
Ben Skeggs4f326562012-08-06 19:28:02 +1000[diff] [blame]82 device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
83 device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
Ben Skeggsb0bc5302013-04-29 09:31:05 +1000[diff] [blame]84 device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
Ben Skeggsb2f04fc2012-11-22 15:42:23 +1000[diff] [blame]85 device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
Ben Skeggsa7416d02012-11-22 15:48:41 +1000[diff] [blame]86 device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
Ben Skeggsfb9bff22012-11-23 11:14:49 +1000[diff] [blame]87 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]88 break;
89 case 0xe7:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]90 device->cname = "GK107";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]91 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggsfa531bc2013-02-13 13:34:39 +1000[diff] [blame]92 device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
Ben Skeggs7dcd060c2013-02-16 15:21:58 +1000[diff] [blame]93 device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]94 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Ben Skeggsbc792022012-12-04 09:50:33 +1000[diff] [blame]95 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]96 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggs88524bc2013-03-05 10:53:54 +1000[diff] [blame]97 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
Ben Skeggs1b4fea02013-10-11 15:38:15 +1000[diff] [blame]98 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
Martin Peresa10220b2012-11-04 01:01:53 +0100[diff] [blame]99 device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]100 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame]101 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]102 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
Ben Skeggs2c1a4252012-08-22 23:55:42 -0400[diff] [blame]103 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]104 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
105 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
106 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
Ben Skeggsff4b42c2013-10-15 09:38:12 +1000[diff] [blame^]107 device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
Ben Skeggs344e1072012-10-08 14:11:35 +1000[diff] [blame]108 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]109 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]110 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
Ben Skeggs30f4e082013-06-09 16:08:22 +1000[diff] [blame]111 device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
Ben Skeggs46654062012-08-28 14:10:39 +1000[diff] [blame]112 device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass;
Ben Skeggs4f326562012-08-06 19:28:02 +1000[diff] [blame]113 device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
114 device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
Ben Skeggsb0bc5302013-04-29 09:31:05 +1000[diff] [blame]115 device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
Ben Skeggsb2f04fc2012-11-22 15:42:23 +1000[diff] [blame]116 device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
Ben Skeggsa7416d02012-11-22 15:48:41 +1000[diff] [blame]117 device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
Ben Skeggsfb9bff22012-11-23 11:14:49 +1000[diff] [blame]118 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]119 break;
Ben Skeggscaba5572012-12-06 14:45:57 +1000[diff] [blame]120 case 0xe6:
121 device->cname = "GK106";
122 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggsfa531bc2013-02-13 13:34:39 +1000[diff] [blame]123 device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
Ben Skeggs7dcd060c2013-02-16 15:21:58 +1000[diff] [blame]124 device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
Ben Skeggscaba5572012-12-06 14:45:57 +1000[diff] [blame]125 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Ben Skeggsbc792022012-12-04 09:50:33 +1000[diff] [blame]126 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
Ben Skeggscaba5572012-12-06 14:45:57 +1000[diff] [blame]127 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggs88524bc2013-03-05 10:53:54 +1000[diff] [blame]128 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
Ben Skeggs1b4fea02013-10-11 15:38:15 +1000[diff] [blame]129 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
Martin Peresa10220b2012-11-04 01:01:53 +0100[diff] [blame]130 device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
Ben Skeggscaba5572012-12-06 14:45:57 +1000[diff] [blame]131 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame]132 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
Ben Skeggscaba5572012-12-06 14:45:57 +1000[diff] [blame]133 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
134 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
135 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
136 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
137 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
Ben Skeggsff4b42c2013-10-15 09:38:12 +1000[diff] [blame^]138 device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
Ben Skeggscaba5572012-12-06 14:45:57 +1000[diff] [blame]139 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]140 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]141 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
Ben Skeggs30f4e082013-06-09 16:08:22 +1000[diff] [blame]142 device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
Ben Skeggscaba5572012-12-06 14:45:57 +1000[diff] [blame]143 device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass;
144 device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
145 device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
Ben Skeggsb0bc5302013-04-29 09:31:05 +1000[diff] [blame]146 device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
Ben Skeggscaba5572012-12-06 14:45:57 +1000[diff] [blame]147 device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
148 device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
149 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
150 break;
Ben Skeggs7b4f6382013-03-30 22:21:54 +1000[diff] [blame]151 case 0xf0:
152 device->cname = "GK110";
153 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
154 device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
155 device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
156 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
157 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
158 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggs88524bc2013-03-05 10:53:54 +1000[diff] [blame]159 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
Ben Skeggs1b4fea02013-10-11 15:38:15 +1000[diff] [blame]160 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
Ben Skeggs7b4f6382013-03-30 22:21:54 +1000[diff] [blame]161 device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
162 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame]163 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
Ben Skeggs7b4f6382013-03-30 22:21:54 +1000[diff] [blame]164 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
165 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
166 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
167 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
168 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
Ben Skeggsff4b42c2013-10-15 09:38:12 +1000[diff] [blame^]169 device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
Ben Skeggs7b4f6382013-03-30 22:21:54 +1000[diff] [blame]170 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]171 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]172 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
Ben Skeggs30f4e082013-06-09 16:08:22 +1000[diff] [blame]173 device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass;
Ben Skeggs7b4f6382013-03-30 22:21:54 +1000[diff] [blame]174 device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass;
Ben Skeggs7b4f6382013-03-30 22:21:54 +1000[diff] [blame]175 device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
176 device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
177 device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
Ben Skeggs9ec2dbb2013-05-02 12:38:41 +1000[diff] [blame]178#if 0
Ben Skeggs7b4f6382013-03-30 22:21:54 +1000[diff] [blame]179 device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
180 device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
181 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
182#endif
183 break;
Ben Skeggsaabf19c2013-11-05 13:14:25 +1000[diff] [blame]184 case 0x108:
185 device->cname = "GK208";
186 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
187 device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
188 device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
189 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
190 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
191 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
192 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
193 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
194 device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
195 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
196 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
197 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
198 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
199 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
200 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
201 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
Ben Skeggsff4b42c2013-10-15 09:38:12 +1000[diff] [blame^]202 device->oclass[NVDEV_SUBDEV_PWR ] = &nv108_pwr_oclass;
Ben Skeggsaabf19c2013-11-05 13:14:25 +1000[diff] [blame]203 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
204#if 0
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]205 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
Ben Skeggsaabf19c2013-11-05 13:14:25 +1000[diff] [blame]206 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
207 device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass;
208#endif
209 device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass;
210#if 0
211 device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
212 device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
213 device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
214 device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
215 device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
216 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
217#endif
218 break;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]219 default:
220 nv_fatal(device, "unknown Kepler chipset\n");
221 return -EINVAL;
222 }
223
224 return 0;
225}