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Felipe Balbi550a7372008-07-24 12:27:36 +03001/*
2 * MUSB OTG driver register defines
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35#ifndef __MUSB_REGS_H__
36#define __MUSB_REGS_H__
37
38#define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */
39
40/*
Felipe Balbi550a7372008-07-24 12:27:36 +030041 * MUSB Register bits
42 */
43
44/* POWER */
45#define MUSB_POWER_ISOUPDATE 0x80
46#define MUSB_POWER_SOFTCONN 0x40
47#define MUSB_POWER_HSENAB 0x20
48#define MUSB_POWER_HSMODE 0x10
49#define MUSB_POWER_RESET 0x08
50#define MUSB_POWER_RESUME 0x04
51#define MUSB_POWER_SUSPENDM 0x02
52#define MUSB_POWER_ENSUSPEND 0x01
53
54/* INTRUSB */
55#define MUSB_INTR_SUSPEND 0x01
56#define MUSB_INTR_RESUME 0x02
57#define MUSB_INTR_RESET 0x04
58#define MUSB_INTR_BABBLE 0x04
59#define MUSB_INTR_SOF 0x08
60#define MUSB_INTR_CONNECT 0x10
61#define MUSB_INTR_DISCONNECT 0x20
62#define MUSB_INTR_SESSREQ 0x40
63#define MUSB_INTR_VBUSERROR 0x80 /* For SESSION end */
64
65/* DEVCTL */
66#define MUSB_DEVCTL_BDEVICE 0x80
67#define MUSB_DEVCTL_FSDEV 0x40
68#define MUSB_DEVCTL_LSDEV 0x20
69#define MUSB_DEVCTL_VBUS 0x18
70#define MUSB_DEVCTL_VBUS_SHIFT 3
71#define MUSB_DEVCTL_HM 0x04
72#define MUSB_DEVCTL_HR 0x02
73#define MUSB_DEVCTL_SESSION 0x01
74
Ajay Kumar Gupta5fc4e772009-12-28 13:40:42 +020075/* MUSB ULPI VBUSCONTROL */
76#define MUSB_ULPI_USE_EXTVBUS 0x01
77#define MUSB_ULPI_USE_EXTVBUSIND 0x02
Heikki Krogerusffb865b2010-03-25 13:25:28 +020078/* ULPI_REG_CONTROL */
79#define MUSB_ULPI_REG_REQ (1 << 0)
80#define MUSB_ULPI_REG_CMPLT (1 << 1)
81#define MUSB_ULPI_RDN_WR (1 << 2)
Ajay Kumar Gupta5fc4e772009-12-28 13:40:42 +020082
Felipe Balbi550a7372008-07-24 12:27:36 +030083/* TESTMODE */
84#define MUSB_TEST_FORCE_HOST 0x80
85#define MUSB_TEST_FIFO_ACCESS 0x40
86#define MUSB_TEST_FORCE_FS 0x20
87#define MUSB_TEST_FORCE_HS 0x10
88#define MUSB_TEST_PACKET 0x08
89#define MUSB_TEST_K 0x04
90#define MUSB_TEST_J 0x02
91#define MUSB_TEST_SE0_NAK 0x01
92
93/* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
94#define MUSB_FIFOSZ_DPB 0x10
95/* Allocation size (8, 16, 32, ... 4096) */
96#define MUSB_FIFOSZ_SIZE 0x0f
97
98/* CSR0 */
99#define MUSB_CSR0_FLUSHFIFO 0x0100
100#define MUSB_CSR0_TXPKTRDY 0x0002
101#define MUSB_CSR0_RXPKTRDY 0x0001
102
103/* CSR0 in Peripheral mode */
104#define MUSB_CSR0_P_SVDSETUPEND 0x0080
105#define MUSB_CSR0_P_SVDRXPKTRDY 0x0040
106#define MUSB_CSR0_P_SENDSTALL 0x0020
107#define MUSB_CSR0_P_SETUPEND 0x0010
108#define MUSB_CSR0_P_DATAEND 0x0008
109#define MUSB_CSR0_P_SENTSTALL 0x0004
110
111/* CSR0 in Host mode */
112#define MUSB_CSR0_H_DIS_PING 0x0800
113#define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */
114#define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */
115#define MUSB_CSR0_H_NAKTIMEOUT 0x0080
116#define MUSB_CSR0_H_STATUSPKT 0x0040
117#define MUSB_CSR0_H_REQPKT 0x0020
118#define MUSB_CSR0_H_ERROR 0x0010
119#define MUSB_CSR0_H_SETUPPKT 0x0008
120#define MUSB_CSR0_H_RXSTALL 0x0004
121
122/* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
123#define MUSB_CSR0_P_WZC_BITS \
124 (MUSB_CSR0_P_SENTSTALL)
125#define MUSB_CSR0_H_WZC_BITS \
126 (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
127 | MUSB_CSR0_RXPKTRDY)
128
129/* TxType/RxType */
130#define MUSB_TYPE_SPEED 0xc0
131#define MUSB_TYPE_SPEED_SHIFT 6
132#define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */
133#define MUSB_TYPE_PROTO_SHIFT 4
134#define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */
135
136/* CONFIGDATA */
137#define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */
138#define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */
139#define MUSB_CONFIGDATA_BIGENDIAN 0x20
140#define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
141#define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
142#define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */
143#define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
144#define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */
145
146/* TXCSR in Peripheral and Host mode */
147#define MUSB_TXCSR_AUTOSET 0x8000
Felipe Balbi550a7372008-07-24 12:27:36 +0300148#define MUSB_TXCSR_DMAENAB 0x1000
149#define MUSB_TXCSR_FRCDATATOG 0x0800
150#define MUSB_TXCSR_DMAMODE 0x0400
151#define MUSB_TXCSR_CLRDATATOG 0x0040
152#define MUSB_TXCSR_FLUSHFIFO 0x0008
153#define MUSB_TXCSR_FIFONOTEMPTY 0x0002
154#define MUSB_TXCSR_TXPKTRDY 0x0001
155
156/* TXCSR in Peripheral mode */
157#define MUSB_TXCSR_P_ISO 0x4000
158#define MUSB_TXCSR_P_INCOMPTX 0x0080
159#define MUSB_TXCSR_P_SENTSTALL 0x0020
160#define MUSB_TXCSR_P_SENDSTALL 0x0010
161#define MUSB_TXCSR_P_UNDERRUN 0x0004
162
163/* TXCSR in Host mode */
164#define MUSB_TXCSR_H_WR_DATATOGGLE 0x0200
165#define MUSB_TXCSR_H_DATATOGGLE 0x0100
166#define MUSB_TXCSR_H_NAKTIMEOUT 0x0080
167#define MUSB_TXCSR_H_RXSTALL 0x0020
168#define MUSB_TXCSR_H_ERROR 0x0004
169
170/* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
171#define MUSB_TXCSR_P_WZC_BITS \
172 (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \
173 | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY)
174#define MUSB_TXCSR_H_WZC_BITS \
175 (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
176 | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY)
177
178/* RXCSR in Peripheral and Host mode */
179#define MUSB_RXCSR_AUTOCLEAR 0x8000
180#define MUSB_RXCSR_DMAENAB 0x2000
181#define MUSB_RXCSR_DISNYET 0x1000
182#define MUSB_RXCSR_PID_ERR 0x1000
183#define MUSB_RXCSR_DMAMODE 0x0800
184#define MUSB_RXCSR_INCOMPRX 0x0100
185#define MUSB_RXCSR_CLRDATATOG 0x0080
186#define MUSB_RXCSR_FLUSHFIFO 0x0010
187#define MUSB_RXCSR_DATAERROR 0x0008
188#define MUSB_RXCSR_FIFOFULL 0x0002
189#define MUSB_RXCSR_RXPKTRDY 0x0001
190
191/* RXCSR in Peripheral mode */
192#define MUSB_RXCSR_P_ISO 0x4000
193#define MUSB_RXCSR_P_SENTSTALL 0x0040
194#define MUSB_RXCSR_P_SENDSTALL 0x0020
195#define MUSB_RXCSR_P_OVERRUN 0x0004
196
197/* RXCSR in Host mode */
198#define MUSB_RXCSR_H_AUTOREQ 0x4000
199#define MUSB_RXCSR_H_WR_DATATOGGLE 0x0400
200#define MUSB_RXCSR_H_DATATOGGLE 0x0200
201#define MUSB_RXCSR_H_RXSTALL 0x0040
202#define MUSB_RXCSR_H_REQPKT 0x0020
203#define MUSB_RXCSR_H_ERROR 0x0004
204
205/* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
206#define MUSB_RXCSR_P_WZC_BITS \
207 (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
208 | MUSB_RXCSR_RXPKTRDY)
209#define MUSB_RXCSR_H_WZC_BITS \
210 (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
211 | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY)
212
213/* HUBADDR */
214#define MUSB_HUBADDR_MULTI_TT 0x80
215
Bryan Wuc6cf8b02008-12-02 21:33:48 +0200216
217#ifndef CONFIG_BLACKFIN
218
219/*
220 * Common USB registers
221 */
222
223#define MUSB_FADDR 0x00 /* 8-bit */
224#define MUSB_POWER 0x01 /* 8-bit */
225
226#define MUSB_INTRTX 0x02 /* 16-bit */
227#define MUSB_INTRRX 0x04
228#define MUSB_INTRTXE 0x06
229#define MUSB_INTRRXE 0x08
230#define MUSB_INTRUSB 0x0A /* 8 bit */
231#define MUSB_INTRUSBE 0x0B /* 8 bit */
232#define MUSB_FRAME 0x0C
233#define MUSB_INDEX 0x0E /* 8 bit */
234#define MUSB_TESTMODE 0x0F /* 8 bit */
235
236/* Get offset for a given FIFO from musb->mregs */
237#ifdef CONFIG_USB_TUSB6010
238#define MUSB_FIFO_OFFSET(epnum) (0x200 + ((epnum) * 0x20))
239#else
240#define MUSB_FIFO_OFFSET(epnum) (0x20 + ((epnum) * 4))
241#endif
242
243/*
244 * Additional Control Registers
245 */
246
247#define MUSB_DEVCTL 0x60 /* 8 bit */
248
249/* These are always controlled through the INDEX register */
250#define MUSB_TXFIFOSZ 0x62 /* 8-bit (see masks) */
251#define MUSB_RXFIFOSZ 0x63 /* 8-bit (see masks) */
252#define MUSB_TXFIFOADD 0x64 /* 16-bit offset shifted right 3 */
253#define MUSB_RXFIFOADD 0x66 /* 16-bit offset shifted right 3 */
254
255/* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
256#define MUSB_HWVERS 0x6C /* 8 bit */
Ajay Kumar Gupta5fc4e772009-12-28 13:40:42 +0200257#define MUSB_ULPI_BUSCONTROL 0x70 /* 8 bit */
Heikki Krogerusffb865b2010-03-25 13:25:28 +0200258#define MUSB_ULPI_INT_MASK 0x72 /* 8 bit */
259#define MUSB_ULPI_INT_SRC 0x73 /* 8 bit */
260#define MUSB_ULPI_REG_DATA 0x74 /* 8 bit */
261#define MUSB_ULPI_REG_ADDR 0x75 /* 8 bit */
262#define MUSB_ULPI_REG_CONTROL 0x76 /* 8 bit */
263#define MUSB_ULPI_RAW_DATA 0x77 /* 8 bit */
Bryan Wuc6cf8b02008-12-02 21:33:48 +0200264
265#define MUSB_EPINFO 0x78 /* 8 bit */
266#define MUSB_RAMINFO 0x79 /* 8 bit */
267#define MUSB_LINKINFO 0x7a /* 8 bit */
268#define MUSB_VPLEN 0x7b /* 8 bit */
269#define MUSB_HS_EOF1 0x7c /* 8 bit */
270#define MUSB_FS_EOF1 0x7d /* 8 bit */
271#define MUSB_LS_EOF1 0x7e /* 8 bit */
272
273/* Offsets to endpoint registers */
274#define MUSB_TXMAXP 0x00
275#define MUSB_TXCSR 0x02
276#define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */
277#define MUSB_RXMAXP 0x04
278#define MUSB_RXCSR 0x06
279#define MUSB_RXCOUNT 0x08
280#define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */
281#define MUSB_TXTYPE 0x0A
282#define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */
283#define MUSB_TXINTERVAL 0x0B
284#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */
285#define MUSB_RXTYPE 0x0C
286#define MUSB_RXINTERVAL 0x0D
287#define MUSB_FIFOSIZE 0x0F
288#define MUSB_CONFIGDATA MUSB_FIFOSIZE /* Re-used for EP0 */
289
290/* Offsets to endpoint registers in indexed model (using INDEX register) */
291#define MUSB_INDEXED_OFFSET(_epnum, _offset) \
292 (0x10 + (_offset))
293
294/* Offsets to endpoint registers in flat models */
295#define MUSB_FLAT_OFFSET(_epnum, _offset) \
296 (0x100 + (0x10*(_epnum)) + (_offset))
297
298#ifdef CONFIG_USB_TUSB6010
299/* TUSB6010 EP0 configuration register is special */
300#define MUSB_TUSB_OFFSET(_epnum, _offset) \
301 (0x10 + _offset)
302#include "tusb6010.h" /* Needed "only" for TUSB_EP0_CONF */
303#endif
304
305#define MUSB_TXCSR_MODE 0x2000
306
307/* "bus control"/target registers, for host side multipoint (external hubs) */
308#define MUSB_TXFUNCADDR 0x00
309#define MUSB_TXHUBADDR 0x02
310#define MUSB_TXHUBPORT 0x03
311
312#define MUSB_RXFUNCADDR 0x04
313#define MUSB_RXHUBADDR 0x06
314#define MUSB_RXHUBPORT 0x07
315
316#define MUSB_BUSCTL_OFFSET(_epnum, _offset) \
317 (0x80 + (8*(_epnum)) + (_offset))
318
319static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
320{
321 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
322}
323
324static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
325{
326 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
327}
328
329static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
330{
331 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
332}
333
334static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
335{
336 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
337}
338
Mike Frysingeradb3ee42010-03-12 10:27:21 +0200339static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
340{
341 musb_writeb(mbase, MUSB_ULPI_BUSCONTROL, val);
342}
343
Ajay Kumar Gupta4f712e02010-01-21 15:33:52 +0200344static inline u8 musb_read_txfifosz(void __iomem *mbase)
345{
346 return musb_readb(mbase, MUSB_TXFIFOSZ);
347}
348
349static inline u16 musb_read_txfifoadd(void __iomem *mbase)
350{
351 return musb_readw(mbase, MUSB_TXFIFOADD);
352}
353
354static inline u8 musb_read_rxfifosz(void __iomem *mbase)
355{
356 return musb_readb(mbase, MUSB_RXFIFOSZ);
357}
358
359static inline u16 musb_read_rxfifoadd(void __iomem *mbase)
360{
361 return musb_readw(mbase, MUSB_RXFIFOADD);
362}
363
Mike Frysingeradb3ee42010-03-12 10:27:21 +0200364static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
365{
366 return musb_readb(mbase, MUSB_ULPI_BUSCONTROL);
367}
368
Bryan Wuc6cf8b02008-12-02 21:33:48 +0200369static inline u8 musb_read_configdata(void __iomem *mbase)
370{
Ajay Kumar Gupta2bbff7b2009-07-27 14:32:15 -0700371 musb_writeb(mbase, MUSB_INDEX, 0);
Bryan Wuc6cf8b02008-12-02 21:33:48 +0200372 return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
373}
374
375static inline u16 musb_read_hwvers(void __iomem *mbase)
376{
377 return musb_readw(mbase, MUSB_HWVERS);
378}
379
380static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase)
381{
382 return (MUSB_BUSCTL_OFFSET(i, 0) + mbase);
383}
384
385static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs,
386 u8 qh_addr_reg)
387{
388 musb_writeb(ep_target_regs, MUSB_RXFUNCADDR, qh_addr_reg);
389}
390
391static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs,
392 u8 qh_h_addr_reg)
393{
394 musb_writeb(ep_target_regs, MUSB_RXHUBADDR, qh_h_addr_reg);
395}
396
397static inline void musb_write_rxhubport(void __iomem *ep_target_regs,
398 u8 qh_h_port_reg)
399{
400 musb_writeb(ep_target_regs, MUSB_RXHUBPORT, qh_h_port_reg);
401}
402
403static inline void musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
404 u8 qh_addr_reg)
405{
406 musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR),
407 qh_addr_reg);
408}
409
410static inline void musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
411 u8 qh_addr_reg)
412{
413 musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR),
414 qh_addr_reg);
415}
416
417static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum,
418 u8 qh_h_port_reg)
419{
420 musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT),
421 qh_h_port_reg);
422}
423
Ajay Kumar Gupta4f712e02010-01-21 15:33:52 +0200424static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
425{
426 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXFUNCADDR));
427}
428
429static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
430{
431 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBADDR));
432}
433
434static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
435{
436 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBPORT));
437}
438
439static inline u8 musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
440{
441 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR));
442}
443
444static inline u8 musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
445{
446 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR));
447}
448
449static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum)
450{
451 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT));
452}
453
Bryan Wuc6cf8b02008-12-02 21:33:48 +0200454#else /* CONFIG_BLACKFIN */
455
456#define USB_BASE USB_FADDR
457#define USB_OFFSET(reg) (reg - USB_BASE)
458
459/*
460 * Common USB registers
461 */
462#define MUSB_FADDR USB_OFFSET(USB_FADDR) /* 8-bit */
463#define MUSB_POWER USB_OFFSET(USB_POWER) /* 8-bit */
464#define MUSB_INTRTX USB_OFFSET(USB_INTRTX) /* 16-bit */
465#define MUSB_INTRRX USB_OFFSET(USB_INTRRX)
466#define MUSB_INTRTXE USB_OFFSET(USB_INTRTXE)
467#define MUSB_INTRRXE USB_OFFSET(USB_INTRRXE)
468#define MUSB_INTRUSB USB_OFFSET(USB_INTRUSB) /* 8 bit */
469#define MUSB_INTRUSBE USB_OFFSET(USB_INTRUSBE)/* 8 bit */
470#define MUSB_FRAME USB_OFFSET(USB_FRAME)
471#define MUSB_INDEX USB_OFFSET(USB_INDEX) /* 8 bit */
472#define MUSB_TESTMODE USB_OFFSET(USB_TESTMODE)/* 8 bit */
473
474/* Get offset for a given FIFO from musb->mregs */
475#define MUSB_FIFO_OFFSET(epnum) \
476 (USB_OFFSET(USB_EP0_FIFO) + ((epnum) * 8))
477
478/*
479 * Additional Control Registers
480 */
481
482#define MUSB_DEVCTL USB_OFFSET(USB_OTG_DEV_CTL) /* 8 bit */
483
484#define MUSB_LINKINFO USB_OFFSET(USB_LINKINFO)/* 8 bit */
485#define MUSB_VPLEN USB_OFFSET(USB_VPLEN) /* 8 bit */
486#define MUSB_HS_EOF1 USB_OFFSET(USB_HS_EOF1) /* 8 bit */
487#define MUSB_FS_EOF1 USB_OFFSET(USB_FS_EOF1) /* 8 bit */
488#define MUSB_LS_EOF1 USB_OFFSET(USB_LS_EOF1) /* 8 bit */
489
490/* Offsets to endpoint registers */
491#define MUSB_TXMAXP 0x00
492#define MUSB_TXCSR 0x04
493#define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */
494#define MUSB_RXMAXP 0x08
495#define MUSB_RXCSR 0x0C
496#define MUSB_RXCOUNT 0x10
497#define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */
498#define MUSB_TXTYPE 0x14
499#define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */
500#define MUSB_TXINTERVAL 0x18
501#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */
502#define MUSB_RXTYPE 0x1C
503#define MUSB_RXINTERVAL 0x20
504#define MUSB_TXCOUNT 0x28
505
506/* Offsets to endpoint registers in indexed model (using INDEX register) */
507#define MUSB_INDEXED_OFFSET(_epnum, _offset) \
508 (0x40 + (_offset))
509
510/* Offsets to endpoint registers in flat models */
511#define MUSB_FLAT_OFFSET(_epnum, _offset) \
512 (USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))
513
Daniel Mack3ad2f3f2010-02-03 08:01:28 +0800514/* Not implemented - HW has separate Tx/Rx FIFO */
Bryan Wuc6cf8b02008-12-02 21:33:48 +0200515#define MUSB_TXCSR_MODE 0x0000
516
Bryan Wuc6cf8b02008-12-02 21:33:48 +0200517static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
518{
519}
520
521static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
522{
523}
524
525static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
526{
527}
528
529static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
530{
531}
532
Mike Frysingeradb3ee42010-03-12 10:27:21 +0200533static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
534{
535}
536
Ajay Kumar Gupta4f712e02010-01-21 15:33:52 +0200537static inline u8 musb_read_txfifosz(void __iomem *mbase)
538{
Mike Frysinger7f4bca42010-03-12 10:27:23 +0200539 return 0;
Ajay Kumar Gupta4f712e02010-01-21 15:33:52 +0200540}
541
542static inline u16 musb_read_txfifoadd(void __iomem *mbase)
543{
Mike Frysinger7f4bca42010-03-12 10:27:23 +0200544 return 0;
Ajay Kumar Gupta4f712e02010-01-21 15:33:52 +0200545}
546
547static inline u8 musb_read_rxfifosz(void __iomem *mbase)
548{
Mike Frysinger7f4bca42010-03-12 10:27:23 +0200549 return 0;
Ajay Kumar Gupta4f712e02010-01-21 15:33:52 +0200550}
551
552static inline u16 musb_read_rxfifoadd(void __iomem *mbase)
553{
Mike Frysinger7f4bca42010-03-12 10:27:23 +0200554 return 0;
Ajay Kumar Gupta4f712e02010-01-21 15:33:52 +0200555}
556
Mike Frysingeradb3ee42010-03-12 10:27:21 +0200557static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
558{
559 return 0;
560}
561
Bryan Wuc6cf8b02008-12-02 21:33:48 +0200562static inline u8 musb_read_configdata(void __iomem *mbase)
563{
564 return 0;
565}
566
567static inline u16 musb_read_hwvers(void __iomem *mbase)
568{
Cliff Cai0ded2f12010-01-28 20:43:44 -0500569 /*
570 * This register is invisible on Blackfin, actually the MUSB
571 * RTL version of Blackfin is 1.9, so just harcode its value.
572 */
573 return MUSB_HWVERS_1900;
Bryan Wuc6cf8b02008-12-02 21:33:48 +0200574}
575
Bryan Wu92dea9f2009-11-16 16:19:20 +0530576static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase)
Bryan Wuc6cf8b02008-12-02 21:33:48 +0200577{
Bryan Wu92dea9f2009-11-16 16:19:20 +0530578 return NULL;
Bryan Wuc6cf8b02008-12-02 21:33:48 +0200579}
580
581static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs,
582 u8 qh_addr_req)
583{
584}
585
586static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs,
587 u8 qh_h_addr_reg)
588{
589}
590
591static inline void musb_write_rxhubport(void __iomem *ep_target_regs,
592 u8 qh_h_port_reg)
593{
594}
595
596static inline void musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
597 u8 qh_addr_reg)
598{
599}
600
601static inline void musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
602 u8 qh_addr_reg)
603{
604}
605
606static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum,
607 u8 qh_h_port_reg)
608{
609}
610
Ajay Kumar Gupta4f712e02010-01-21 15:33:52 +0200611static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
612{
Mike Frysinger7f4bca42010-03-12 10:27:23 +0200613 return 0;
Ajay Kumar Gupta4f712e02010-01-21 15:33:52 +0200614}
615
616static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
617{
Mike Frysinger7f4bca42010-03-12 10:27:23 +0200618 return 0;
Ajay Kumar Gupta4f712e02010-01-21 15:33:52 +0200619}
620
621static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
622{
Mike Frysinger7f4bca42010-03-12 10:27:23 +0200623 return 0;
Ajay Kumar Gupta4f712e02010-01-21 15:33:52 +0200624}
625
626static inline u8 musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
627{
Mike Frysinger7f4bca42010-03-12 10:27:23 +0200628 return 0;
Ajay Kumar Gupta4f712e02010-01-21 15:33:52 +0200629}
630
631static inline u8 musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
632{
Mike Frysinger7f4bca42010-03-12 10:27:23 +0200633 return 0;
Ajay Kumar Gupta4f712e02010-01-21 15:33:52 +0200634}
635
636static inline void musb_read_txhubport(void __iomem *mbase, u8 epnum)
637{
638}
639
Bryan Wuc6cf8b02008-12-02 21:33:48 +0200640#endif /* CONFIG_BLACKFIN */
641
Felipe Balbi550a7372008-07-24 12:27:36 +0300642#endif /* __MUSB_REGS_H__ */