Dave Gordon | 2617268 | 2015-07-09 19:29:04 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2014 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | */ |
| 23 | #ifndef _INTEL_GUC_FWIF_H |
| 24 | #define _INTEL_GUC_FWIF_H |
| 25 | |
| 26 | /* |
| 27 | * This file is partially autogenerated, although currently with some manual |
| 28 | * fixups afterwards. In future, it should be entirely autogenerated, in order |
| 29 | * to ensure that the definitions herein remain in sync with those used by the |
| 30 | * GuC's own firmware. |
| 31 | * |
| 32 | * EDITING THIS FILE IS THEREFORE NOT RECOMMENDED - YOUR CHANGES MAY BE LOST. |
| 33 | */ |
| 34 | |
Dave Gordon | 2617268 | 2015-07-09 19:29:04 +0100 | [diff] [blame] | 35 | #define GFXCORE_FAMILY_GEN9 12 |
Alex Dai | 33a732f | 2015-08-12 15:43:36 +0100 | [diff] [blame] | 36 | #define GFXCORE_FAMILY_UNKNOWN 0x7fffffff |
Dave Gordon | 2617268 | 2015-07-09 19:29:04 +0100 | [diff] [blame] | 37 | |
Dave Gordon | 44a28b1 | 2015-08-12 15:43:41 +0100 | [diff] [blame] | 38 | #define GUC_CTX_PRIORITY_KMD_HIGH 0 |
Dave Gordon | 2617268 | 2015-07-09 19:29:04 +0100 | [diff] [blame] | 39 | #define GUC_CTX_PRIORITY_HIGH 1 |
Dave Gordon | 44a28b1 | 2015-08-12 15:43:41 +0100 | [diff] [blame] | 40 | #define GUC_CTX_PRIORITY_KMD_NORMAL 2 |
| 41 | #define GUC_CTX_PRIORITY_NORMAL 3 |
Dave Gordon | 2617268 | 2015-07-09 19:29:04 +0100 | [diff] [blame] | 42 | |
| 43 | #define GUC_MAX_GPU_CONTEXTS 1024 |
Alex Dai | aa557ab | 2015-08-18 14:32:35 -0700 | [diff] [blame] | 44 | #define GUC_INVALID_CTX_ID GUC_MAX_GPU_CONTEXTS |
Dave Gordon | 2617268 | 2015-07-09 19:29:04 +0100 | [diff] [blame] | 45 | |
| 46 | /* Work queue item header definitions */ |
| 47 | #define WQ_STATUS_ACTIVE 1 |
| 48 | #define WQ_STATUS_SUSPENDED 2 |
| 49 | #define WQ_STATUS_CMD_ERROR 3 |
| 50 | #define WQ_STATUS_ENGINE_ID_NOT_USED 4 |
| 51 | #define WQ_STATUS_SUSPENDED_FROM_RESET 5 |
| 52 | #define WQ_TYPE_SHIFT 0 |
| 53 | #define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT) |
| 54 | #define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT) |
| 55 | #define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT) |
| 56 | #define WQ_TARGET_SHIFT 10 |
| 57 | #define WQ_LEN_SHIFT 16 |
| 58 | #define WQ_NO_WCFLUSH_WAIT (1 << 27) |
| 59 | #define WQ_PRESENT_WORKLOAD (1 << 28) |
| 60 | #define WQ_WORKLOAD_SHIFT 29 |
| 61 | #define WQ_WORKLOAD_GENERAL (0 << WQ_WORKLOAD_SHIFT) |
| 62 | #define WQ_WORKLOAD_GPGPU (1 << WQ_WORKLOAD_SHIFT) |
| 63 | #define WQ_WORKLOAD_TOUCH (2 << WQ_WORKLOAD_SHIFT) |
| 64 | |
| 65 | #define WQ_RING_TAIL_SHIFT 20 |
| 66 | #define WQ_RING_TAIL_MASK (0x7FF << WQ_RING_TAIL_SHIFT) |
| 67 | |
| 68 | #define GUC_DOORBELL_ENABLED 1 |
| 69 | #define GUC_DOORBELL_DISABLED 0 |
| 70 | |
| 71 | #define GUC_CTX_DESC_ATTR_ACTIVE (1 << 0) |
| 72 | #define GUC_CTX_DESC_ATTR_PENDING_DB (1 << 1) |
| 73 | #define GUC_CTX_DESC_ATTR_KERNEL (1 << 2) |
| 74 | #define GUC_CTX_DESC_ATTR_PREEMPT (1 << 3) |
| 75 | #define GUC_CTX_DESC_ATTR_RESET (1 << 4) |
| 76 | #define GUC_CTX_DESC_ATTR_WQLOCKED (1 << 5) |
| 77 | #define GUC_CTX_DESC_ATTR_PCH (1 << 6) |
Alex Dai | aa557ab | 2015-08-18 14:32:35 -0700 | [diff] [blame] | 78 | #define GUC_CTX_DESC_ATTR_TERMINATED (1 << 7) |
Dave Gordon | 2617268 | 2015-07-09 19:29:04 +0100 | [diff] [blame] | 79 | |
| 80 | /* The guc control data is 10 DWORDs */ |
| 81 | #define GUC_CTL_CTXINFO 0 |
| 82 | #define GUC_CTL_CTXNUM_IN16_SHIFT 0 |
| 83 | #define GUC_CTL_BASE_ADDR_SHIFT 12 |
| 84 | #define GUC_CTL_ARAT_HIGH 1 |
| 85 | #define GUC_CTL_ARAT_LOW 2 |
| 86 | #define GUC_CTL_DEVICE_INFO 3 |
| 87 | #define GUC_CTL_GTTYPE_SHIFT 0 |
| 88 | #define GUC_CTL_COREFAMILY_SHIFT 7 |
| 89 | #define GUC_CTL_LOG_PARAMS 4 |
| 90 | #define GUC_LOG_VALID (1 << 0) |
| 91 | #define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1) |
| 92 | #define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3) |
| 93 | #define GUC_LOG_CRASH_PAGES 1 |
| 94 | #define GUC_LOG_CRASH_SHIFT 4 |
| 95 | #define GUC_LOG_DPC_PAGES 3 |
| 96 | #define GUC_LOG_DPC_SHIFT 6 |
| 97 | #define GUC_LOG_ISR_PAGES 3 |
| 98 | #define GUC_LOG_ISR_SHIFT 9 |
| 99 | #define GUC_LOG_BUF_ADDR_SHIFT 12 |
| 100 | #define GUC_CTL_PAGE_FAULT_CONTROL 5 |
| 101 | #define GUC_CTL_WA 6 |
| 102 | #define GUC_CTL_WA_UK_BY_DRIVER (1 << 3) |
| 103 | #define GUC_CTL_FEATURE 7 |
| 104 | #define GUC_CTL_VCS2_ENABLED (1 << 0) |
| 105 | #define GUC_CTL_KERNEL_SUBMISSIONS (1 << 1) |
| 106 | #define GUC_CTL_FEATURE2 (1 << 2) |
| 107 | #define GUC_CTL_POWER_GATING (1 << 3) |
| 108 | #define GUC_CTL_DISABLE_SCHEDULER (1 << 4) |
| 109 | #define GUC_CTL_PREEMPTION_LOG (1 << 5) |
| 110 | #define GUC_CTL_ENABLE_SLPC (1 << 7) |
Alex Dai | aa557ab | 2015-08-18 14:32:35 -0700 | [diff] [blame] | 111 | #define GUC_CTL_RESET_ON_PREMPT_FAILURE (1 << 8) |
Dave Gordon | 2617268 | 2015-07-09 19:29:04 +0100 | [diff] [blame] | 112 | #define GUC_CTL_DEBUG 8 |
| 113 | #define GUC_LOG_VERBOSITY_SHIFT 0 |
| 114 | #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT) |
| 115 | #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT) |
| 116 | #define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT) |
| 117 | #define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT) |
| 118 | /* Verbosity range-check limits, without the shift */ |
| 119 | #define GUC_LOG_VERBOSITY_MIN 0 |
| 120 | #define GUC_LOG_VERBOSITY_MAX 3 |
Alex Dai | aa557ab | 2015-08-18 14:32:35 -0700 | [diff] [blame] | 121 | #define GUC_CTL_RSRVD 9 |
Dave Gordon | 2617268 | 2015-07-09 19:29:04 +0100 | [diff] [blame] | 122 | |
Alex Dai | aa557ab | 2015-08-18 14:32:35 -0700 | [diff] [blame] | 123 | #define GUC_CTL_MAX_DWORDS (GUC_CTL_RSRVD + 1) |
Dave Gordon | 2617268 | 2015-07-09 19:29:04 +0100 | [diff] [blame] | 124 | |
| 125 | struct guc_doorbell_info { |
| 126 | u32 db_status; |
| 127 | u32 cookie; |
| 128 | u32 reserved[14]; |
| 129 | } __packed; |
| 130 | |
| 131 | union guc_doorbell_qw { |
| 132 | struct { |
| 133 | u32 db_status; |
| 134 | u32 cookie; |
| 135 | }; |
| 136 | u64 value_qw; |
| 137 | } __packed; |
| 138 | |
| 139 | #define GUC_MAX_DOORBELLS 256 |
| 140 | #define GUC_INVALID_DOORBELL_ID (GUC_MAX_DOORBELLS) |
| 141 | |
| 142 | #define GUC_DB_SIZE (PAGE_SIZE) |
| 143 | #define GUC_WQ_SIZE (PAGE_SIZE * 2) |
| 144 | |
| 145 | /* Work item for submitting workloads into work queue of GuC. */ |
| 146 | struct guc_wq_item { |
| 147 | u32 header; |
| 148 | u32 context_desc; |
| 149 | u32 ring_tail; |
| 150 | u32 fence_id; |
| 151 | } __packed; |
| 152 | |
| 153 | struct guc_process_desc { |
| 154 | u32 context_id; |
| 155 | u64 db_base_addr; |
| 156 | u32 head; |
| 157 | u32 tail; |
| 158 | u32 error_offset; |
| 159 | u64 wq_base_addr; |
| 160 | u32 wq_size_bytes; |
| 161 | u32 wq_status; |
| 162 | u32 engine_presence; |
| 163 | u32 priority; |
| 164 | u32 reserved[30]; |
| 165 | } __packed; |
| 166 | |
| 167 | /* engine id and context id is packed into guc_execlist_context.context_id*/ |
| 168 | #define GUC_ELC_CTXID_OFFSET 0 |
| 169 | #define GUC_ELC_ENGINE_OFFSET 29 |
| 170 | |
| 171 | /* The execlist context including software and HW information */ |
| 172 | struct guc_execlist_context { |
| 173 | u32 context_desc; |
| 174 | u32 context_id; |
| 175 | u32 ring_status; |
| 176 | u32 ring_lcra; |
| 177 | u32 ring_begin; |
| 178 | u32 ring_end; |
| 179 | u32 ring_next_free_location; |
| 180 | u32 ring_current_tail_pointer_value; |
| 181 | u8 engine_state_submit_value; |
| 182 | u8 engine_state_wait_value; |
| 183 | u16 pagefault_count; |
| 184 | u16 engine_submit_queue_count; |
| 185 | } __packed; |
| 186 | |
| 187 | /*Context descriptor for communicating between uKernel and Driver*/ |
| 188 | struct guc_context_desc { |
| 189 | u32 sched_common_area; |
| 190 | u32 context_id; |
| 191 | u32 pas_id; |
| 192 | u8 engines_used; |
| 193 | u64 db_trigger_cpu; |
| 194 | u32 db_trigger_uk; |
| 195 | u64 db_trigger_phy; |
| 196 | u16 db_id; |
| 197 | |
| 198 | struct guc_execlist_context lrc[I915_NUM_RINGS]; |
| 199 | |
| 200 | u8 attribute; |
| 201 | |
| 202 | u32 priority; |
| 203 | |
| 204 | u32 wq_sampled_tail_offset; |
| 205 | u32 wq_total_submit_enqueues; |
| 206 | |
| 207 | u32 process_desc; |
| 208 | u32 wq_addr; |
| 209 | u32 wq_size; |
| 210 | |
| 211 | u32 engine_presence; |
| 212 | |
Alex Dai | aa557ab | 2015-08-18 14:32:35 -0700 | [diff] [blame] | 213 | u8 engine_suspended; |
| 214 | |
| 215 | u8 reserved0[3]; |
Dave Gordon | 2617268 | 2015-07-09 19:29:04 +0100 | [diff] [blame] | 216 | u64 reserved1[1]; |
| 217 | |
| 218 | u64 desc_private; |
| 219 | } __packed; |
| 220 | |
Alex Dai | 93f2531 | 2015-09-25 11:46:56 -0700 | [diff] [blame] | 221 | #define GUC_FORCEWAKE_RENDER (1 << 0) |
| 222 | #define GUC_FORCEWAKE_MEDIA (1 << 1) |
| 223 | |
Alex Dai | a1c4199 | 2015-09-30 09:46:37 -0700 | [diff] [blame] | 224 | #define GUC_POWER_UNSPECIFIED 0 |
| 225 | #define GUC_POWER_D0 1 |
| 226 | #define GUC_POWER_D1 2 |
| 227 | #define GUC_POWER_D2 3 |
| 228 | #define GUC_POWER_D3 4 |
| 229 | |
Dave Gordon | 2617268 | 2015-07-09 19:29:04 +0100 | [diff] [blame] | 230 | /* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */ |
| 231 | enum host2guc_action { |
| 232 | HOST2GUC_ACTION_DEFAULT = 0x0, |
| 233 | HOST2GUC_ACTION_SAMPLE_FORCEWAKE = 0x6, |
| 234 | HOST2GUC_ACTION_ALLOCATE_DOORBELL = 0x10, |
| 235 | HOST2GUC_ACTION_DEALLOCATE_DOORBELL = 0x20, |
Alex Dai | a1c4199 | 2015-09-30 09:46:37 -0700 | [diff] [blame] | 236 | HOST2GUC_ACTION_ENTER_S_STATE = 0x501, |
| 237 | HOST2GUC_ACTION_EXIT_S_STATE = 0x502, |
Dave Gordon | 2617268 | 2015-07-09 19:29:04 +0100 | [diff] [blame] | 238 | HOST2GUC_ACTION_SLPC_REQUEST = 0x3003, |
| 239 | HOST2GUC_ACTION_LIMIT |
| 240 | }; |
| 241 | |
| 242 | /* |
| 243 | * The GuC sends its response to a command by overwriting the |
| 244 | * command in SS0. The response is distinguishable from a command |
| 245 | * by the fact that all the MASK bits are set. The remaining bits |
| 246 | * give more detail. |
| 247 | */ |
| 248 | #define GUC2HOST_RESPONSE_MASK ((u32)0xF0000000) |
| 249 | #define GUC2HOST_IS_RESPONSE(x) ((u32)(x) >= GUC2HOST_RESPONSE_MASK) |
| 250 | #define GUC2HOST_STATUS(x) (GUC2HOST_RESPONSE_MASK | (x)) |
| 251 | |
| 252 | /* GUC will return status back to SOFT_SCRATCH_O_REG */ |
| 253 | enum guc2host_status { |
| 254 | GUC2HOST_STATUS_SUCCESS = GUC2HOST_STATUS(0x0), |
| 255 | GUC2HOST_STATUS_ALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x10), |
| 256 | GUC2HOST_STATUS_DEALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x20), |
| 257 | GUC2HOST_STATUS_GENERIC_FAIL = GUC2HOST_STATUS(0x0000F000) |
| 258 | }; |
| 259 | |
| 260 | #endif |