Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / refs/heads/int/10/fp3 / . / drivers / phy / phy-qcom-ufs-qrbtc-sdm845.h
blob: ddcf4192bfa2cf6c7affa0c8eee701f77d51a103 [file] [log] [blame]
Subhash Jadavanid6cf9e62016-08-04 11:41:09 -0700[diff] [blame]1/*
2 * Copyright (c) 2016, Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
Kyle Yan6a20fae2017-02-14 13:34:41 -0800[diff] [blame]15#ifndef UFS_QCOM_PHY_QRBTC_SDM845_H_
16#define UFS_QCOM_PHY_QRBTC_SDM845_H_
Subhash Jadavanid6cf9e62016-08-04 11:41:09 -0700[diff] [blame]17
18#include "phy-qcom-ufs-i.h"
19
20/* QCOM UFS PHY control registers */
21#define COM_OFF(x) (0x000 + x)
22#define TX_OFF(n, x) (0x400 + (0x400 * n) + x)
23#define RX_OFF(n, x) (0x600 + (0x400 * n) + x)
24#define PHY_OFF(x) (0xC00 + x)
25#define PHY_USR(x) (x)
26
27/* UFS PHY PLL block registers */
28#define QSERDES_COM_SYS_CLK_CTRL COM_OFF(0x00)
29#define QSERDES_COM_PLL_VCOTAIL_EN COM_OFF(0x04)
30#define QSERDES_COM_PLL_CNTRL COM_OFF(0x14)
31#define QSERDES_COM_PLL_IP_SETI COM_OFF(0x18)
32#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN COM_OFF(0x20)
33#define QSERDES_COM_PLL_CP_SETI COM_OFF(0x24)
34#define QSERDES_COM_PLL_IP_SETP COM_OFF(0x28)
35#define QSERDES_COM_PLL_CP_SETP COM_OFF(0x2C)
36#define QSERDES_COM_SYSCLK_EN_SEL COM_OFF(0x38)
37#define QSERDES_COM_RES_CODE_TXBAND COM_OFF(0x3C)
38#define QSERDES_COM_RESETSM_CNTRL COM_OFF(0x40)
39#define QSERDES_COM_PLLLOCK_CMP1 COM_OFF(0x44)
40#define QSERDES_COM_PLLLOCK_CMP2 COM_OFF(0x48)
41#define QSERDES_COM_PLLLOCK_CMP3 COM_OFF(0x4C)
42#define QSERDES_COM_PLLLOCK_CMP_EN COM_OFF(0x50)
43#define QSERDES_COM_DEC_START1 COM_OFF(0x64)
44#define QSERDES_COM_DIV_FRAC_START1 COM_OFF(0x98)
45#define QSERDES_COM_DIV_FRAC_START2 COM_OFF(0x9C)
46#define QSERDES_COM_DIV_FRAC_START3 COM_OFF(0xA0)
47#define QSERDES_COM_DEC_START2 COM_OFF(0xA4)
48#define QSERDES_COM_PLL_RXTXEPCLK_EN COM_OFF(0xA8)
49#define QSERDES_COM_PLL_CRCTRL COM_OFF(0xAC)
50#define QSERDES_COM_PLL_CLKEPDIV COM_OFF(0xB0)
51#define QSERDES_COM_RESET_SM COM_OFF(0xBC)
52
Subhash Jadavaniea0f3de2016-12-13 16:43:47 -0800[diff] [blame]53/* TX LANE n (0, 1) registers */
54#define QSERDES_TX_CLKBUF_ENABLE(n) TX_OFF(n, 0x4)
55
Subhash Jadavanid6cf9e62016-08-04 11:41:09 -0700[diff] [blame]56/* RX LANE n (0, 1) registers */
57#define QSERDES_RX_CDR_CONTROL(n) RX_OFF(n, 0x0)
58#define QSERDES_RX_RX_IQ_RXDET_EN(n) RX_OFF(n, 0x28)
59#define QSERDES_RX_SIGDET_CNTRL(n) RX_OFF(n, 0x34)
60#define QSERDES_RX_RX_BAND(n) RX_OFF(n, 0x38)
61#define QSERDES_RX_CDR_CONTROL_HALF(n) RX_OFF(n, 0x98)
62#define QSERDES_RX_CDR_CONTROL_QUARTER(n) RX_OFF(n, 0x9C)
63#define QSERDES_RX_PWM_CNTRL1(n) RX_OFF(n, 0x80)
64#define QSERDES_RX_PWM_CNTRL2(n) RX_OFF(n, 0x84)
65#define QSERDES_RX_PWM_NDIV(n) RX_OFF(n, 0x88)
66#define QSERDES_RX_SIGDET_CNTRL2(n) RX_OFF(n, 0x8C)
67#define QSERDES_RX_UFS_CNTRL(n) RX_OFF(n, 0x90)
68
69/* UFS PHY registers */
70#define UFS_PHY_PHY_START PHY_OFF(0x00)
71#define UFS_PHY_POWER_DOWN_CONTROL PHY_OFF(0x04)
72#define UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB PHY_OFF(0x08)
73#define UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB PHY_OFF(0x0C)
74#define UFS_PHY_RX_SYM_RESYNC_CTRL PHY_OFF(0x134)
Subhash Jadavani7865e3c2016-09-08 17:55:36 -0700[diff] [blame]75#define UFS_PHY_MULTI_LANE_CTRL1 PHY_OFF(0x1C4)
Subhash Jadavanid6cf9e62016-08-04 11:41:09 -0700[diff] [blame]76
77/* QRBTC V2 USER REGISTERS */
78#define U11_UFS_RESET_REG_OFFSET PHY_USR(0x4)
79#define U11_QRBTC_CONTROL_OFFSET PHY_USR(0x18)
80#define U11_QRBTC_TX_CLK_CTRL PHY_USR(0x20)
81
82static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = {
83 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PHY_START, 0x00),
84 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x00),
85 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYM_RESYNC_CTRL, 0x03),
86 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB, 0x0F),
87 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB, 0x00),
88
89 /* QSERDES Common */
90 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3F),
91 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0x03),
92 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x16),
93 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RES_CODE_TXBAND, 0xC0),
94 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_VCOTAIL_EN, 0x03),
95 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CNTRL, 0x24),
96 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),
97 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x10),
98 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x13),
99 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0x43),
100
Subhash Jadavaniea0f3de2016-12-13 16:43:47 -0800[diff] [blame]101 /* QSERDES TX */
102 /* Enable large amplitude setting */
103 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_CLKBUF_ENABLE(0), 0x29),
104 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_CLKBUF_ENABLE(1), 0x29),
105
Subhash Jadavanid6cf9e62016-08-04 11:41:09 -0700[diff] [blame]106 /* QSERDES RX0 */
107 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_CNTRL1(0), 0x08),
108 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_CNTRL2(0), 0x40),
109 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_NDIV(0), 0x30),
110 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL(0), 0x40),
111 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x0C),
112 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x12),
113 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL(0), 0xC0),
114 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL2(0), 0x07),
115 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_BAND(0), 0x06),
116 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UFS_CNTRL(0), 0x00),
117 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_IQ_RXDET_EN(0), 0xF3),
118
119 /* QSERDES RX1 */
120 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_CNTRL1(1), 0x08),
121 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_CNTRL2(1), 0x40),
122 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_NDIV(1), 0x30),
123 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL(1), 0x40),
124 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x0C),
125 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x12),
126 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL(1), 0xC0),
127 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL2(1), 0x07),
128 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_BAND(1), 0x06),
129 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UFS_CNTRL(1), 0x00),
130 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_IQ_RXDET_EN(1), 0xF3),
131
132 /* QSERDES PLL Settings - Series A */
133 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x82),
134 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),
135 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),
136 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),
137 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x10),
138 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0xFF),
139 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x19),
140 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),
141 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),
142 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x07),
143 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x0F),
144 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x07),
145 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x01),
Subhash Jadavani7865e3c2016-09-08 17:55:36 -0700[diff] [blame]146
147 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_MULTI_LANE_CTRL1, 0x02),
Subhash Jadavanid6cf9e62016-08-04 11:41:09 -0700[diff] [blame]148};
149
150static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {
151 /* QSERDES PLL Settings - Series B */
152 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x98),
153 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),
154 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),
155 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),
156 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x10),
157 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0x65),
158 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x1E),
159 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),
160 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),
161 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x07),
162 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x0F),
163 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x07),
164 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x01),
165};
166
167
168/*
Kyle Yan6a20fae2017-02-14 13:34:41 -0800[diff] [blame]169 * This structure represents the qrbtc-sdm845 specific phy.
Subhash Jadavanid6cf9e62016-08-04 11:41:09 -0700[diff] [blame]170 * common_cfg MUST remain the first field in this structure
171 * in case extra fields are added. This way, when calling
172 * get_ufs_qcom_phy() of generic phy, we can extract the
173 * common phy structure (struct ufs_qcom_phy) out of it
174 * regardless of the relevant specific phy.
175 */
Kyle Yan6a20fae2017-02-14 13:34:41 -0800[diff] [blame]176struct ufs_qcom_phy_qrbtc_sdm845 {
Subhash Jadavanid6cf9e62016-08-04 11:41:09 -0700[diff] [blame]177 struct ufs_qcom_phy common_cfg;
178};
179
180#endif