| Sachin Bhayare | 2043571 | 2018-01-15 09:57:00 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | &soc { |
| 14 | mdss_dsi0_pll: qcom,mdss_dsi_pll@994400 { |
| 15 | compatible = "qcom,mdss_dsi_pll_8953"; |
| 16 | label = "MDSS DSI 0 PLL"; |
| 17 | cell-index = <0>; |
| 18 | #clock-cells = <1>; |
| 19 | |
| 20 | reg = <0x01a94400 0x588>, |
| 21 | <0x0184d074 0x8>, |
| 22 | <0x01a94200 0x98>; |
| 23 | reg-names = "pll_base", "gdsc_base", "dynamic_pll_base"; |
| 24 | |
| 25 | gdsc-supply = <&gdsc_mdss>; |
| 26 | |
| 27 | clocks = <&clock_gcc clk_gcc_mdss_ahb_clk>; |
| 28 | clock-names = "iface_clk"; |
| 29 | clock-rate = <0>; |
| 30 | |
| 31 | qcom,dsi-pll-ssc-en; |
| 32 | qcom,dsi-pll-ssc-mode = "down-spread"; |
| 33 | /* Memory region for passing dynamic refresh pll codes */ |
| 34 | memory-region = <&dfps_data_mem>; |
| 35 | |
| 36 | qcom,platform-supply-entries { |
| 37 | #address-cells = <1>; |
| 38 | #size-cells = <0>; |
| 39 | |
| 40 | qcom,platform-supply-entry@0 { |
| 41 | reg = <0>; |
| 42 | qcom,supply-name = "gdsc"; |
| 43 | qcom,supply-min-voltage = <0>; |
| 44 | qcom,supply-max-voltage = <0>; |
| 45 | qcom,supply-enable-load = <0>; |
| 46 | qcom,supply-disable-load = <0>; |
| 47 | }; |
| 48 | }; |
| 49 | }; |
| 50 | |
| 51 | mdss_dsi1_pll: qcom,mdss_dsi_pll@996400 { |
| 52 | compatible = "qcom,mdss_dsi_pll_8953"; |
| 53 | label = "MDSS DSI 1 PLL"; |
| 54 | cell-index = <1>; |
| 55 | #clock-cells = <1>; |
| 56 | |
| 57 | reg = <0x01a96400 0x588>, |
| 58 | <0x0184d074 0x8>, |
| 59 | <0x01a96200 0x98>; |
| 60 | reg-names = "pll_base", "gdsc_base", "dynamic_pll_base"; |
| 61 | |
| 62 | gdsc-supply = <&gdsc_mdss>; |
| 63 | |
| 64 | qcom,dsi-pll-ssc-en; |
| 65 | qcom,dsi-pll-ssc-mode = "down-spread"; |
| 66 | clocks = <&clock_gcc clk_gcc_mdss_ahb_clk>; |
| 67 | clock-names = "iface_clk"; |
| 68 | clock-rate = <0>; |
| 69 | |
| 70 | qcom,platform-supply-entries { |
| 71 | #address-cells = <1>; |
| 72 | #size-cells = <0>; |
| 73 | |
| 74 | qcom,platform-supply-entry@0 { |
| 75 | reg = <0>; |
| 76 | qcom,supply-name = "gdsc"; |
| 77 | qcom,supply-min-voltage = <0>; |
| 78 | qcom,supply-max-voltage = <0>; |
| 79 | qcom,supply-enable-load = <0>; |
| 80 | qcom,supply-disable-load = <0>; |
| 81 | }; |
| 82 | }; |
| 83 | }; |
| 84 | }; |