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Afzal Mohammed246da262012-08-02 20:02:10 +05301GPMC (General Purpose Memory Controller):
2=========================================
3
4GPMC is an unified memory controller dedicated to interfacing external
5memory devices like
6 * Asynchronous SRAM like memories and application specific integrated
7 circuit devices.
8 * Asynchronous, synchronous, and page mode burst NOR flash devices
9 NAND flash
10 * Pseudo-SRAM devices
11
12GPMC is found on Texas Instruments SoC's (OMAP based)
13IP details: http://www.ti.com/lit/pdf/spruh73 section 7.1
14
15
16GPMC generic timing calculation:
17================================
18
19GPMC has certain timings that has to be programmed for proper
20functioning of the peripheral, while peripheral has another set of
21timings. To have peripheral work with gpmc, peripheral timings has to
22be translated to the form gpmc can understand. The way it has to be
23translated depends on the connected peripheral. Also there is a
24dependency for certain gpmc timings on gpmc clock frequency. Hence a
25generic timing routine was developed to achieve above requirements.
26
27Generic routine provides a generic method to calculate gpmc timings
28from gpmc peripheral timings. struct gpmc_device_timings fields has to
29be updated with timings from the datasheet of the peripheral that is
30connected to gpmc. A few of the peripheral timings can be fed either
31in time or in cycles, provision to handle this scenario has been
32provided (refer struct gpmc_device_timings definition). It may so
33happen that timing as specified by peripheral datasheet is not present
34in timing structure, in this scenario, try to correlate peripheral
35timing to the one available. If that doesn't work, try to add a new
36field as required by peripheral, educate generic timing routine to
37handle it, make sure that it does not break any of the existing.
38Then there may be cases where peripheral datasheet doesn't mention
39certain fields of struct gpmc_device_timings, zero those entries.
40
41Generic timing routine has been verified to work properly on
42multiple onenand's and tusb6010 peripherals.
43
44A word of caution: generic timing routine has been developed based
45on understanding of gpmc timings, peripheral timings, available
46custom timing routines, a kind of reverse engineering without
47most of the datasheets & hardware (to be exact none of those supported
48in mainline having custom timing routine) and by simulation.
49
50gpmc timing dependency on peripheral timings:
51[<gpmc_timing>: <peripheral timing1>, <peripheral timing2> ...]
52
531. common
54cs_on: t_ceasu
55adv_on: t_avdasu, t_ceavd
56
572. sync common
58sync_clk: clk
59page_burst_access: t_bacc
60clk_activation: t_ces, t_avds
61
623. read async muxed
63adv_rd_off: t_avdp_r
64oe_on: t_oeasu, t_aavdh
65access: t_iaa, t_oe, t_ce, t_aa
66rd_cycle: t_rd_cycle, t_cez_r, t_oez
67
684. read async non-muxed
69adv_rd_off: t_avdp_r
70oe_on: t_oeasu
71access: t_iaa, t_oe, t_ce, t_aa
72rd_cycle: t_rd_cycle, t_cez_r, t_oez
73
745. read sync muxed
75adv_rd_off: t_avdp_r, t_avdh
76oe_on: t_oeasu, t_ach, cyc_aavdh_oe
77access: t_iaa, cyc_iaa, cyc_oe
78rd_cycle: t_cez_r, t_oez, t_ce_rdyz
79
806. read sync non-muxed
81adv_rd_off: t_avdp_r
82oe_on: t_oeasu
83access: t_iaa, cyc_iaa, cyc_oe
84rd_cycle: t_cez_r, t_oez, t_ce_rdyz
85
867. write async muxed
87adv_wr_off: t_avdp_w
88we_on, wr_data_mux_bus: t_weasu, t_aavdh, cyc_aavhd_we
89we_off: t_wpl
90cs_wr_off: t_wph
91wr_cycle: t_cez_w, t_wr_cycle
92
938. write async non-muxed
94adv_wr_off: t_avdp_w
95we_on, wr_data_mux_bus: t_weasu
96we_off: t_wpl
97cs_wr_off: t_wph
98wr_cycle: t_cez_w, t_wr_cycle
99
1009. write sync muxed
101adv_wr_off: t_avdp_w, t_avdh
102we_on, wr_data_mux_bus: t_weasu, t_rdyo, t_aavdh, cyc_aavhd_we
103we_off: t_wpl, cyc_wpl
104cs_wr_off: t_wph
105wr_cycle: t_cez_w, t_ce_rdyz
106
10710. write sync non-muxed
108adv_wr_off: t_avdp_w
109we_on, wr_data_mux_bus: t_weasu, t_rdyo
110we_off: t_wpl, cyc_wpl
111cs_wr_off: t_wph
112wr_cycle: t_cez_w, t_ce_rdyz
113
114
115Note: Many of gpmc timings are dependent on other gpmc timings (a few
116gpmc timings purely dependent on other gpmc timings, a reason that
117some of the gpmc timings are missing above), and it will result in
118indirect dependency of peripheral timings to gpmc timings other than
119mentioned above, refer timing routine for more details. To know what
120these peripheral timings correspond to, please see explanations in
121struct gpmc_device_timings definition. And for gpmc timings refer
122IP details (link above).