Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 1 | /* |
| 2 | * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code. |
| 3 | * |
| 4 | * ARMv7 support: Jean Pihet <jpihet@mvista.com> |
| 5 | * 2010 (c) MontaVista Software, LLC. |
| 6 | * |
| 7 | * Copied from ARMv6 code, with the low level code inspired |
| 8 | * by the ARMv7 Oprofile code. |
| 9 | * |
| 10 | * Cortex-A8 has up to 4 configurable performance counters and |
| 11 | * a single cycle counter. |
| 12 | * Cortex-A9 has up to 31 configurable performance counters and |
| 13 | * a single cycle counter. |
| 14 | * |
| 15 | * All counters can be enabled/disabled and IRQ masked separately. The cycle |
| 16 | * counter and all 4 performance counters together can be reset separately. |
| 17 | */ |
| 18 | |
| 19 | #ifdef CONFIG_CPU_V7 |
Will Deacon | a505add | 2011-07-19 13:53:36 +0100 | [diff] [blame] | 20 | |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 21 | #include <asm/cp15.h> |
Mark Rutland | 29ba0f3 | 2015-05-26 17:23:38 +0100 | [diff] [blame] | 22 | #include <asm/cputype.h> |
| 23 | #include <asm/irq_regs.h> |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 24 | #include <asm/vfp.h> |
| 25 | #include "../vfp/vfpinstr.h" |
| 26 | |
Mark Rutland | 29ba0f3 | 2015-05-26 17:23:38 +0100 | [diff] [blame] | 27 | #include <linux/of.h> |
Mark Rutland | fa8ad78 | 2015-07-06 12:23:53 +0100 | [diff] [blame] | 28 | #include <linux/perf/arm_pmu.h> |
Mark Rutland | 29ba0f3 | 2015-05-26 17:23:38 +0100 | [diff] [blame] | 29 | #include <linux/platform_device.h> |
| 30 | |
Will Deacon | 6d4eaf9 | 2011-01-19 14:15:34 +0000 | [diff] [blame] | 31 | /* |
| 32 | * Common ARMv7 event types |
| 33 | * |
| 34 | * Note: An implementation may not be able to count all of these events |
| 35 | * but the encodings are considered to be `reserved' in the case that |
| 36 | * they are not available. |
| 37 | */ |
Drew Richardson | f4ab36c | 2015-10-28 08:19:56 -0700 | [diff] [blame] | 38 | #define ARMV7_PERFCTR_PMNC_SW_INCR 0x00 |
| 39 | #define ARMV7_PERFCTR_L1_ICACHE_REFILL 0x01 |
| 40 | #define ARMV7_PERFCTR_ITLB_REFILL 0x02 |
| 41 | #define ARMV7_PERFCTR_L1_DCACHE_REFILL 0x03 |
| 42 | #define ARMV7_PERFCTR_L1_DCACHE_ACCESS 0x04 |
| 43 | #define ARMV7_PERFCTR_DTLB_REFILL 0x05 |
| 44 | #define ARMV7_PERFCTR_MEM_READ 0x06 |
| 45 | #define ARMV7_PERFCTR_MEM_WRITE 0x07 |
| 46 | #define ARMV7_PERFCTR_INSTR_EXECUTED 0x08 |
| 47 | #define ARMV7_PERFCTR_EXC_TAKEN 0x09 |
| 48 | #define ARMV7_PERFCTR_EXC_EXECUTED 0x0A |
| 49 | #define ARMV7_PERFCTR_CID_WRITE 0x0B |
Will Deacon | 4d30151 | 2011-09-29 15:29:02 +0100 | [diff] [blame] | 50 | |
Drew Richardson | f4ab36c | 2015-10-28 08:19:56 -0700 | [diff] [blame] | 51 | /* |
| 52 | * ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS. |
| 53 | * It counts: |
| 54 | * - all (taken) branch instructions, |
| 55 | * - instructions that explicitly write the PC, |
| 56 | * - exception generating instructions. |
| 57 | */ |
| 58 | #define ARMV7_PERFCTR_PC_WRITE 0x0C |
| 59 | #define ARMV7_PERFCTR_PC_IMM_BRANCH 0x0D |
| 60 | #define ARMV7_PERFCTR_PC_PROC_RETURN 0x0E |
| 61 | #define ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS 0x0F |
| 62 | #define ARMV7_PERFCTR_PC_BRANCH_MIS_PRED 0x10 |
| 63 | #define ARMV7_PERFCTR_CLOCK_CYCLES 0x11 |
| 64 | #define ARMV7_PERFCTR_PC_BRANCH_PRED 0x12 |
Will Deacon | 6d4eaf9 | 2011-01-19 14:15:34 +0000 | [diff] [blame] | 65 | |
Drew Richardson | f4ab36c | 2015-10-28 08:19:56 -0700 | [diff] [blame] | 66 | /* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */ |
| 67 | #define ARMV7_PERFCTR_MEM_ACCESS 0x13 |
| 68 | #define ARMV7_PERFCTR_L1_ICACHE_ACCESS 0x14 |
| 69 | #define ARMV7_PERFCTR_L1_DCACHE_WB 0x15 |
| 70 | #define ARMV7_PERFCTR_L2_CACHE_ACCESS 0x16 |
| 71 | #define ARMV7_PERFCTR_L2_CACHE_REFILL 0x17 |
| 72 | #define ARMV7_PERFCTR_L2_CACHE_WB 0x18 |
| 73 | #define ARMV7_PERFCTR_BUS_ACCESS 0x19 |
| 74 | #define ARMV7_PERFCTR_MEM_ERROR 0x1A |
| 75 | #define ARMV7_PERFCTR_INSTR_SPEC 0x1B |
| 76 | #define ARMV7_PERFCTR_TTBR_WRITE 0x1C |
| 77 | #define ARMV7_PERFCTR_BUS_CYCLES 0x1D |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 78 | |
Drew Richardson | f4ab36c | 2015-10-28 08:19:56 -0700 | [diff] [blame] | 79 | #define ARMV7_PERFCTR_CPU_CYCLES 0xFF |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 80 | |
| 81 | /* ARMv7 Cortex-A8 specific event types */ |
Drew Richardson | f4ab36c | 2015-10-28 08:19:56 -0700 | [diff] [blame] | 82 | #define ARMV7_A8_PERFCTR_L2_CACHE_ACCESS 0x43 |
| 83 | #define ARMV7_A8_PERFCTR_L2_CACHE_REFILL 0x44 |
| 84 | #define ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS 0x50 |
| 85 | #define ARMV7_A8_PERFCTR_STALL_ISIDE 0x56 |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 86 | |
| 87 | /* ARMv7 Cortex-A9 specific event types */ |
Drew Richardson | f4ab36c | 2015-10-28 08:19:56 -0700 | [diff] [blame] | 88 | #define ARMV7_A9_PERFCTR_INSTR_CORE_RENAME 0x68 |
| 89 | #define ARMV7_A9_PERFCTR_STALL_ICACHE 0x60 |
| 90 | #define ARMV7_A9_PERFCTR_STALL_DISPATCH 0x66 |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 91 | |
Will Deacon | 0c205cb | 2011-06-03 17:40:15 +0100 | [diff] [blame] | 92 | /* ARMv7 Cortex-A5 specific event types */ |
Drew Richardson | f4ab36c | 2015-10-28 08:19:56 -0700 | [diff] [blame] | 93 | #define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL 0xc2 |
| 94 | #define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP 0xc3 |
Will Deacon | 0c205cb | 2011-06-03 17:40:15 +0100 | [diff] [blame] | 95 | |
Will Deacon | 14abd03 | 2011-01-19 14:24:38 +0000 | [diff] [blame] | 96 | /* ARMv7 Cortex-A15 specific event types */ |
Drew Richardson | f4ab36c | 2015-10-28 08:19:56 -0700 | [diff] [blame] | 97 | #define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ 0x40 |
| 98 | #define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41 |
| 99 | #define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ 0x42 |
| 100 | #define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE 0x43 |
Will Deacon | 14abd03 | 2011-01-19 14:24:38 +0000 | [diff] [blame] | 101 | |
Drew Richardson | f4ab36c | 2015-10-28 08:19:56 -0700 | [diff] [blame] | 102 | #define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ 0x4C |
| 103 | #define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE 0x4D |
Will Deacon | 14abd03 | 2011-01-19 14:24:38 +0000 | [diff] [blame] | 104 | |
Drew Richardson | f4ab36c | 2015-10-28 08:19:56 -0700 | [diff] [blame] | 105 | #define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ 0x50 |
| 106 | #define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51 |
| 107 | #define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ 0x52 |
| 108 | #define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE 0x53 |
Will Deacon | 14abd03 | 2011-01-19 14:24:38 +0000 | [diff] [blame] | 109 | |
Drew Richardson | f4ab36c | 2015-10-28 08:19:56 -0700 | [diff] [blame] | 110 | #define ARMV7_A15_PERFCTR_PC_WRITE_SPEC 0x76 |
Will Deacon | 14abd03 | 2011-01-19 14:24:38 +0000 | [diff] [blame] | 111 | |
Albin Tonnerre | 8e781f6 | 2014-01-29 14:28:57 +0000 | [diff] [blame] | 112 | /* ARMv7 Cortex-A12 specific event types */ |
Drew Richardson | f4ab36c | 2015-10-28 08:19:56 -0700 | [diff] [blame] | 113 | #define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ 0x40 |
| 114 | #define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41 |
Albin Tonnerre | 8e781f6 | 2014-01-29 14:28:57 +0000 | [diff] [blame] | 115 | |
Drew Richardson | f4ab36c | 2015-10-28 08:19:56 -0700 | [diff] [blame] | 116 | #define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ 0x50 |
| 117 | #define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51 |
Albin Tonnerre | 8e781f6 | 2014-01-29 14:28:57 +0000 | [diff] [blame] | 118 | |
Drew Richardson | f4ab36c | 2015-10-28 08:19:56 -0700 | [diff] [blame] | 119 | #define ARMV7_A12_PERFCTR_PC_WRITE_SPEC 0x76 |
Albin Tonnerre | 8e781f6 | 2014-01-29 14:28:57 +0000 | [diff] [blame] | 120 | |
Drew Richardson | f4ab36c | 2015-10-28 08:19:56 -0700 | [diff] [blame] | 121 | #define ARMV7_A12_PERFCTR_PF_TLB_REFILL 0xe7 |
Albin Tonnerre | 8e781f6 | 2014-01-29 14:28:57 +0000 | [diff] [blame] | 122 | |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 123 | /* ARMv7 Krait specific event types */ |
Drew Richardson | f4ab36c | 2015-10-28 08:19:56 -0700 | [diff] [blame] | 124 | #define KRAIT_PMRESR0_GROUP0 0xcc |
| 125 | #define KRAIT_PMRESR1_GROUP0 0xd0 |
| 126 | #define KRAIT_PMRESR2_GROUP0 0xd4 |
| 127 | #define KRAIT_VPMRESR0_GROUP0 0xd8 |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 128 | |
Drew Richardson | f4ab36c | 2015-10-28 08:19:56 -0700 | [diff] [blame] | 129 | #define KRAIT_PERFCTR_L1_ICACHE_ACCESS 0x10011 |
| 130 | #define KRAIT_PERFCTR_L1_ICACHE_MISS 0x10010 |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 131 | |
Drew Richardson | f4ab36c | 2015-10-28 08:19:56 -0700 | [diff] [blame] | 132 | #define KRAIT_PERFCTR_L1_ITLB_ACCESS 0x12222 |
| 133 | #define KRAIT_PERFCTR_L1_DTLB_ACCESS 0x12210 |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 134 | |
Stephen Boyd | 341e42c | 2015-02-27 16:11:35 -0800 | [diff] [blame] | 135 | /* ARMv7 Scorpion specific event types */ |
Drew Richardson | f4ab36c | 2015-10-28 08:19:56 -0700 | [diff] [blame] | 136 | #define SCORPION_LPM0_GROUP0 0x4c |
| 137 | #define SCORPION_LPM1_GROUP0 0x50 |
| 138 | #define SCORPION_LPM2_GROUP0 0x54 |
| 139 | #define SCORPION_L2LPM_GROUP0 0x58 |
| 140 | #define SCORPION_VLPM_GROUP0 0x5c |
Stephen Boyd | 341e42c | 2015-02-27 16:11:35 -0800 | [diff] [blame] | 141 | |
Drew Richardson | f4ab36c | 2015-10-28 08:19:56 -0700 | [diff] [blame] | 142 | #define SCORPION_ICACHE_ACCESS 0x10053 |
| 143 | #define SCORPION_ICACHE_MISS 0x10052 |
Stephen Boyd | 341e42c | 2015-02-27 16:11:35 -0800 | [diff] [blame] | 144 | |
Drew Richardson | f4ab36c | 2015-10-28 08:19:56 -0700 | [diff] [blame] | 145 | #define SCORPION_DTLB_ACCESS 0x12013 |
| 146 | #define SCORPION_DTLB_MISS 0x12012 |
Stephen Boyd | 341e42c | 2015-02-27 16:11:35 -0800 | [diff] [blame] | 147 | |
Drew Richardson | f4ab36c | 2015-10-28 08:19:56 -0700 | [diff] [blame] | 148 | #define SCORPION_ITLB_MISS 0x12021 |
Stephen Boyd | 341e42c | 2015-02-27 16:11:35 -0800 | [diff] [blame] | 149 | |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 150 | /* |
| 151 | * Cortex-A8 HW events mapping |
| 152 | * |
| 153 | * The hardware events that we support. We do support cache operations but |
| 154 | * we have harvard caches and no way to combine instruction and data |
| 155 | * accesses/misses in hardware. |
| 156 | */ |
| 157 | static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = { |
Mark Rutland | 6b7658e | 2014-05-30 17:27:21 +0100 | [diff] [blame] | 158 | PERF_MAP_ALL_UNSUPPORTED, |
Will Deacon | 0445e7a | 2011-09-29 18:23:39 +0100 | [diff] [blame] | 159 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, |
| 160 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, |
| 161 | [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, |
| 162 | [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, |
| 163 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, |
| 164 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
Will Deacon | 0445e7a | 2011-09-29 18:23:39 +0100 | [diff] [blame] | 165 | [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A8_PERFCTR_STALL_ISIDE, |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 166 | }; |
| 167 | |
| 168 | static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] |
| 169 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 170 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { |
Mark Rutland | 6b7658e | 2014-05-30 17:27:21 +0100 | [diff] [blame] | 171 | PERF_CACHE_MAP_ALL_UNSUPPORTED, |
| 172 | |
| 173 | /* |
| 174 | * The performance counters don't differentiate between read and write |
| 175 | * accesses/misses so this isn't strictly correct, but it's the best we |
| 176 | * can do. Writes and reads get combined. |
| 177 | */ |
| 178 | [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, |
| 179 | [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, |
| 180 | [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, |
| 181 | [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, |
| 182 | |
| 183 | [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS, |
| 184 | [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, |
| 185 | |
| 186 | [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS, |
| 187 | [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL, |
| 188 | [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS, |
| 189 | [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL, |
| 190 | |
| 191 | [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, |
| 192 | [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, |
| 193 | |
| 194 | [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, |
| 195 | [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, |
| 196 | |
| 197 | [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, |
| 198 | [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
| 199 | [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, |
| 200 | [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 201 | }; |
| 202 | |
| 203 | /* |
| 204 | * Cortex-A9 HW events mapping |
| 205 | */ |
| 206 | static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = { |
Mark Rutland | 6b7658e | 2014-05-30 17:27:21 +0100 | [diff] [blame] | 207 | PERF_MAP_ALL_UNSUPPORTED, |
Will Deacon | 0445e7a | 2011-09-29 18:23:39 +0100 | [diff] [blame] | 208 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, |
| 209 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_A9_PERFCTR_INSTR_CORE_RENAME, |
| 210 | [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, |
| 211 | [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, |
| 212 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, |
| 213 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
Will Deacon | 0445e7a | 2011-09-29 18:23:39 +0100 | [diff] [blame] | 214 | [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A9_PERFCTR_STALL_ICACHE, |
| 215 | [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV7_A9_PERFCTR_STALL_DISPATCH, |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 216 | }; |
| 217 | |
| 218 | static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] |
| 219 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 220 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { |
Mark Rutland | 6b7658e | 2014-05-30 17:27:21 +0100 | [diff] [blame] | 221 | PERF_CACHE_MAP_ALL_UNSUPPORTED, |
| 222 | |
| 223 | /* |
| 224 | * The performance counters don't differentiate between read and write |
| 225 | * accesses/misses so this isn't strictly correct, but it's the best we |
| 226 | * can do. Writes and reads get combined. |
| 227 | */ |
| 228 | [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, |
| 229 | [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, |
| 230 | [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, |
| 231 | [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, |
| 232 | |
| 233 | [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, |
| 234 | |
| 235 | [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, |
| 236 | [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, |
| 237 | |
| 238 | [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, |
| 239 | [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, |
| 240 | |
| 241 | [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, |
| 242 | [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
| 243 | [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, |
| 244 | [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 245 | }; |
| 246 | |
| 247 | /* |
Will Deacon | 0c205cb | 2011-06-03 17:40:15 +0100 | [diff] [blame] | 248 | * Cortex-A5 HW events mapping |
| 249 | */ |
| 250 | static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = { |
Mark Rutland | 6b7658e | 2014-05-30 17:27:21 +0100 | [diff] [blame] | 251 | PERF_MAP_ALL_UNSUPPORTED, |
Will Deacon | 0445e7a | 2011-09-29 18:23:39 +0100 | [diff] [blame] | 252 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, |
| 253 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, |
| 254 | [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, |
| 255 | [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, |
| 256 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, |
| 257 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
Will Deacon | 0c205cb | 2011-06-03 17:40:15 +0100 | [diff] [blame] | 258 | }; |
| 259 | |
| 260 | static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] |
| 261 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 262 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { |
Mark Rutland | 6b7658e | 2014-05-30 17:27:21 +0100 | [diff] [blame] | 263 | PERF_CACHE_MAP_ALL_UNSUPPORTED, |
| 264 | |
| 265 | [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, |
| 266 | [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, |
| 267 | [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, |
| 268 | [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, |
| 269 | [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL, |
| 270 | [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP, |
| 271 | |
| 272 | [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, |
| 273 | [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, |
| 274 | /* |
| 275 | * The prefetch counters don't differentiate between the I side and the |
| 276 | * D side. |
| 277 | */ |
| 278 | [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL, |
| 279 | [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP, |
| 280 | |
| 281 | [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, |
| 282 | [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, |
| 283 | |
| 284 | [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, |
| 285 | [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, |
| 286 | |
| 287 | [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, |
| 288 | [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
| 289 | [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, |
| 290 | [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
Will Deacon | 0c205cb | 2011-06-03 17:40:15 +0100 | [diff] [blame] | 291 | }; |
| 292 | |
| 293 | /* |
Will Deacon | 14abd03 | 2011-01-19 14:24:38 +0000 | [diff] [blame] | 294 | * Cortex-A15 HW events mapping |
| 295 | */ |
| 296 | static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = { |
Mark Rutland | 6b7658e | 2014-05-30 17:27:21 +0100 | [diff] [blame] | 297 | PERF_MAP_ALL_UNSUPPORTED, |
Will Deacon | 0445e7a | 2011-09-29 18:23:39 +0100 | [diff] [blame] | 298 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, |
| 299 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, |
| 300 | [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, |
| 301 | [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, |
| 302 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A15_PERFCTR_PC_WRITE_SPEC, |
| 303 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
| 304 | [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES, |
Will Deacon | 14abd03 | 2011-01-19 14:24:38 +0000 | [diff] [blame] | 305 | }; |
| 306 | |
| 307 | static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] |
| 308 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 309 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { |
Mark Rutland | 6b7658e | 2014-05-30 17:27:21 +0100 | [diff] [blame] | 310 | PERF_CACHE_MAP_ALL_UNSUPPORTED, |
| 311 | |
| 312 | [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ, |
| 313 | [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ, |
| 314 | [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE, |
| 315 | [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE, |
| 316 | |
| 317 | /* |
| 318 | * Not all performance counters differentiate between read and write |
| 319 | * accesses/misses so we're not always strictly correct, but it's the |
| 320 | * best we can do. Writes and reads get combined in these cases. |
| 321 | */ |
| 322 | [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, |
| 323 | [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, |
| 324 | |
| 325 | [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ, |
| 326 | [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ, |
| 327 | [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE, |
| 328 | [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE, |
| 329 | |
| 330 | [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ, |
| 331 | [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE, |
| 332 | |
| 333 | [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, |
| 334 | [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, |
| 335 | |
| 336 | [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, |
| 337 | [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
| 338 | [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, |
| 339 | [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
Will Deacon | 14abd03 | 2011-01-19 14:24:38 +0000 | [diff] [blame] | 340 | }; |
| 341 | |
| 342 | /* |
Will Deacon | d33c88c | 2012-02-03 14:46:01 +0100 | [diff] [blame] | 343 | * Cortex-A7 HW events mapping |
| 344 | */ |
| 345 | static const unsigned armv7_a7_perf_map[PERF_COUNT_HW_MAX] = { |
Mark Rutland | 6b7658e | 2014-05-30 17:27:21 +0100 | [diff] [blame] | 346 | PERF_MAP_ALL_UNSUPPORTED, |
Will Deacon | d33c88c | 2012-02-03 14:46:01 +0100 | [diff] [blame] | 347 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, |
| 348 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, |
| 349 | [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, |
| 350 | [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, |
| 351 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, |
| 352 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
| 353 | [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES, |
Will Deacon | d33c88c | 2012-02-03 14:46:01 +0100 | [diff] [blame] | 354 | }; |
| 355 | |
| 356 | static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] |
| 357 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 358 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { |
Mark Rutland | 6b7658e | 2014-05-30 17:27:21 +0100 | [diff] [blame] | 359 | PERF_CACHE_MAP_ALL_UNSUPPORTED, |
| 360 | |
| 361 | /* |
| 362 | * The performance counters don't differentiate between read and write |
| 363 | * accesses/misses so this isn't strictly correct, but it's the best we |
| 364 | * can do. Writes and reads get combined. |
| 365 | */ |
| 366 | [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, |
| 367 | [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, |
| 368 | [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, |
| 369 | [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, |
| 370 | |
| 371 | [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, |
| 372 | [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, |
| 373 | |
| 374 | [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS, |
| 375 | [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, |
| 376 | [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS, |
| 377 | [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, |
| 378 | |
| 379 | [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, |
| 380 | [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, |
| 381 | |
| 382 | [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, |
| 383 | [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, |
| 384 | |
| 385 | [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, |
| 386 | [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
| 387 | [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, |
| 388 | [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
Will Deacon | d33c88c | 2012-02-03 14:46:01 +0100 | [diff] [blame] | 389 | }; |
| 390 | |
| 391 | /* |
Albin Tonnerre | 8e781f6 | 2014-01-29 14:28:57 +0000 | [diff] [blame] | 392 | * Cortex-A12 HW events mapping |
| 393 | */ |
| 394 | static const unsigned armv7_a12_perf_map[PERF_COUNT_HW_MAX] = { |
Mark Rutland | 6b7658e | 2014-05-30 17:27:21 +0100 | [diff] [blame] | 395 | PERF_MAP_ALL_UNSUPPORTED, |
Albin Tonnerre | 8e781f6 | 2014-01-29 14:28:57 +0000 | [diff] [blame] | 396 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, |
| 397 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, |
| 398 | [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, |
| 399 | [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, |
| 400 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A12_PERFCTR_PC_WRITE_SPEC, |
| 401 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
| 402 | [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES, |
Albin Tonnerre | 8e781f6 | 2014-01-29 14:28:57 +0000 | [diff] [blame] | 403 | }; |
| 404 | |
| 405 | static const unsigned armv7_a12_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] |
| 406 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 407 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { |
Mark Rutland | 6b7658e | 2014-05-30 17:27:21 +0100 | [diff] [blame] | 408 | PERF_CACHE_MAP_ALL_UNSUPPORTED, |
| 409 | |
| 410 | [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ, |
| 411 | [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, |
| 412 | [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE, |
| 413 | [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, |
| 414 | |
| 415 | /* |
| 416 | * Not all performance counters differentiate between read and write |
| 417 | * accesses/misses so we're not always strictly correct, but it's the |
| 418 | * best we can do. Writes and reads get combined in these cases. |
| 419 | */ |
| 420 | [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, |
| 421 | [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, |
| 422 | |
| 423 | [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ, |
| 424 | [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, |
| 425 | [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE, |
| 426 | [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, |
| 427 | |
| 428 | [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, |
| 429 | [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, |
| 430 | [C(DTLB)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A12_PERFCTR_PF_TLB_REFILL, |
| 431 | |
| 432 | [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, |
| 433 | [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, |
| 434 | |
| 435 | [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, |
| 436 | [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
| 437 | [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, |
| 438 | [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
Albin Tonnerre | 8e781f6 | 2014-01-29 14:28:57 +0000 | [diff] [blame] | 439 | }; |
| 440 | |
| 441 | /* |
Stephen Boyd | 2a3391c | 2014-02-07 21:01:21 +0000 | [diff] [blame] | 442 | * Krait HW events mapping |
| 443 | */ |
| 444 | static const unsigned krait_perf_map[PERF_COUNT_HW_MAX] = { |
Mark Rutland | 6b7658e | 2014-05-30 17:27:21 +0100 | [diff] [blame] | 445 | PERF_MAP_ALL_UNSUPPORTED, |
Stephen Boyd | 2a3391c | 2014-02-07 21:01:21 +0000 | [diff] [blame] | 446 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, |
| 447 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, |
Stephen Boyd | 2a3391c | 2014-02-07 21:01:21 +0000 | [diff] [blame] | 448 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, |
| 449 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
| 450 | [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, |
| 451 | }; |
| 452 | |
| 453 | static const unsigned krait_perf_map_no_branch[PERF_COUNT_HW_MAX] = { |
Mark Rutland | 6b7658e | 2014-05-30 17:27:21 +0100 | [diff] [blame] | 454 | PERF_MAP_ALL_UNSUPPORTED, |
Stephen Boyd | 2a3391c | 2014-02-07 21:01:21 +0000 | [diff] [blame] | 455 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, |
| 456 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, |
Stephen Boyd | 2a3391c | 2014-02-07 21:01:21 +0000 | [diff] [blame] | 457 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
| 458 | [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, |
| 459 | }; |
| 460 | |
| 461 | static const unsigned krait_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] |
| 462 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 463 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { |
Mark Rutland | 6b7658e | 2014-05-30 17:27:21 +0100 | [diff] [blame] | 464 | PERF_CACHE_MAP_ALL_UNSUPPORTED, |
| 465 | |
| 466 | /* |
| 467 | * The performance counters don't differentiate between read and write |
| 468 | * accesses/misses so this isn't strictly correct, but it's the best we |
| 469 | * can do. Writes and reads get combined. |
| 470 | */ |
| 471 | [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, |
| 472 | [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, |
| 473 | [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, |
| 474 | [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, |
| 475 | |
| 476 | [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ICACHE_ACCESS, |
| 477 | [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = KRAIT_PERFCTR_L1_ICACHE_MISS, |
| 478 | |
| 479 | [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_DTLB_ACCESS, |
| 480 | [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_DTLB_ACCESS, |
| 481 | |
| 482 | [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ITLB_ACCESS, |
| 483 | [C(ITLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ITLB_ACCESS, |
| 484 | |
| 485 | [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, |
| 486 | [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
| 487 | [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, |
| 488 | [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
Stephen Boyd | 2a3391c | 2014-02-07 21:01:21 +0000 | [diff] [blame] | 489 | }; |
| 490 | |
| 491 | /* |
Stephen Boyd | 341e42c | 2015-02-27 16:11:35 -0800 | [diff] [blame] | 492 | * Scorpion HW events mapping |
| 493 | */ |
| 494 | static const unsigned scorpion_perf_map[PERF_COUNT_HW_MAX] = { |
| 495 | PERF_MAP_ALL_UNSUPPORTED, |
| 496 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, |
| 497 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, |
| 498 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, |
| 499 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
| 500 | [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, |
| 501 | }; |
| 502 | |
| 503 | static const unsigned scorpion_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] |
| 504 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 505 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { |
| 506 | PERF_CACHE_MAP_ALL_UNSUPPORTED, |
| 507 | /* |
| 508 | * The performance counters don't differentiate between read and write |
| 509 | * accesses/misses so this isn't strictly correct, but it's the best we |
| 510 | * can do. Writes and reads get combined. |
| 511 | */ |
| 512 | [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, |
| 513 | [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, |
| 514 | [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, |
| 515 | [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, |
| 516 | [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = SCORPION_ICACHE_ACCESS, |
| 517 | [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ICACHE_MISS, |
| 518 | /* |
| 519 | * Only ITLB misses and DTLB refills are supported. If users want the |
| 520 | * DTLB refills misses a raw counter must be used. |
| 521 | */ |
| 522 | [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = SCORPION_DTLB_ACCESS, |
| 523 | [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_DTLB_MISS, |
| 524 | [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = SCORPION_DTLB_ACCESS, |
| 525 | [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_DTLB_MISS, |
| 526 | [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ITLB_MISS, |
| 527 | [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_ITLB_MISS, |
| 528 | [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, |
| 529 | [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
| 530 | [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, |
| 531 | [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
| 532 | }; |
| 533 | |
Will Deacon | abff083 | 2015-12-22 14:42:57 +0000 | [diff] [blame] | 534 | PMU_FORMAT_ATTR(event, "config:0-7"); |
| 535 | |
| 536 | static struct attribute *armv7_pmu_format_attrs[] = { |
| 537 | &format_attr_event.attr, |
| 538 | NULL, |
| 539 | }; |
| 540 | |
| 541 | static struct attribute_group armv7_pmu_format_attr_group = { |
| 542 | .name = "format", |
| 543 | .attrs = armv7_pmu_format_attrs, |
| 544 | }; |
| 545 | |
Drew Richardson | 3fbac6c | 2015-10-28 08:20:41 -0700 | [diff] [blame] | 546 | #define ARMV7_EVENT_ATTR_RESOLVE(m) #m |
| 547 | #define ARMV7_EVENT_ATTR(name, config) \ |
| 548 | PMU_EVENT_ATTR_STRING(name, armv7_event_attr_##name, \ |
| 549 | "event=" ARMV7_EVENT_ATTR_RESOLVE(config)) |
| 550 | |
| 551 | ARMV7_EVENT_ATTR(sw_incr, ARMV7_PERFCTR_PMNC_SW_INCR); |
| 552 | ARMV7_EVENT_ATTR(l1i_cache_refill, ARMV7_PERFCTR_L1_ICACHE_REFILL); |
| 553 | ARMV7_EVENT_ATTR(l1i_tlb_refill, ARMV7_PERFCTR_ITLB_REFILL); |
| 554 | ARMV7_EVENT_ATTR(l1d_cache_refill, ARMV7_PERFCTR_L1_DCACHE_REFILL); |
| 555 | ARMV7_EVENT_ATTR(l1d_cache, ARMV7_PERFCTR_L1_DCACHE_ACCESS); |
| 556 | ARMV7_EVENT_ATTR(l1d_tlb_refill, ARMV7_PERFCTR_DTLB_REFILL); |
| 557 | ARMV7_EVENT_ATTR(ld_retired, ARMV7_PERFCTR_MEM_READ); |
| 558 | ARMV7_EVENT_ATTR(st_retired, ARMV7_PERFCTR_MEM_WRITE); |
| 559 | ARMV7_EVENT_ATTR(inst_retired, ARMV7_PERFCTR_INSTR_EXECUTED); |
| 560 | ARMV7_EVENT_ATTR(exc_taken, ARMV7_PERFCTR_EXC_TAKEN); |
| 561 | ARMV7_EVENT_ATTR(exc_return, ARMV7_PERFCTR_EXC_EXECUTED); |
| 562 | ARMV7_EVENT_ATTR(cid_write_retired, ARMV7_PERFCTR_CID_WRITE); |
| 563 | ARMV7_EVENT_ATTR(pc_write_retired, ARMV7_PERFCTR_PC_WRITE); |
| 564 | ARMV7_EVENT_ATTR(br_immed_retired, ARMV7_PERFCTR_PC_IMM_BRANCH); |
| 565 | ARMV7_EVENT_ATTR(br_return_retired, ARMV7_PERFCTR_PC_PROC_RETURN); |
| 566 | ARMV7_EVENT_ATTR(unaligned_ldst_retired, ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS); |
| 567 | ARMV7_EVENT_ATTR(br_mis_pred, ARMV7_PERFCTR_PC_BRANCH_MIS_PRED); |
| 568 | ARMV7_EVENT_ATTR(cpu_cycles, ARMV7_PERFCTR_CLOCK_CYCLES); |
| 569 | ARMV7_EVENT_ATTR(br_pred, ARMV7_PERFCTR_PC_BRANCH_PRED); |
| 570 | |
| 571 | static struct attribute *armv7_pmuv1_event_attrs[] = { |
| 572 | &armv7_event_attr_sw_incr.attr.attr, |
| 573 | &armv7_event_attr_l1i_cache_refill.attr.attr, |
| 574 | &armv7_event_attr_l1i_tlb_refill.attr.attr, |
| 575 | &armv7_event_attr_l1d_cache_refill.attr.attr, |
| 576 | &armv7_event_attr_l1d_cache.attr.attr, |
| 577 | &armv7_event_attr_l1d_tlb_refill.attr.attr, |
| 578 | &armv7_event_attr_ld_retired.attr.attr, |
| 579 | &armv7_event_attr_st_retired.attr.attr, |
| 580 | &armv7_event_attr_inst_retired.attr.attr, |
| 581 | &armv7_event_attr_exc_taken.attr.attr, |
| 582 | &armv7_event_attr_exc_return.attr.attr, |
| 583 | &armv7_event_attr_cid_write_retired.attr.attr, |
| 584 | &armv7_event_attr_pc_write_retired.attr.attr, |
| 585 | &armv7_event_attr_br_immed_retired.attr.attr, |
| 586 | &armv7_event_attr_br_return_retired.attr.attr, |
| 587 | &armv7_event_attr_unaligned_ldst_retired.attr.attr, |
| 588 | &armv7_event_attr_br_mis_pred.attr.attr, |
| 589 | &armv7_event_attr_cpu_cycles.attr.attr, |
| 590 | &armv7_event_attr_br_pred.attr.attr, |
Will Deacon | abff083 | 2015-12-22 14:42:57 +0000 | [diff] [blame] | 591 | NULL, |
Drew Richardson | 3fbac6c | 2015-10-28 08:20:41 -0700 | [diff] [blame] | 592 | }; |
| 593 | |
| 594 | static struct attribute_group armv7_pmuv1_events_attr_group = { |
| 595 | .name = "events", |
| 596 | .attrs = armv7_pmuv1_event_attrs, |
| 597 | }; |
| 598 | |
Drew Richardson | 3fbac6c | 2015-10-28 08:20:41 -0700 | [diff] [blame] | 599 | ARMV7_EVENT_ATTR(mem_access, ARMV7_PERFCTR_MEM_ACCESS); |
| 600 | ARMV7_EVENT_ATTR(l1i_cache, ARMV7_PERFCTR_L1_ICACHE_ACCESS); |
| 601 | ARMV7_EVENT_ATTR(l1d_cache_wb, ARMV7_PERFCTR_L1_DCACHE_WB); |
| 602 | ARMV7_EVENT_ATTR(l2d_cache, ARMV7_PERFCTR_L2_CACHE_ACCESS); |
| 603 | ARMV7_EVENT_ATTR(l2d_cache_refill, ARMV7_PERFCTR_L2_CACHE_REFILL); |
| 604 | ARMV7_EVENT_ATTR(l2d_cache_wb, ARMV7_PERFCTR_L2_CACHE_WB); |
| 605 | ARMV7_EVENT_ATTR(bus_access, ARMV7_PERFCTR_BUS_ACCESS); |
| 606 | ARMV7_EVENT_ATTR(memory_error, ARMV7_PERFCTR_MEM_ERROR); |
| 607 | ARMV7_EVENT_ATTR(inst_spec, ARMV7_PERFCTR_INSTR_SPEC); |
| 608 | ARMV7_EVENT_ATTR(ttbr_write_retired, ARMV7_PERFCTR_TTBR_WRITE); |
| 609 | ARMV7_EVENT_ATTR(bus_cycles, ARMV7_PERFCTR_BUS_CYCLES); |
| 610 | |
| 611 | static struct attribute *armv7_pmuv2_event_attrs[] = { |
| 612 | &armv7_event_attr_sw_incr.attr.attr, |
| 613 | &armv7_event_attr_l1i_cache_refill.attr.attr, |
| 614 | &armv7_event_attr_l1i_tlb_refill.attr.attr, |
| 615 | &armv7_event_attr_l1d_cache_refill.attr.attr, |
| 616 | &armv7_event_attr_l1d_cache.attr.attr, |
| 617 | &armv7_event_attr_l1d_tlb_refill.attr.attr, |
| 618 | &armv7_event_attr_ld_retired.attr.attr, |
| 619 | &armv7_event_attr_st_retired.attr.attr, |
| 620 | &armv7_event_attr_inst_retired.attr.attr, |
| 621 | &armv7_event_attr_exc_taken.attr.attr, |
| 622 | &armv7_event_attr_exc_return.attr.attr, |
| 623 | &armv7_event_attr_cid_write_retired.attr.attr, |
| 624 | &armv7_event_attr_pc_write_retired.attr.attr, |
| 625 | &armv7_event_attr_br_immed_retired.attr.attr, |
| 626 | &armv7_event_attr_br_return_retired.attr.attr, |
| 627 | &armv7_event_attr_unaligned_ldst_retired.attr.attr, |
| 628 | &armv7_event_attr_br_mis_pred.attr.attr, |
| 629 | &armv7_event_attr_cpu_cycles.attr.attr, |
| 630 | &armv7_event_attr_br_pred.attr.attr, |
| 631 | &armv7_event_attr_mem_access.attr.attr, |
| 632 | &armv7_event_attr_l1i_cache.attr.attr, |
| 633 | &armv7_event_attr_l1d_cache_wb.attr.attr, |
| 634 | &armv7_event_attr_l2d_cache.attr.attr, |
| 635 | &armv7_event_attr_l2d_cache_refill.attr.attr, |
| 636 | &armv7_event_attr_l2d_cache_wb.attr.attr, |
| 637 | &armv7_event_attr_bus_access.attr.attr, |
| 638 | &armv7_event_attr_memory_error.attr.attr, |
| 639 | &armv7_event_attr_inst_spec.attr.attr, |
| 640 | &armv7_event_attr_ttbr_write_retired.attr.attr, |
| 641 | &armv7_event_attr_bus_cycles.attr.attr, |
Will Deacon | abff083 | 2015-12-22 14:42:57 +0000 | [diff] [blame] | 642 | NULL, |
Drew Richardson | 3fbac6c | 2015-10-28 08:20:41 -0700 | [diff] [blame] | 643 | }; |
| 644 | |
| 645 | static struct attribute_group armv7_pmuv2_events_attr_group = { |
| 646 | .name = "events", |
| 647 | .attrs = armv7_pmuv2_event_attrs, |
| 648 | }; |
| 649 | |
Stephen Boyd | 341e42c | 2015-02-27 16:11:35 -0800 | [diff] [blame] | 650 | /* |
Will Deacon | c691bb6 | 2011-07-19 22:25:55 +0100 | [diff] [blame] | 651 | * Perf Events' indices |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 652 | */ |
Will Deacon | c691bb6 | 2011-07-19 22:25:55 +0100 | [diff] [blame] | 653 | #define ARMV7_IDX_CYCLE_COUNTER 0 |
| 654 | #define ARMV7_IDX_COUNTER0 1 |
Sudeep KarkadaNagesha | 7279adb | 2012-07-20 15:18:07 +0100 | [diff] [blame] | 655 | #define ARMV7_IDX_COUNTER_LAST(cpu_pmu) \ |
| 656 | (ARMV7_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 657 | |
Will Deacon | c691bb6 | 2011-07-19 22:25:55 +0100 | [diff] [blame] | 658 | #define ARMV7_MAX_COUNTERS 32 |
| 659 | #define ARMV7_COUNTER_MASK (ARMV7_MAX_COUNTERS - 1) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 660 | |
| 661 | /* |
| 662 | * ARMv7 low level PMNC access |
| 663 | */ |
| 664 | |
| 665 | /* |
Will Deacon | c691bb6 | 2011-07-19 22:25:55 +0100 | [diff] [blame] | 666 | * Perf Event to low level counters mapping |
| 667 | */ |
| 668 | #define ARMV7_IDX_TO_COUNTER(x) \ |
| 669 | (((x) - ARMV7_IDX_COUNTER0) & ARMV7_COUNTER_MASK) |
| 670 | |
| 671 | /* |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 672 | * Per-CPU PMNC: config reg |
| 673 | */ |
| 674 | #define ARMV7_PMNC_E (1 << 0) /* Enable all counters */ |
| 675 | #define ARMV7_PMNC_P (1 << 1) /* Reset all counters */ |
| 676 | #define ARMV7_PMNC_C (1 << 2) /* Cycle counter reset */ |
| 677 | #define ARMV7_PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */ |
| 678 | #define ARMV7_PMNC_X (1 << 4) /* Export to ETM */ |
| 679 | #define ARMV7_PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ |
| 680 | #define ARMV7_PMNC_N_SHIFT 11 /* Number of counters supported */ |
| 681 | #define ARMV7_PMNC_N_MASK 0x1f |
| 682 | #define ARMV7_PMNC_MASK 0x3f /* Mask for writable bits */ |
| 683 | |
| 684 | /* |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 685 | * FLAG: counters overflow flag status reg |
| 686 | */ |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 687 | #define ARMV7_FLAG_MASK 0xffffffff /* Mask for writable bits */ |
| 688 | #define ARMV7_OVERFLOWED_MASK ARMV7_FLAG_MASK |
| 689 | |
Will Deacon | a505add | 2011-07-19 13:53:36 +0100 | [diff] [blame] | 690 | /* |
| 691 | * PMXEVTYPER: Event selection reg |
| 692 | */ |
Will Deacon | f2fe09b | 2013-02-28 17:49:11 +0100 | [diff] [blame] | 693 | #define ARMV7_EVTYPE_MASK 0xc80000ff /* Mask for writable bits */ |
Will Deacon | a505add | 2011-07-19 13:53:36 +0100 | [diff] [blame] | 694 | #define ARMV7_EVTYPE_EVENT 0xff /* Mask for EVENT bits */ |
| 695 | |
| 696 | /* |
| 697 | * Event filters for PMUv2 |
| 698 | */ |
| 699 | #define ARMV7_EXCLUDE_PL1 (1 << 31) |
| 700 | #define ARMV7_EXCLUDE_USER (1 << 30) |
| 701 | #define ARMV7_INCLUDE_HYP (1 << 27) |
| 702 | |
Martin Fuzzey | 8d1a0ae | 2016-01-13 23:36:26 -0500 | [diff] [blame] | 703 | /* |
| 704 | * Secure debug enable reg |
| 705 | */ |
| 706 | #define ARMV7_SDER_SUNIDEN BIT(1) /* Permit non-invasive debug */ |
| 707 | |
Will Deacon | 6330aae | 2011-07-19 14:55:57 +0100 | [diff] [blame] | 708 | static inline u32 armv7_pmnc_read(void) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 709 | { |
| 710 | u32 val; |
| 711 | asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val)); |
| 712 | return val; |
| 713 | } |
| 714 | |
Will Deacon | 6330aae | 2011-07-19 14:55:57 +0100 | [diff] [blame] | 715 | static inline void armv7_pmnc_write(u32 val) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 716 | { |
| 717 | val &= ARMV7_PMNC_MASK; |
Will Deacon | d25d3b4 | 2011-03-25 13:12:23 +0100 | [diff] [blame] | 718 | isb(); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 719 | asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val)); |
| 720 | } |
| 721 | |
Will Deacon | 6330aae | 2011-07-19 14:55:57 +0100 | [diff] [blame] | 722 | static inline int armv7_pmnc_has_overflowed(u32 pmnc) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 723 | { |
| 724 | return pmnc & ARMV7_OVERFLOWED_MASK; |
| 725 | } |
| 726 | |
Sudeep KarkadaNagesha | 7279adb | 2012-07-20 15:18:07 +0100 | [diff] [blame] | 727 | static inline int armv7_pmnc_counter_valid(struct arm_pmu *cpu_pmu, int idx) |
Will Deacon | c691bb6 | 2011-07-19 22:25:55 +0100 | [diff] [blame] | 728 | { |
Sudeep KarkadaNagesha | 7279adb | 2012-07-20 15:18:07 +0100 | [diff] [blame] | 729 | return idx >= ARMV7_IDX_CYCLE_COUNTER && |
| 730 | idx <= ARMV7_IDX_COUNTER_LAST(cpu_pmu); |
Will Deacon | c691bb6 | 2011-07-19 22:25:55 +0100 | [diff] [blame] | 731 | } |
| 732 | |
| 733 | static inline int armv7_pmnc_counter_has_overflowed(u32 pmnc, int idx) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 734 | { |
Sudeep KarkadaNagesha | 7279adb | 2012-07-20 15:18:07 +0100 | [diff] [blame] | 735 | return pmnc & BIT(ARMV7_IDX_TO_COUNTER(idx)); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 736 | } |
| 737 | |
chai wen | cb6eb10 | 2014-10-22 13:16:49 +0100 | [diff] [blame] | 738 | static inline void armv7_pmnc_select_counter(int idx) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 739 | { |
Sudeep KarkadaNagesha | 7279adb | 2012-07-20 15:18:07 +0100 | [diff] [blame] | 740 | u32 counter = ARMV7_IDX_TO_COUNTER(idx); |
Will Deacon | c691bb6 | 2011-07-19 22:25:55 +0100 | [diff] [blame] | 741 | asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (counter)); |
Will Deacon | d25d3b4 | 2011-03-25 13:12:23 +0100 | [diff] [blame] | 742 | isb(); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 743 | } |
| 744 | |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 745 | static inline u32 armv7pmu_read_counter(struct perf_event *event) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 746 | { |
Sudeep KarkadaNagesha | 7279adb | 2012-07-20 15:18:07 +0100 | [diff] [blame] | 747 | struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 748 | struct hw_perf_event *hwc = &event->hw; |
| 749 | int idx = hwc->idx; |
Will Deacon | 6330aae | 2011-07-19 14:55:57 +0100 | [diff] [blame] | 750 | u32 value = 0; |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 751 | |
chai wen | cb6eb10 | 2014-10-22 13:16:49 +0100 | [diff] [blame] | 752 | if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) { |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 753 | pr_err("CPU%u reading wrong counter %d\n", |
| 754 | smp_processor_id(), idx); |
chai wen | cb6eb10 | 2014-10-22 13:16:49 +0100 | [diff] [blame] | 755 | } else if (idx == ARMV7_IDX_CYCLE_COUNTER) { |
Will Deacon | c691bb6 | 2011-07-19 22:25:55 +0100 | [diff] [blame] | 756 | asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value)); |
chai wen | cb6eb10 | 2014-10-22 13:16:49 +0100 | [diff] [blame] | 757 | } else { |
| 758 | armv7_pmnc_select_counter(idx); |
Will Deacon | c691bb6 | 2011-07-19 22:25:55 +0100 | [diff] [blame] | 759 | asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (value)); |
chai wen | cb6eb10 | 2014-10-22 13:16:49 +0100 | [diff] [blame] | 760 | } |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 761 | |
| 762 | return value; |
| 763 | } |
| 764 | |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 765 | static inline void armv7pmu_write_counter(struct perf_event *event, u32 value) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 766 | { |
Sudeep KarkadaNagesha | 7279adb | 2012-07-20 15:18:07 +0100 | [diff] [blame] | 767 | struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 768 | struct hw_perf_event *hwc = &event->hw; |
| 769 | int idx = hwc->idx; |
| 770 | |
chai wen | cb6eb10 | 2014-10-22 13:16:49 +0100 | [diff] [blame] | 771 | if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) { |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 772 | pr_err("CPU%u writing wrong counter %d\n", |
| 773 | smp_processor_id(), idx); |
chai wen | cb6eb10 | 2014-10-22 13:16:49 +0100 | [diff] [blame] | 774 | } else if (idx == ARMV7_IDX_CYCLE_COUNTER) { |
Will Deacon | c691bb6 | 2011-07-19 22:25:55 +0100 | [diff] [blame] | 775 | asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value)); |
chai wen | cb6eb10 | 2014-10-22 13:16:49 +0100 | [diff] [blame] | 776 | } else { |
| 777 | armv7_pmnc_select_counter(idx); |
Will Deacon | c691bb6 | 2011-07-19 22:25:55 +0100 | [diff] [blame] | 778 | asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" (value)); |
chai wen | cb6eb10 | 2014-10-22 13:16:49 +0100 | [diff] [blame] | 779 | } |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 780 | } |
| 781 | |
Will Deacon | 25e29c7 | 2011-07-19 22:17:48 +0100 | [diff] [blame] | 782 | static inline void armv7_pmnc_write_evtsel(int idx, u32 val) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 783 | { |
chai wen | cb6eb10 | 2014-10-22 13:16:49 +0100 | [diff] [blame] | 784 | armv7_pmnc_select_counter(idx); |
| 785 | val &= ARMV7_EVTYPE_MASK; |
| 786 | asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val)); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 787 | } |
| 788 | |
chai wen | cb6eb10 | 2014-10-22 13:16:49 +0100 | [diff] [blame] | 789 | static inline void armv7_pmnc_enable_counter(int idx) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 790 | { |
Sudeep KarkadaNagesha | 7279adb | 2012-07-20 15:18:07 +0100 | [diff] [blame] | 791 | u32 counter = ARMV7_IDX_TO_COUNTER(idx); |
Will Deacon | c691bb6 | 2011-07-19 22:25:55 +0100 | [diff] [blame] | 792 | asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (BIT(counter))); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 793 | } |
| 794 | |
chai wen | cb6eb10 | 2014-10-22 13:16:49 +0100 | [diff] [blame] | 795 | static inline void armv7_pmnc_disable_counter(int idx) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 796 | { |
Sudeep KarkadaNagesha | 7279adb | 2012-07-20 15:18:07 +0100 | [diff] [blame] | 797 | u32 counter = ARMV7_IDX_TO_COUNTER(idx); |
Will Deacon | c691bb6 | 2011-07-19 22:25:55 +0100 | [diff] [blame] | 798 | asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (BIT(counter))); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 799 | } |
| 800 | |
chai wen | cb6eb10 | 2014-10-22 13:16:49 +0100 | [diff] [blame] | 801 | static inline void armv7_pmnc_enable_intens(int idx) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 802 | { |
Sudeep KarkadaNagesha | 7279adb | 2012-07-20 15:18:07 +0100 | [diff] [blame] | 803 | u32 counter = ARMV7_IDX_TO_COUNTER(idx); |
Will Deacon | c691bb6 | 2011-07-19 22:25:55 +0100 | [diff] [blame] | 804 | asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (BIT(counter))); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 805 | } |
| 806 | |
chai wen | cb6eb10 | 2014-10-22 13:16:49 +0100 | [diff] [blame] | 807 | static inline void armv7_pmnc_disable_intens(int idx) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 808 | { |
Sudeep KarkadaNagesha | 7279adb | 2012-07-20 15:18:07 +0100 | [diff] [blame] | 809 | u32 counter = ARMV7_IDX_TO_COUNTER(idx); |
Will Deacon | c691bb6 | 2011-07-19 22:25:55 +0100 | [diff] [blame] | 810 | asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(counter))); |
Will Deacon | 99c1745 | 2012-03-06 17:34:22 +0100 | [diff] [blame] | 811 | isb(); |
| 812 | /* Clear the overflow flag in case an interrupt is pending. */ |
| 813 | asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (BIT(counter))); |
| 814 | isb(); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 815 | } |
| 816 | |
| 817 | static inline u32 armv7_pmnc_getreset_flags(void) |
| 818 | { |
| 819 | u32 val; |
| 820 | |
| 821 | /* Read */ |
| 822 | asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); |
| 823 | |
| 824 | /* Write to clear flags */ |
| 825 | val &= ARMV7_FLAG_MASK; |
| 826 | asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val)); |
| 827 | |
| 828 | return val; |
| 829 | } |
| 830 | |
| 831 | #ifdef DEBUG |
Sudeep KarkadaNagesha | 7279adb | 2012-07-20 15:18:07 +0100 | [diff] [blame] | 832 | static void armv7_pmnc_dump_regs(struct arm_pmu *cpu_pmu) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 833 | { |
| 834 | u32 val; |
| 835 | unsigned int cnt; |
| 836 | |
Will Deacon | 52a5566 | 2014-10-30 11:26:57 +0000 | [diff] [blame] | 837 | pr_info("PMNC registers dump:\n"); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 838 | |
| 839 | asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val)); |
Will Deacon | 52a5566 | 2014-10-30 11:26:57 +0000 | [diff] [blame] | 840 | pr_info("PMNC =0x%08x\n", val); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 841 | |
| 842 | asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val)); |
Will Deacon | 52a5566 | 2014-10-30 11:26:57 +0000 | [diff] [blame] | 843 | pr_info("CNTENS=0x%08x\n", val); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 844 | |
| 845 | asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val)); |
Will Deacon | 52a5566 | 2014-10-30 11:26:57 +0000 | [diff] [blame] | 846 | pr_info("INTENS=0x%08x\n", val); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 847 | |
| 848 | asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); |
Will Deacon | 52a5566 | 2014-10-30 11:26:57 +0000 | [diff] [blame] | 849 | pr_info("FLAGS =0x%08x\n", val); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 850 | |
| 851 | asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val)); |
Will Deacon | 52a5566 | 2014-10-30 11:26:57 +0000 | [diff] [blame] | 852 | pr_info("SELECT=0x%08x\n", val); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 853 | |
| 854 | asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val)); |
Will Deacon | 52a5566 | 2014-10-30 11:26:57 +0000 | [diff] [blame] | 855 | pr_info("CCNT =0x%08x\n", val); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 856 | |
Sudeep KarkadaNagesha | 7279adb | 2012-07-20 15:18:07 +0100 | [diff] [blame] | 857 | for (cnt = ARMV7_IDX_COUNTER0; |
| 858 | cnt <= ARMV7_IDX_COUNTER_LAST(cpu_pmu); cnt++) { |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 859 | armv7_pmnc_select_counter(cnt); |
| 860 | asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val)); |
Will Deacon | 52a5566 | 2014-10-30 11:26:57 +0000 | [diff] [blame] | 861 | pr_info("CNT[%d] count =0x%08x\n", |
Will Deacon | c691bb6 | 2011-07-19 22:25:55 +0100 | [diff] [blame] | 862 | ARMV7_IDX_TO_COUNTER(cnt), val); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 863 | asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val)); |
Will Deacon | 52a5566 | 2014-10-30 11:26:57 +0000 | [diff] [blame] | 864 | pr_info("CNT[%d] evtsel=0x%08x\n", |
Will Deacon | c691bb6 | 2011-07-19 22:25:55 +0100 | [diff] [blame] | 865 | ARMV7_IDX_TO_COUNTER(cnt), val); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 866 | } |
| 867 | } |
| 868 | #endif |
| 869 | |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 870 | static void armv7pmu_enable_event(struct perf_event *event) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 871 | { |
| 872 | unsigned long flags; |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 873 | struct hw_perf_event *hwc = &event->hw; |
| 874 | struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); |
Mark Rutland | 1167925 | 2014-05-13 19:36:31 +0100 | [diff] [blame] | 875 | struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events); |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 876 | int idx = hwc->idx; |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 877 | |
Sudeep KarkadaNagesha | 7279adb | 2012-07-20 15:18:07 +0100 | [diff] [blame] | 878 | if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) { |
| 879 | pr_err("CPU%u enabling wrong PMNC counter IRQ enable %d\n", |
| 880 | smp_processor_id(), idx); |
| 881 | return; |
| 882 | } |
| 883 | |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 884 | /* |
| 885 | * Enable counter and interrupt, and set the counter to count |
| 886 | * the event that we're interested in. |
| 887 | */ |
Mark Rutland | 0f78d2d | 2011-04-28 10:17:04 +0100 | [diff] [blame] | 888 | raw_spin_lock_irqsave(&events->pmu_lock, flags); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 889 | |
| 890 | /* |
| 891 | * Disable counter |
| 892 | */ |
| 893 | armv7_pmnc_disable_counter(idx); |
| 894 | |
| 895 | /* |
| 896 | * Set event (if destined for PMNx counters) |
Will Deacon | a505add | 2011-07-19 13:53:36 +0100 | [diff] [blame] | 897 | * We only need to set the event for the cycle counter if we |
| 898 | * have the ability to perform event filtering. |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 899 | */ |
Sudeep KarkadaNagesha | 513c99c | 2012-07-31 10:11:23 +0100 | [diff] [blame] | 900 | if (cpu_pmu->set_event_filter || idx != ARMV7_IDX_CYCLE_COUNTER) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 901 | armv7_pmnc_write_evtsel(idx, hwc->config_base); |
| 902 | |
| 903 | /* |
| 904 | * Enable interrupt for this counter |
| 905 | */ |
| 906 | armv7_pmnc_enable_intens(idx); |
| 907 | |
| 908 | /* |
| 909 | * Enable counter |
| 910 | */ |
| 911 | armv7_pmnc_enable_counter(idx); |
| 912 | |
Mark Rutland | 0f78d2d | 2011-04-28 10:17:04 +0100 | [diff] [blame] | 913 | raw_spin_unlock_irqrestore(&events->pmu_lock, flags); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 914 | } |
| 915 | |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 916 | static void armv7pmu_disable_event(struct perf_event *event) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 917 | { |
| 918 | unsigned long flags; |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 919 | struct hw_perf_event *hwc = &event->hw; |
| 920 | struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); |
Mark Rutland | 1167925 | 2014-05-13 19:36:31 +0100 | [diff] [blame] | 921 | struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events); |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 922 | int idx = hwc->idx; |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 923 | |
Sudeep KarkadaNagesha | 7279adb | 2012-07-20 15:18:07 +0100 | [diff] [blame] | 924 | if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) { |
| 925 | pr_err("CPU%u disabling wrong PMNC counter IRQ enable %d\n", |
| 926 | smp_processor_id(), idx); |
| 927 | return; |
| 928 | } |
| 929 | |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 930 | /* |
| 931 | * Disable counter and interrupt |
| 932 | */ |
Mark Rutland | 0f78d2d | 2011-04-28 10:17:04 +0100 | [diff] [blame] | 933 | raw_spin_lock_irqsave(&events->pmu_lock, flags); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 934 | |
| 935 | /* |
| 936 | * Disable counter |
| 937 | */ |
| 938 | armv7_pmnc_disable_counter(idx); |
| 939 | |
| 940 | /* |
| 941 | * Disable interrupt for this counter |
| 942 | */ |
| 943 | armv7_pmnc_disable_intens(idx); |
| 944 | |
Mark Rutland | 0f78d2d | 2011-04-28 10:17:04 +0100 | [diff] [blame] | 945 | raw_spin_unlock_irqrestore(&events->pmu_lock, flags); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 946 | } |
| 947 | |
| 948 | static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev) |
| 949 | { |
Will Deacon | 6330aae | 2011-07-19 14:55:57 +0100 | [diff] [blame] | 950 | u32 pmnc; |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 951 | struct perf_sample_data data; |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 952 | struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev; |
Mark Rutland | 1167925 | 2014-05-13 19:36:31 +0100 | [diff] [blame] | 953 | struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 954 | struct pt_regs *regs; |
| 955 | int idx; |
| 956 | |
| 957 | /* |
| 958 | * Get and reset the IRQ flags |
| 959 | */ |
| 960 | pmnc = armv7_pmnc_getreset_flags(); |
| 961 | |
| 962 | /* |
| 963 | * Did an overflow occur? |
| 964 | */ |
| 965 | if (!armv7_pmnc_has_overflowed(pmnc)) |
| 966 | return IRQ_NONE; |
| 967 | |
| 968 | /* |
| 969 | * Handle the counter(s) overflow(s) |
| 970 | */ |
| 971 | regs = get_irq_regs(); |
| 972 | |
Mark Rutland | 8be3f9a | 2011-05-17 11:20:11 +0100 | [diff] [blame] | 973 | for (idx = 0; idx < cpu_pmu->num_events; ++idx) { |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 974 | struct perf_event *event = cpuc->events[idx]; |
| 975 | struct hw_perf_event *hwc; |
| 976 | |
Will Deacon | f6f5a30 | 2012-03-06 17:34:50 +0100 | [diff] [blame] | 977 | /* Ignore if we don't have an event. */ |
| 978 | if (!event) |
| 979 | continue; |
| 980 | |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 981 | /* |
| 982 | * We have a single interrupt for all counters. Check that |
| 983 | * each counter has overflowed before we process it. |
| 984 | */ |
| 985 | if (!armv7_pmnc_counter_has_overflowed(pmnc, idx)) |
| 986 | continue; |
| 987 | |
| 988 | hwc = &event->hw; |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 989 | armpmu_event_update(event); |
Robert Richter | fd0d000 | 2012-04-02 20:19:08 +0200 | [diff] [blame] | 990 | perf_sample_data_init(&data, 0, hwc->last_period); |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 991 | if (!armpmu_event_set_period(event)) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 992 | continue; |
| 993 | |
Peter Zijlstra | a8b0ca1 | 2011-06-27 14:41:57 +0200 | [diff] [blame] | 994 | if (perf_event_overflow(event, &data, regs)) |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 995 | cpu_pmu->disable(event); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 996 | } |
| 997 | |
| 998 | /* |
| 999 | * Handle the pending perf events. |
| 1000 | * |
| 1001 | * Note: this call *must* be run with interrupts disabled. For |
| 1002 | * platforms that can have the PMU interrupts raised as an NMI, this |
| 1003 | * will not work. |
| 1004 | */ |
| 1005 | irq_work_run(); |
| 1006 | |
| 1007 | return IRQ_HANDLED; |
| 1008 | } |
| 1009 | |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 1010 | static void armv7pmu_start(struct arm_pmu *cpu_pmu) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 1011 | { |
| 1012 | unsigned long flags; |
Mark Rutland | 1167925 | 2014-05-13 19:36:31 +0100 | [diff] [blame] | 1013 | struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 1014 | |
Mark Rutland | 0f78d2d | 2011-04-28 10:17:04 +0100 | [diff] [blame] | 1015 | raw_spin_lock_irqsave(&events->pmu_lock, flags); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 1016 | /* Enable all counters */ |
| 1017 | armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E); |
Mark Rutland | 0f78d2d | 2011-04-28 10:17:04 +0100 | [diff] [blame] | 1018 | raw_spin_unlock_irqrestore(&events->pmu_lock, flags); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 1019 | } |
| 1020 | |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 1021 | static void armv7pmu_stop(struct arm_pmu *cpu_pmu) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 1022 | { |
| 1023 | unsigned long flags; |
Mark Rutland | 1167925 | 2014-05-13 19:36:31 +0100 | [diff] [blame] | 1024 | struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 1025 | |
Mark Rutland | 0f78d2d | 2011-04-28 10:17:04 +0100 | [diff] [blame] | 1026 | raw_spin_lock_irqsave(&events->pmu_lock, flags); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 1027 | /* Disable all counters */ |
| 1028 | armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E); |
Mark Rutland | 0f78d2d | 2011-04-28 10:17:04 +0100 | [diff] [blame] | 1029 | raw_spin_unlock_irqrestore(&events->pmu_lock, flags); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 1030 | } |
| 1031 | |
Mark Rutland | 8be3f9a | 2011-05-17 11:20:11 +0100 | [diff] [blame] | 1032 | static int armv7pmu_get_event_idx(struct pmu_hw_events *cpuc, |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 1033 | struct perf_event *event) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 1034 | { |
| 1035 | int idx; |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 1036 | struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); |
| 1037 | struct hw_perf_event *hwc = &event->hw; |
| 1038 | unsigned long evtype = hwc->config_base & ARMV7_EVTYPE_EVENT; |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 1039 | |
| 1040 | /* Always place a cycle counter into the cycle counter. */ |
Will Deacon | a505add | 2011-07-19 13:53:36 +0100 | [diff] [blame] | 1041 | if (evtype == ARMV7_PERFCTR_CPU_CYCLES) { |
Will Deacon | c691bb6 | 2011-07-19 22:25:55 +0100 | [diff] [blame] | 1042 | if (test_and_set_bit(ARMV7_IDX_CYCLE_COUNTER, cpuc->used_mask)) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 1043 | return -EAGAIN; |
| 1044 | |
Will Deacon | c691bb6 | 2011-07-19 22:25:55 +0100 | [diff] [blame] | 1045 | return ARMV7_IDX_CYCLE_COUNTER; |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 1046 | } |
Will Deacon | c691bb6 | 2011-07-19 22:25:55 +0100 | [diff] [blame] | 1047 | |
| 1048 | /* |
| 1049 | * For anything other than a cycle counter, try and use |
| 1050 | * the events counters |
| 1051 | */ |
Mark Rutland | 8be3f9a | 2011-05-17 11:20:11 +0100 | [diff] [blame] | 1052 | for (idx = ARMV7_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) { |
Will Deacon | c691bb6 | 2011-07-19 22:25:55 +0100 | [diff] [blame] | 1053 | if (!test_and_set_bit(idx, cpuc->used_mask)) |
| 1054 | return idx; |
| 1055 | } |
| 1056 | |
| 1057 | /* The counters are all in use. */ |
| 1058 | return -EAGAIN; |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 1059 | } |
| 1060 | |
Will Deacon | a505add | 2011-07-19 13:53:36 +0100 | [diff] [blame] | 1061 | /* |
| 1062 | * Add an event filter to a given event. This will only work for PMUv2 PMUs. |
| 1063 | */ |
| 1064 | static int armv7pmu_set_event_filter(struct hw_perf_event *event, |
| 1065 | struct perf_event_attr *attr) |
| 1066 | { |
| 1067 | unsigned long config_base = 0; |
| 1068 | |
Will Deacon | a505add | 2011-07-19 13:53:36 +0100 | [diff] [blame] | 1069 | if (attr->exclude_user) |
| 1070 | config_base |= ARMV7_EXCLUDE_USER; |
| 1071 | if (attr->exclude_kernel) |
| 1072 | config_base |= ARMV7_EXCLUDE_PL1; |
| 1073 | if (!attr->exclude_hv) |
| 1074 | config_base |= ARMV7_INCLUDE_HYP; |
| 1075 | |
| 1076 | /* |
| 1077 | * Install the filter into config_base as this is used to |
| 1078 | * construct the event type. |
| 1079 | */ |
| 1080 | event->config_base = config_base; |
| 1081 | |
| 1082 | return 0; |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 1083 | } |
| 1084 | |
Will Deacon | 574b69c | 2011-03-25 13:13:34 +0100 | [diff] [blame] | 1085 | static void armv7pmu_reset(void *info) |
| 1086 | { |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 1087 | struct arm_pmu *cpu_pmu = (struct arm_pmu *)info; |
Martin Fuzzey | 8d1a0ae | 2016-01-13 23:36:26 -0500 | [diff] [blame] | 1088 | u32 idx, nb_cnt = cpu_pmu->num_events, val; |
| 1089 | |
| 1090 | if (cpu_pmu->secure_access) { |
| 1091 | asm volatile("mrc p15, 0, %0, c1, c1, 1" : "=r" (val)); |
| 1092 | val |= ARMV7_SDER_SUNIDEN; |
| 1093 | asm volatile("mcr p15, 0, %0, c1, c1, 1" : : "r" (val)); |
| 1094 | } |
Will Deacon | 574b69c | 2011-03-25 13:13:34 +0100 | [diff] [blame] | 1095 | |
| 1096 | /* The counter and interrupt enable registers are unknown at reset. */ |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 1097 | for (idx = ARMV7_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) { |
| 1098 | armv7_pmnc_disable_counter(idx); |
| 1099 | armv7_pmnc_disable_intens(idx); |
| 1100 | } |
Will Deacon | 574b69c | 2011-03-25 13:13:34 +0100 | [diff] [blame] | 1101 | |
| 1102 | /* Initialize & Reset PMNC: C and P bits */ |
Prasad Sodagudi | fda5fed | 2015-11-19 15:19:46 +0530 | [diff] [blame] | 1103 | armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_P | ARMV7_PMNC_C); |
Will Deacon | 574b69c | 2011-03-25 13:13:34 +0100 | [diff] [blame] | 1104 | } |
| 1105 | |
Mark Rutland | e1f431b | 2011-04-28 15:47:10 +0100 | [diff] [blame] | 1106 | static int armv7_a8_map_event(struct perf_event *event) |
| 1107 | { |
Will Deacon | 6dbc002 | 2012-07-29 12:36:28 +0100 | [diff] [blame] | 1108 | return armpmu_map_event(event, &armv7_a8_perf_map, |
Mark Rutland | e1f431b | 2011-04-28 15:47:10 +0100 | [diff] [blame] | 1109 | &armv7_a8_perf_cache_map, 0xFF); |
| 1110 | } |
| 1111 | |
| 1112 | static int armv7_a9_map_event(struct perf_event *event) |
| 1113 | { |
Will Deacon | 6dbc002 | 2012-07-29 12:36:28 +0100 | [diff] [blame] | 1114 | return armpmu_map_event(event, &armv7_a9_perf_map, |
Mark Rutland | e1f431b | 2011-04-28 15:47:10 +0100 | [diff] [blame] | 1115 | &armv7_a9_perf_cache_map, 0xFF); |
| 1116 | } |
| 1117 | |
| 1118 | static int armv7_a5_map_event(struct perf_event *event) |
| 1119 | { |
Will Deacon | 6dbc002 | 2012-07-29 12:36:28 +0100 | [diff] [blame] | 1120 | return armpmu_map_event(event, &armv7_a5_perf_map, |
Mark Rutland | e1f431b | 2011-04-28 15:47:10 +0100 | [diff] [blame] | 1121 | &armv7_a5_perf_cache_map, 0xFF); |
| 1122 | } |
| 1123 | |
| 1124 | static int armv7_a15_map_event(struct perf_event *event) |
| 1125 | { |
Will Deacon | 6dbc002 | 2012-07-29 12:36:28 +0100 | [diff] [blame] | 1126 | return armpmu_map_event(event, &armv7_a15_perf_map, |
Mark Rutland | e1f431b | 2011-04-28 15:47:10 +0100 | [diff] [blame] | 1127 | &armv7_a15_perf_cache_map, 0xFF); |
| 1128 | } |
| 1129 | |
Will Deacon | d33c88c | 2012-02-03 14:46:01 +0100 | [diff] [blame] | 1130 | static int armv7_a7_map_event(struct perf_event *event) |
| 1131 | { |
Will Deacon | 6dbc002 | 2012-07-29 12:36:28 +0100 | [diff] [blame] | 1132 | return armpmu_map_event(event, &armv7_a7_perf_map, |
Will Deacon | d33c88c | 2012-02-03 14:46:01 +0100 | [diff] [blame] | 1133 | &armv7_a7_perf_cache_map, 0xFF); |
| 1134 | } |
| 1135 | |
Albin Tonnerre | 8e781f6 | 2014-01-29 14:28:57 +0000 | [diff] [blame] | 1136 | static int armv7_a12_map_event(struct perf_event *event) |
| 1137 | { |
| 1138 | return armpmu_map_event(event, &armv7_a12_perf_map, |
| 1139 | &armv7_a12_perf_cache_map, 0xFF); |
| 1140 | } |
| 1141 | |
Stephen Boyd | 2a3391c | 2014-02-07 21:01:21 +0000 | [diff] [blame] | 1142 | static int krait_map_event(struct perf_event *event) |
| 1143 | { |
| 1144 | return armpmu_map_event(event, &krait_perf_map, |
| 1145 | &krait_perf_cache_map, 0xFFFFF); |
| 1146 | } |
| 1147 | |
| 1148 | static int krait_map_event_no_branch(struct perf_event *event) |
| 1149 | { |
| 1150 | return armpmu_map_event(event, &krait_perf_map_no_branch, |
| 1151 | &krait_perf_cache_map, 0xFFFFF); |
| 1152 | } |
| 1153 | |
Stephen Boyd | 341e42c | 2015-02-27 16:11:35 -0800 | [diff] [blame] | 1154 | static int scorpion_map_event(struct perf_event *event) |
| 1155 | { |
| 1156 | return armpmu_map_event(event, &scorpion_perf_map, |
| 1157 | &scorpion_perf_cache_map, 0xFFFFF); |
| 1158 | } |
| 1159 | |
Sudeep KarkadaNagesha | 513c99c | 2012-07-31 10:11:23 +0100 | [diff] [blame] | 1160 | static void armv7pmu_init(struct arm_pmu *cpu_pmu) |
| 1161 | { |
| 1162 | cpu_pmu->handle_irq = armv7pmu_handle_irq; |
| 1163 | cpu_pmu->enable = armv7pmu_enable_event; |
| 1164 | cpu_pmu->disable = armv7pmu_disable_event; |
| 1165 | cpu_pmu->read_counter = armv7pmu_read_counter; |
| 1166 | cpu_pmu->write_counter = armv7pmu_write_counter; |
| 1167 | cpu_pmu->get_event_idx = armv7pmu_get_event_idx; |
| 1168 | cpu_pmu->start = armv7pmu_start; |
| 1169 | cpu_pmu->stop = armv7pmu_stop; |
| 1170 | cpu_pmu->reset = armv7pmu_reset; |
| 1171 | cpu_pmu->max_period = (1LLU << 32) - 1; |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 1172 | }; |
| 1173 | |
Mark Rutland | 0e3038d | 2015-05-13 17:12:27 +0100 | [diff] [blame] | 1174 | static void armv7_read_num_pmnc_events(void *info) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 1175 | { |
Mark Rutland | 0e3038d | 2015-05-13 17:12:27 +0100 | [diff] [blame] | 1176 | int *nb_cnt = info; |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 1177 | |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 1178 | /* Read the nb of CNTx counters supported from PMNC */ |
Mark Rutland | 0e3038d | 2015-05-13 17:12:27 +0100 | [diff] [blame] | 1179 | *nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK; |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 1180 | |
Mark Rutland | 0e3038d | 2015-05-13 17:12:27 +0100 | [diff] [blame] | 1181 | /* Add the CPU cycles counter */ |
| 1182 | *nb_cnt += 1; |
| 1183 | } |
| 1184 | |
Raghavendra Rao Ananta | 31ff143 | 2018-05-09 19:49:48 -0700 | [diff] [blame] | 1185 | static void armv7_pmu_idle_update(struct arm_pmu *cpu_pmu) |
Mark Rutland | 0e3038d | 2015-05-13 17:12:27 +0100 | [diff] [blame] | 1186 | { |
Raghavendra Rao Ananta | 31ff143 | 2018-05-09 19:49:48 -0700 | [diff] [blame] | 1187 | struct pmu_hw_events *hw_events; |
| 1188 | struct perf_event *event; |
| 1189 | int idx; |
| 1190 | |
| 1191 | if (!cpu_pmu) |
| 1192 | return; |
| 1193 | |
| 1194 | hw_events = this_cpu_ptr(cpu_pmu->hw_events); |
| 1195 | if (!hw_events) |
| 1196 | return; |
| 1197 | |
| 1198 | for (idx = 0; idx < cpu_pmu->num_events; ++idx) { |
| 1199 | event = hw_events->events[idx]; |
| 1200 | |
| 1201 | if (!event || !event->attr.exclude_idle || |
| 1202 | event->state != PERF_EVENT_STATE_ACTIVE) |
| 1203 | continue; |
| 1204 | |
| 1205 | cpu_pmu->pmu.read(event); |
| 1206 | } |
| 1207 | } |
| 1208 | |
| 1209 | struct armv7_pmu_idle_nb { |
| 1210 | struct arm_pmu *cpu_pmu; |
| 1211 | struct notifier_block perf_cpu_idle_nb; |
| 1212 | }; |
| 1213 | |
| 1214 | static int armv7_pmu_idle_notifier(struct notifier_block *nb, |
| 1215 | unsigned long action, void *data) |
| 1216 | { |
| 1217 | struct armv7_pmu_idle_nb *pmu_idle_nb = container_of(nb, |
| 1218 | struct armv7_pmu_idle_nb, perf_cpu_idle_nb); |
| 1219 | |
| 1220 | if (action == IDLE_START) |
| 1221 | armv7_pmu_idle_update(pmu_idle_nb->cpu_pmu); |
| 1222 | |
| 1223 | return NOTIFY_OK; |
| 1224 | } |
| 1225 | |
| 1226 | static int armv7_probe_pmu(struct arm_pmu *arm_pmu) |
| 1227 | { |
Raghavendra Rao Ananta | ad9b5da | 2018-05-23 16:58:49 -0700 | [diff] [blame] | 1228 | return smp_call_function_any(&arm_pmu->supported_cpus, |
Mark Rutland | 0e3038d | 2015-05-13 17:12:27 +0100 | [diff] [blame] | 1229 | armv7_read_num_pmnc_events, |
| 1230 | &arm_pmu->num_events, 1); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 1231 | } |
| 1232 | |
Greg Kroah-Hartman | 351a102 | 2012-12-21 14:02:24 -0800 | [diff] [blame] | 1233 | static int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 1234 | { |
Sudeep KarkadaNagesha | 513c99c | 2012-07-31 10:11:23 +0100 | [diff] [blame] | 1235 | armv7pmu_init(cpu_pmu); |
Mark Rutland | 3d1ff75 | 2012-12-19 16:33:24 +0000 | [diff] [blame] | 1236 | cpu_pmu->name = "armv7_cortex_a8"; |
Sudeep KarkadaNagesha | 513c99c | 2012-07-31 10:11:23 +0100 | [diff] [blame] | 1237 | cpu_pmu->map_event = armv7_a8_map_event; |
Mark Rutland | 9268c5d | 2016-09-09 14:08:28 +0100 | [diff] [blame] | 1238 | cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = |
| 1239 | &armv7_pmuv1_events_attr_group; |
| 1240 | cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = |
| 1241 | &armv7_pmu_format_attr_group; |
Raghavendra Rao Ananta | 31ff143 | 2018-05-09 19:49:48 -0700 | [diff] [blame] | 1242 | return armv7_probe_pmu(cpu_pmu); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 1243 | } |
| 1244 | |
Greg Kroah-Hartman | 351a102 | 2012-12-21 14:02:24 -0800 | [diff] [blame] | 1245 | static int armv7_a9_pmu_init(struct arm_pmu *cpu_pmu) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 1246 | { |
Sudeep KarkadaNagesha | 513c99c | 2012-07-31 10:11:23 +0100 | [diff] [blame] | 1247 | armv7pmu_init(cpu_pmu); |
Mark Rutland | 3d1ff75 | 2012-12-19 16:33:24 +0000 | [diff] [blame] | 1248 | cpu_pmu->name = "armv7_cortex_a9"; |
Sudeep KarkadaNagesha | 513c99c | 2012-07-31 10:11:23 +0100 | [diff] [blame] | 1249 | cpu_pmu->map_event = armv7_a9_map_event; |
Mark Rutland | 9268c5d | 2016-09-09 14:08:28 +0100 | [diff] [blame] | 1250 | cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = |
| 1251 | &armv7_pmuv1_events_attr_group; |
| 1252 | cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = |
| 1253 | &armv7_pmu_format_attr_group; |
Raghavendra Rao Ananta | 31ff143 | 2018-05-09 19:49:48 -0700 | [diff] [blame] | 1254 | return armv7_probe_pmu(cpu_pmu); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 1255 | } |
Will Deacon | 0c205cb | 2011-06-03 17:40:15 +0100 | [diff] [blame] | 1256 | |
Greg Kroah-Hartman | 351a102 | 2012-12-21 14:02:24 -0800 | [diff] [blame] | 1257 | static int armv7_a5_pmu_init(struct arm_pmu *cpu_pmu) |
Will Deacon | 0c205cb | 2011-06-03 17:40:15 +0100 | [diff] [blame] | 1258 | { |
Sudeep KarkadaNagesha | 513c99c | 2012-07-31 10:11:23 +0100 | [diff] [blame] | 1259 | armv7pmu_init(cpu_pmu); |
Mark Rutland | 3d1ff75 | 2012-12-19 16:33:24 +0000 | [diff] [blame] | 1260 | cpu_pmu->name = "armv7_cortex_a5"; |
Sudeep KarkadaNagesha | 513c99c | 2012-07-31 10:11:23 +0100 | [diff] [blame] | 1261 | cpu_pmu->map_event = armv7_a5_map_event; |
Mark Rutland | 9268c5d | 2016-09-09 14:08:28 +0100 | [diff] [blame] | 1262 | cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = |
| 1263 | &armv7_pmuv1_events_attr_group; |
| 1264 | cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = |
| 1265 | &armv7_pmu_format_attr_group; |
Raghavendra Rao Ananta | 31ff143 | 2018-05-09 19:49:48 -0700 | [diff] [blame] | 1266 | return armv7_probe_pmu(cpu_pmu); |
Will Deacon | 0c205cb | 2011-06-03 17:40:15 +0100 | [diff] [blame] | 1267 | } |
Will Deacon | 14abd03 | 2011-01-19 14:24:38 +0000 | [diff] [blame] | 1268 | |
Greg Kroah-Hartman | 351a102 | 2012-12-21 14:02:24 -0800 | [diff] [blame] | 1269 | static int armv7_a15_pmu_init(struct arm_pmu *cpu_pmu) |
Will Deacon | 14abd03 | 2011-01-19 14:24:38 +0000 | [diff] [blame] | 1270 | { |
Sudeep KarkadaNagesha | 513c99c | 2012-07-31 10:11:23 +0100 | [diff] [blame] | 1271 | armv7pmu_init(cpu_pmu); |
Mark Rutland | 3d1ff75 | 2012-12-19 16:33:24 +0000 | [diff] [blame] | 1272 | cpu_pmu->name = "armv7_cortex_a15"; |
Sudeep KarkadaNagesha | 513c99c | 2012-07-31 10:11:23 +0100 | [diff] [blame] | 1273 | cpu_pmu->map_event = armv7_a15_map_event; |
Sudeep KarkadaNagesha | 513c99c | 2012-07-31 10:11:23 +0100 | [diff] [blame] | 1274 | cpu_pmu->set_event_filter = armv7pmu_set_event_filter; |
Mark Rutland | 9268c5d | 2016-09-09 14:08:28 +0100 | [diff] [blame] | 1275 | cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = |
| 1276 | &armv7_pmuv2_events_attr_group; |
| 1277 | cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = |
| 1278 | &armv7_pmu_format_attr_group; |
Raghavendra Rao Ananta | 31ff143 | 2018-05-09 19:49:48 -0700 | [diff] [blame] | 1279 | return armv7_probe_pmu(cpu_pmu); |
Will Deacon | 14abd03 | 2011-01-19 14:24:38 +0000 | [diff] [blame] | 1280 | } |
Will Deacon | d33c88c | 2012-02-03 14:46:01 +0100 | [diff] [blame] | 1281 | |
blong | 9eb77b9 | 2018-06-20 17:33:16 +0800 | [diff] [blame] | 1282 | static int armv8_pmuv3_pmu_init(struct arm_pmu *cpu_pmu) |
| 1283 | { |
| 1284 | armv7pmu_init(cpu_pmu); |
| 1285 | cpu_pmu->name = "ARMv8 Cortex-A53"; |
| 1286 | cpu_pmu->map_event = armv7_a7_map_event; |
| 1287 | armv7_read_num_pmnc_events(&cpu_pmu->num_events); |
| 1288 | cpu_pmu->set_event_filter = armv7pmu_set_event_filter; |
| 1289 | return 0; |
| 1290 | } |
| 1291 | |
Greg Kroah-Hartman | 351a102 | 2012-12-21 14:02:24 -0800 | [diff] [blame] | 1292 | static int armv7_a7_pmu_init(struct arm_pmu *cpu_pmu) |
Will Deacon | d33c88c | 2012-02-03 14:46:01 +0100 | [diff] [blame] | 1293 | { |
Sudeep KarkadaNagesha | 513c99c | 2012-07-31 10:11:23 +0100 | [diff] [blame] | 1294 | armv7pmu_init(cpu_pmu); |
Mark Rutland | 3d1ff75 | 2012-12-19 16:33:24 +0000 | [diff] [blame] | 1295 | cpu_pmu->name = "armv7_cortex_a7"; |
Sudeep KarkadaNagesha | 513c99c | 2012-07-31 10:11:23 +0100 | [diff] [blame] | 1296 | cpu_pmu->map_event = armv7_a7_map_event; |
Sudeep KarkadaNagesha | 513c99c | 2012-07-31 10:11:23 +0100 | [diff] [blame] | 1297 | cpu_pmu->set_event_filter = armv7pmu_set_event_filter; |
Mark Rutland | 9268c5d | 2016-09-09 14:08:28 +0100 | [diff] [blame] | 1298 | cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = |
| 1299 | &armv7_pmuv2_events_attr_group; |
| 1300 | cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = |
| 1301 | &armv7_pmu_format_attr_group; |
Raghavendra Rao Ananta | 31ff143 | 2018-05-09 19:49:48 -0700 | [diff] [blame] | 1302 | return armv7_probe_pmu(cpu_pmu); |
Will Deacon | d33c88c | 2012-02-03 14:46:01 +0100 | [diff] [blame] | 1303 | } |
Stephen Boyd | 2a3391c | 2014-02-07 21:01:21 +0000 | [diff] [blame] | 1304 | |
Albin Tonnerre | 8e781f6 | 2014-01-29 14:28:57 +0000 | [diff] [blame] | 1305 | static int armv7_a12_pmu_init(struct arm_pmu *cpu_pmu) |
| 1306 | { |
| 1307 | armv7pmu_init(cpu_pmu); |
Mark Rutland | 3d1ff75 | 2012-12-19 16:33:24 +0000 | [diff] [blame] | 1308 | cpu_pmu->name = "armv7_cortex_a12"; |
Albin Tonnerre | 8e781f6 | 2014-01-29 14:28:57 +0000 | [diff] [blame] | 1309 | cpu_pmu->map_event = armv7_a12_map_event; |
Albin Tonnerre | 8e781f6 | 2014-01-29 14:28:57 +0000 | [diff] [blame] | 1310 | cpu_pmu->set_event_filter = armv7pmu_set_event_filter; |
Mark Rutland | 9268c5d | 2016-09-09 14:08:28 +0100 | [diff] [blame] | 1311 | cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = |
| 1312 | &armv7_pmuv2_events_attr_group; |
| 1313 | cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = |
| 1314 | &armv7_pmu_format_attr_group; |
Raghavendra Rao Ananta | 31ff143 | 2018-05-09 19:49:48 -0700 | [diff] [blame] | 1315 | return armv7_probe_pmu(cpu_pmu); |
Albin Tonnerre | 8e781f6 | 2014-01-29 14:28:57 +0000 | [diff] [blame] | 1316 | } |
| 1317 | |
Will Deacon | 03eff46 | 2014-05-09 18:34:19 +0100 | [diff] [blame] | 1318 | static int armv7_a17_pmu_init(struct arm_pmu *cpu_pmu) |
| 1319 | { |
Mark Rutland | 0e3038d | 2015-05-13 17:12:27 +0100 | [diff] [blame] | 1320 | int ret = armv7_a12_pmu_init(cpu_pmu); |
Mark Rutland | 3d1ff75 | 2012-12-19 16:33:24 +0000 | [diff] [blame] | 1321 | cpu_pmu->name = "armv7_cortex_a17"; |
Mark Rutland | 9268c5d | 2016-09-09 14:08:28 +0100 | [diff] [blame] | 1322 | cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = |
| 1323 | &armv7_pmuv2_events_attr_group; |
| 1324 | cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = |
| 1325 | &armv7_pmu_format_attr_group; |
Mark Rutland | 0e3038d | 2015-05-13 17:12:27 +0100 | [diff] [blame] | 1326 | return ret; |
Will Deacon | 03eff46 | 2014-05-09 18:34:19 +0100 | [diff] [blame] | 1327 | } |
| 1328 | |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1329 | /* |
| 1330 | * Krait Performance Monitor Region Event Selection Register (PMRESRn) |
| 1331 | * |
| 1332 | * 31 30 24 16 8 0 |
| 1333 | * +--------------------------------+ |
| 1334 | * PMRESR0 | EN | CC | CC | CC | CC | N = 1, R = 0 |
| 1335 | * +--------------------------------+ |
| 1336 | * PMRESR1 | EN | CC | CC | CC | CC | N = 1, R = 1 |
| 1337 | * +--------------------------------+ |
| 1338 | * PMRESR2 | EN | CC | CC | CC | CC | N = 1, R = 2 |
| 1339 | * +--------------------------------+ |
| 1340 | * VPMRESR0 | EN | CC | CC | CC | CC | N = 2, R = ? |
| 1341 | * +--------------------------------+ |
| 1342 | * EN | G=3 | G=2 | G=1 | G=0 |
| 1343 | * |
| 1344 | * Event Encoding: |
| 1345 | * |
| 1346 | * hwc->config_base = 0xNRCCG |
| 1347 | * |
| 1348 | * N = prefix, 1 for Krait CPU (PMRESRn), 2 for Venum VFP (VPMRESR) |
| 1349 | * R = region register |
| 1350 | * CC = class of events the group G is choosing from |
| 1351 | * G = group or particular event |
| 1352 | * |
| 1353 | * Example: 0x12021 is a Krait CPU event in PMRESR2's group 1 with code 2 |
| 1354 | * |
| 1355 | * A region (R) corresponds to a piece of the CPU (execution unit, instruction |
| 1356 | * unit, etc.) while the event code (CC) corresponds to a particular class of |
| 1357 | * events (interrupts for example). An event code is broken down into |
| 1358 | * groups (G) that can be mapped into the PMU (irq, fiqs, and irq+fiqs for |
| 1359 | * example). |
| 1360 | */ |
| 1361 | |
| 1362 | #define KRAIT_EVENT (1 << 16) |
| 1363 | #define VENUM_EVENT (2 << 16) |
| 1364 | #define KRAIT_EVENT_MASK (KRAIT_EVENT | VENUM_EVENT) |
| 1365 | #define PMRESRn_EN BIT(31) |
| 1366 | |
Stephen Boyd | 65bab45 | 2015-02-28 00:11:33 +0000 | [diff] [blame] | 1367 | #define EVENT_REGION(event) (((event) >> 12) & 0xf) /* R */ |
| 1368 | #define EVENT_GROUP(event) ((event) & 0xf) /* G */ |
| 1369 | #define EVENT_CODE(event) (((event) >> 4) & 0xff) /* CC */ |
| 1370 | #define EVENT_VENUM(event) (!!(event & VENUM_EVENT)) /* N=2 */ |
| 1371 | #define EVENT_CPU(event) (!!(event & KRAIT_EVENT)) /* N=1 */ |
| 1372 | |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1373 | static u32 krait_read_pmresrn(int n) |
| 1374 | { |
| 1375 | u32 val; |
| 1376 | |
| 1377 | switch (n) { |
| 1378 | case 0: |
| 1379 | asm volatile("mrc p15, 1, %0, c9, c15, 0" : "=r" (val)); |
| 1380 | break; |
| 1381 | case 1: |
| 1382 | asm volatile("mrc p15, 1, %0, c9, c15, 1" : "=r" (val)); |
| 1383 | break; |
| 1384 | case 2: |
| 1385 | asm volatile("mrc p15, 1, %0, c9, c15, 2" : "=r" (val)); |
| 1386 | break; |
| 1387 | default: |
| 1388 | BUG(); /* Should be validated in krait_pmu_get_event_idx() */ |
| 1389 | } |
| 1390 | |
| 1391 | return val; |
| 1392 | } |
| 1393 | |
| 1394 | static void krait_write_pmresrn(int n, u32 val) |
| 1395 | { |
| 1396 | switch (n) { |
| 1397 | case 0: |
| 1398 | asm volatile("mcr p15, 1, %0, c9, c15, 0" : : "r" (val)); |
| 1399 | break; |
| 1400 | case 1: |
| 1401 | asm volatile("mcr p15, 1, %0, c9, c15, 1" : : "r" (val)); |
| 1402 | break; |
| 1403 | case 2: |
| 1404 | asm volatile("mcr p15, 1, %0, c9, c15, 2" : : "r" (val)); |
| 1405 | break; |
| 1406 | default: |
| 1407 | BUG(); /* Should be validated in krait_pmu_get_event_idx() */ |
| 1408 | } |
| 1409 | } |
| 1410 | |
Stephen Boyd | 65bab45 | 2015-02-28 00:11:33 +0000 | [diff] [blame] | 1411 | static u32 venum_read_pmresr(void) |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1412 | { |
| 1413 | u32 val; |
| 1414 | asm volatile("mrc p10, 7, %0, c11, c0, 0" : "=r" (val)); |
| 1415 | return val; |
| 1416 | } |
| 1417 | |
Stephen Boyd | 65bab45 | 2015-02-28 00:11:33 +0000 | [diff] [blame] | 1418 | static void venum_write_pmresr(u32 val) |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1419 | { |
| 1420 | asm volatile("mcr p10, 7, %0, c11, c0, 0" : : "r" (val)); |
| 1421 | } |
| 1422 | |
Stephen Boyd | 65bab45 | 2015-02-28 00:11:33 +0000 | [diff] [blame] | 1423 | static void venum_pre_pmresr(u32 *venum_orig_val, u32 *fp_orig_val) |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1424 | { |
| 1425 | u32 venum_new_val; |
| 1426 | u32 fp_new_val; |
| 1427 | |
| 1428 | BUG_ON(preemptible()); |
| 1429 | /* CPACR Enable CP10 and CP11 access */ |
| 1430 | *venum_orig_val = get_copro_access(); |
| 1431 | venum_new_val = *venum_orig_val | CPACC_SVC(10) | CPACC_SVC(11); |
| 1432 | set_copro_access(venum_new_val); |
| 1433 | |
| 1434 | /* Enable FPEXC */ |
| 1435 | *fp_orig_val = fmrx(FPEXC); |
| 1436 | fp_new_val = *fp_orig_val | FPEXC_EN; |
| 1437 | fmxr(FPEXC, fp_new_val); |
| 1438 | } |
| 1439 | |
Stephen Boyd | 65bab45 | 2015-02-28 00:11:33 +0000 | [diff] [blame] | 1440 | static void venum_post_pmresr(u32 venum_orig_val, u32 fp_orig_val) |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1441 | { |
| 1442 | BUG_ON(preemptible()); |
| 1443 | /* Restore FPEXC */ |
| 1444 | fmxr(FPEXC, fp_orig_val); |
| 1445 | isb(); |
| 1446 | /* Restore CPACR */ |
| 1447 | set_copro_access(venum_orig_val); |
| 1448 | } |
| 1449 | |
| 1450 | static u32 krait_get_pmresrn_event(unsigned int region) |
| 1451 | { |
| 1452 | static const u32 pmresrn_table[] = { KRAIT_PMRESR0_GROUP0, |
| 1453 | KRAIT_PMRESR1_GROUP0, |
| 1454 | KRAIT_PMRESR2_GROUP0 }; |
| 1455 | return pmresrn_table[region]; |
| 1456 | } |
| 1457 | |
| 1458 | static void krait_evt_setup(int idx, u32 config_base) |
| 1459 | { |
| 1460 | u32 val; |
| 1461 | u32 mask; |
| 1462 | u32 vval, fval; |
Stephen Boyd | 65bab45 | 2015-02-28 00:11:33 +0000 | [diff] [blame] | 1463 | unsigned int region = EVENT_REGION(config_base); |
| 1464 | unsigned int group = EVENT_GROUP(config_base); |
| 1465 | unsigned int code = EVENT_CODE(config_base); |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1466 | unsigned int group_shift; |
Stephen Boyd | 65bab45 | 2015-02-28 00:11:33 +0000 | [diff] [blame] | 1467 | bool venum_event = EVENT_VENUM(config_base); |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1468 | |
| 1469 | group_shift = group * 8; |
| 1470 | mask = 0xff << group_shift; |
| 1471 | |
| 1472 | /* Configure evtsel for the region and group */ |
| 1473 | if (venum_event) |
| 1474 | val = KRAIT_VPMRESR0_GROUP0; |
| 1475 | else |
| 1476 | val = krait_get_pmresrn_event(region); |
| 1477 | val += group; |
| 1478 | /* Mix in mode-exclusion bits */ |
| 1479 | val |= config_base & (ARMV7_EXCLUDE_USER | ARMV7_EXCLUDE_PL1); |
| 1480 | armv7_pmnc_write_evtsel(idx, val); |
| 1481 | |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1482 | if (venum_event) { |
Stephen Boyd | 65bab45 | 2015-02-28 00:11:33 +0000 | [diff] [blame] | 1483 | venum_pre_pmresr(&vval, &fval); |
| 1484 | val = venum_read_pmresr(); |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1485 | val &= ~mask; |
| 1486 | val |= code << group_shift; |
| 1487 | val |= PMRESRn_EN; |
Stephen Boyd | 65bab45 | 2015-02-28 00:11:33 +0000 | [diff] [blame] | 1488 | venum_write_pmresr(val); |
| 1489 | venum_post_pmresr(vval, fval); |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1490 | } else { |
| 1491 | val = krait_read_pmresrn(region); |
| 1492 | val &= ~mask; |
| 1493 | val |= code << group_shift; |
| 1494 | val |= PMRESRn_EN; |
| 1495 | krait_write_pmresrn(region, val); |
| 1496 | } |
| 1497 | } |
| 1498 | |
Stephen Boyd | 65bab45 | 2015-02-28 00:11:33 +0000 | [diff] [blame] | 1499 | static u32 clear_pmresrn_group(u32 val, int group) |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1500 | { |
| 1501 | u32 mask; |
| 1502 | int group_shift; |
| 1503 | |
| 1504 | group_shift = group * 8; |
| 1505 | mask = 0xff << group_shift; |
| 1506 | val &= ~mask; |
| 1507 | |
| 1508 | /* Don't clear enable bit if entire region isn't disabled */ |
| 1509 | if (val & ~PMRESRn_EN) |
| 1510 | return val |= PMRESRn_EN; |
| 1511 | |
| 1512 | return 0; |
| 1513 | } |
| 1514 | |
| 1515 | static void krait_clearpmu(u32 config_base) |
| 1516 | { |
| 1517 | u32 val; |
| 1518 | u32 vval, fval; |
Stephen Boyd | 65bab45 | 2015-02-28 00:11:33 +0000 | [diff] [blame] | 1519 | unsigned int region = EVENT_REGION(config_base); |
| 1520 | unsigned int group = EVENT_GROUP(config_base); |
| 1521 | bool venum_event = EVENT_VENUM(config_base); |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1522 | |
| 1523 | if (venum_event) { |
Stephen Boyd | 65bab45 | 2015-02-28 00:11:33 +0000 | [diff] [blame] | 1524 | venum_pre_pmresr(&vval, &fval); |
| 1525 | val = venum_read_pmresr(); |
| 1526 | val = clear_pmresrn_group(val, group); |
| 1527 | venum_write_pmresr(val); |
| 1528 | venum_post_pmresr(vval, fval); |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1529 | } else { |
| 1530 | val = krait_read_pmresrn(region); |
Stephen Boyd | 65bab45 | 2015-02-28 00:11:33 +0000 | [diff] [blame] | 1531 | val = clear_pmresrn_group(val, group); |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1532 | krait_write_pmresrn(region, val); |
| 1533 | } |
| 1534 | } |
| 1535 | |
| 1536 | static void krait_pmu_disable_event(struct perf_event *event) |
| 1537 | { |
| 1538 | unsigned long flags; |
| 1539 | struct hw_perf_event *hwc = &event->hw; |
| 1540 | int idx = hwc->idx; |
Mark Rutland | 037e79a | 2014-05-21 18:06:13 +0100 | [diff] [blame] | 1541 | struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); |
Mark Rutland | 1167925 | 2014-05-13 19:36:31 +0100 | [diff] [blame] | 1542 | struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events); |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1543 | |
| 1544 | /* Disable counter and interrupt */ |
| 1545 | raw_spin_lock_irqsave(&events->pmu_lock, flags); |
| 1546 | |
| 1547 | /* Disable counter */ |
| 1548 | armv7_pmnc_disable_counter(idx); |
| 1549 | |
| 1550 | /* |
| 1551 | * Clear pmresr code (if destined for PMNx counters) |
| 1552 | */ |
| 1553 | if (hwc->config_base & KRAIT_EVENT_MASK) |
| 1554 | krait_clearpmu(hwc->config_base); |
| 1555 | |
| 1556 | /* Disable interrupt for this counter */ |
| 1557 | armv7_pmnc_disable_intens(idx); |
| 1558 | |
| 1559 | raw_spin_unlock_irqrestore(&events->pmu_lock, flags); |
| 1560 | } |
| 1561 | |
| 1562 | static void krait_pmu_enable_event(struct perf_event *event) |
| 1563 | { |
| 1564 | unsigned long flags; |
| 1565 | struct hw_perf_event *hwc = &event->hw; |
| 1566 | int idx = hwc->idx; |
Mark Rutland | 037e79a | 2014-05-21 18:06:13 +0100 | [diff] [blame] | 1567 | struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); |
Mark Rutland | 1167925 | 2014-05-13 19:36:31 +0100 | [diff] [blame] | 1568 | struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events); |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1569 | |
| 1570 | /* |
| 1571 | * Enable counter and interrupt, and set the counter to count |
| 1572 | * the event that we're interested in. |
| 1573 | */ |
| 1574 | raw_spin_lock_irqsave(&events->pmu_lock, flags); |
| 1575 | |
| 1576 | /* Disable counter */ |
| 1577 | armv7_pmnc_disable_counter(idx); |
| 1578 | |
| 1579 | /* |
| 1580 | * Set event (if destined for PMNx counters) |
| 1581 | * We set the event for the cycle counter because we |
| 1582 | * have the ability to perform event filtering. |
| 1583 | */ |
| 1584 | if (hwc->config_base & KRAIT_EVENT_MASK) |
| 1585 | krait_evt_setup(idx, hwc->config_base); |
| 1586 | else |
| 1587 | armv7_pmnc_write_evtsel(idx, hwc->config_base); |
| 1588 | |
| 1589 | /* Enable interrupt for this counter */ |
| 1590 | armv7_pmnc_enable_intens(idx); |
| 1591 | |
| 1592 | /* Enable counter */ |
| 1593 | armv7_pmnc_enable_counter(idx); |
| 1594 | |
| 1595 | raw_spin_unlock_irqrestore(&events->pmu_lock, flags); |
| 1596 | } |
| 1597 | |
| 1598 | static void krait_pmu_reset(void *info) |
| 1599 | { |
| 1600 | u32 vval, fval; |
Stephen Boyd | 9349991 | 2015-02-28 00:11:34 +0000 | [diff] [blame] | 1601 | struct arm_pmu *cpu_pmu = info; |
| 1602 | u32 idx, nb_cnt = cpu_pmu->num_events; |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1603 | |
| 1604 | armv7pmu_reset(info); |
| 1605 | |
| 1606 | /* Clear all pmresrs */ |
| 1607 | krait_write_pmresrn(0, 0); |
| 1608 | krait_write_pmresrn(1, 0); |
| 1609 | krait_write_pmresrn(2, 0); |
| 1610 | |
Stephen Boyd | 65bab45 | 2015-02-28 00:11:33 +0000 | [diff] [blame] | 1611 | venum_pre_pmresr(&vval, &fval); |
| 1612 | venum_write_pmresr(0); |
| 1613 | venum_post_pmresr(vval, fval); |
Stephen Boyd | 9349991 | 2015-02-28 00:11:34 +0000 | [diff] [blame] | 1614 | |
| 1615 | /* Reset PMxEVNCTCR to sane default */ |
| 1616 | for (idx = ARMV7_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) { |
| 1617 | armv7_pmnc_select_counter(idx); |
| 1618 | asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); |
| 1619 | } |
| 1620 | |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1621 | } |
| 1622 | |
| 1623 | static int krait_event_to_bit(struct perf_event *event, unsigned int region, |
| 1624 | unsigned int group) |
| 1625 | { |
| 1626 | int bit; |
| 1627 | struct hw_perf_event *hwc = &event->hw; |
| 1628 | struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); |
| 1629 | |
| 1630 | if (hwc->config_base & VENUM_EVENT) |
| 1631 | bit = KRAIT_VPMRESR0_GROUP0; |
| 1632 | else |
| 1633 | bit = krait_get_pmresrn_event(region); |
| 1634 | bit -= krait_get_pmresrn_event(0); |
| 1635 | bit += group; |
| 1636 | /* |
| 1637 | * Lower bits are reserved for use by the counters (see |
| 1638 | * armv7pmu_get_event_idx() for more info) |
| 1639 | */ |
| 1640 | bit += ARMV7_IDX_COUNTER_LAST(cpu_pmu) + 1; |
| 1641 | |
| 1642 | return bit; |
| 1643 | } |
| 1644 | |
| 1645 | /* |
| 1646 | * We check for column exclusion constraints here. |
| 1647 | * Two events cant use the same group within a pmresr register. |
| 1648 | */ |
| 1649 | static int krait_pmu_get_event_idx(struct pmu_hw_events *cpuc, |
| 1650 | struct perf_event *event) |
| 1651 | { |
| 1652 | int idx; |
Russell King | 6a78371 | 2014-06-19 10:39:41 +0100 | [diff] [blame] | 1653 | int bit = -1; |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1654 | struct hw_perf_event *hwc = &event->hw; |
Stephen Boyd | 65bab45 | 2015-02-28 00:11:33 +0000 | [diff] [blame] | 1655 | unsigned int region = EVENT_REGION(hwc->config_base); |
| 1656 | unsigned int code = EVENT_CODE(hwc->config_base); |
| 1657 | unsigned int group = EVENT_GROUP(hwc->config_base); |
| 1658 | bool venum_event = EVENT_VENUM(hwc->config_base); |
| 1659 | bool krait_event = EVENT_CPU(hwc->config_base); |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1660 | |
Stephen Boyd | 65bab45 | 2015-02-28 00:11:33 +0000 | [diff] [blame] | 1661 | if (venum_event || krait_event) { |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1662 | /* Ignore invalid events */ |
| 1663 | if (group > 3 || region > 2) |
| 1664 | return -EINVAL; |
Stephen Boyd | 65bab45 | 2015-02-28 00:11:33 +0000 | [diff] [blame] | 1665 | if (venum_event && (code & 0xe0)) |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1666 | return -EINVAL; |
| 1667 | |
| 1668 | bit = krait_event_to_bit(event, region, group); |
| 1669 | if (test_and_set_bit(bit, cpuc->used_mask)) |
| 1670 | return -EAGAIN; |
| 1671 | } |
| 1672 | |
| 1673 | idx = armv7pmu_get_event_idx(cpuc, event); |
Russell King | 6a78371 | 2014-06-19 10:39:41 +0100 | [diff] [blame] | 1674 | if (idx < 0 && bit >= 0) |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1675 | clear_bit(bit, cpuc->used_mask); |
| 1676 | |
| 1677 | return idx; |
| 1678 | } |
| 1679 | |
| 1680 | static void krait_pmu_clear_event_idx(struct pmu_hw_events *cpuc, |
| 1681 | struct perf_event *event) |
| 1682 | { |
| 1683 | int bit; |
| 1684 | struct hw_perf_event *hwc = &event->hw; |
Stephen Boyd | 65bab45 | 2015-02-28 00:11:33 +0000 | [diff] [blame] | 1685 | unsigned int region = EVENT_REGION(hwc->config_base); |
| 1686 | unsigned int group = EVENT_GROUP(hwc->config_base); |
| 1687 | bool venum_event = EVENT_VENUM(hwc->config_base); |
| 1688 | bool krait_event = EVENT_CPU(hwc->config_base); |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1689 | |
Stephen Boyd | 65bab45 | 2015-02-28 00:11:33 +0000 | [diff] [blame] | 1690 | if (venum_event || krait_event) { |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1691 | bit = krait_event_to_bit(event, region, group); |
| 1692 | clear_bit(bit, cpuc->used_mask); |
| 1693 | } |
| 1694 | } |
| 1695 | |
Stephen Boyd | 2a3391c | 2014-02-07 21:01:21 +0000 | [diff] [blame] | 1696 | static int krait_pmu_init(struct arm_pmu *cpu_pmu) |
| 1697 | { |
| 1698 | armv7pmu_init(cpu_pmu); |
Mark Rutland | 3d1ff75 | 2012-12-19 16:33:24 +0000 | [diff] [blame] | 1699 | cpu_pmu->name = "armv7_krait"; |
Stephen Boyd | 2a3391c | 2014-02-07 21:01:21 +0000 | [diff] [blame] | 1700 | /* Some early versions of Krait don't support PC write events */ |
| 1701 | if (of_property_read_bool(cpu_pmu->plat_device->dev.of_node, |
| 1702 | "qcom,no-pc-write")) |
| 1703 | cpu_pmu->map_event = krait_map_event_no_branch; |
| 1704 | else |
| 1705 | cpu_pmu->map_event = krait_map_event; |
Stephen Boyd | 2a3391c | 2014-02-07 21:01:21 +0000 | [diff] [blame] | 1706 | cpu_pmu->set_event_filter = armv7pmu_set_event_filter; |
Stephen Boyd | b7aafe9 | 2014-02-07 13:01:23 -0800 | [diff] [blame] | 1707 | cpu_pmu->reset = krait_pmu_reset; |
| 1708 | cpu_pmu->enable = krait_pmu_enable_event; |
| 1709 | cpu_pmu->disable = krait_pmu_disable_event; |
| 1710 | cpu_pmu->get_event_idx = krait_pmu_get_event_idx; |
| 1711 | cpu_pmu->clear_event_idx = krait_pmu_clear_event_idx; |
Raghavendra Rao Ananta | 31ff143 | 2018-05-09 19:49:48 -0700 | [diff] [blame] | 1712 | return armv7_probe_pmu(cpu_pmu); |
Stephen Boyd | 2a3391c | 2014-02-07 21:01:21 +0000 | [diff] [blame] | 1713 | } |
Stephen Boyd | 341e42c | 2015-02-27 16:11:35 -0800 | [diff] [blame] | 1714 | |
| 1715 | /* |
| 1716 | * Scorpion Local Performance Monitor Register (LPMn) |
| 1717 | * |
| 1718 | * 31 30 24 16 8 0 |
| 1719 | * +--------------------------------+ |
| 1720 | * LPM0 | EN | CC | CC | CC | CC | N = 1, R = 0 |
| 1721 | * +--------------------------------+ |
| 1722 | * LPM1 | EN | CC | CC | CC | CC | N = 1, R = 1 |
| 1723 | * +--------------------------------+ |
| 1724 | * LPM2 | EN | CC | CC | CC | CC | N = 1, R = 2 |
| 1725 | * +--------------------------------+ |
| 1726 | * L2LPM | EN | CC | CC | CC | CC | N = 1, R = 3 |
| 1727 | * +--------------------------------+ |
| 1728 | * VLPM | EN | CC | CC | CC | CC | N = 2, R = ? |
| 1729 | * +--------------------------------+ |
| 1730 | * EN | G=3 | G=2 | G=1 | G=0 |
| 1731 | * |
| 1732 | * |
| 1733 | * Event Encoding: |
| 1734 | * |
| 1735 | * hwc->config_base = 0xNRCCG |
| 1736 | * |
| 1737 | * N = prefix, 1 for Scorpion CPU (LPMn/L2LPM), 2 for Venum VFP (VLPM) |
| 1738 | * R = region register |
| 1739 | * CC = class of events the group G is choosing from |
| 1740 | * G = group or particular event |
| 1741 | * |
| 1742 | * Example: 0x12021 is a Scorpion CPU event in LPM2's group 1 with code 2 |
| 1743 | * |
| 1744 | * A region (R) corresponds to a piece of the CPU (execution unit, instruction |
| 1745 | * unit, etc.) while the event code (CC) corresponds to a particular class of |
| 1746 | * events (interrupts for example). An event code is broken down into |
| 1747 | * groups (G) that can be mapped into the PMU (irq, fiqs, and irq+fiqs for |
| 1748 | * example). |
| 1749 | */ |
| 1750 | |
| 1751 | static u32 scorpion_read_pmresrn(int n) |
| 1752 | { |
| 1753 | u32 val; |
| 1754 | |
| 1755 | switch (n) { |
| 1756 | case 0: |
| 1757 | asm volatile("mrc p15, 0, %0, c15, c0, 0" : "=r" (val)); |
| 1758 | break; |
| 1759 | case 1: |
| 1760 | asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r" (val)); |
| 1761 | break; |
| 1762 | case 2: |
| 1763 | asm volatile("mrc p15, 2, %0, c15, c0, 0" : "=r" (val)); |
| 1764 | break; |
| 1765 | case 3: |
| 1766 | asm volatile("mrc p15, 3, %0, c15, c2, 0" : "=r" (val)); |
| 1767 | break; |
| 1768 | default: |
| 1769 | BUG(); /* Should be validated in scorpion_pmu_get_event_idx() */ |
| 1770 | } |
| 1771 | |
| 1772 | return val; |
| 1773 | } |
| 1774 | |
| 1775 | static void scorpion_write_pmresrn(int n, u32 val) |
| 1776 | { |
| 1777 | switch (n) { |
| 1778 | case 0: |
| 1779 | asm volatile("mcr p15, 0, %0, c15, c0, 0" : : "r" (val)); |
| 1780 | break; |
| 1781 | case 1: |
| 1782 | asm volatile("mcr p15, 1, %0, c15, c0, 0" : : "r" (val)); |
| 1783 | break; |
| 1784 | case 2: |
| 1785 | asm volatile("mcr p15, 2, %0, c15, c0, 0" : : "r" (val)); |
| 1786 | break; |
| 1787 | case 3: |
| 1788 | asm volatile("mcr p15, 3, %0, c15, c2, 0" : : "r" (val)); |
| 1789 | break; |
| 1790 | default: |
| 1791 | BUG(); /* Should be validated in scorpion_pmu_get_event_idx() */ |
| 1792 | } |
| 1793 | } |
| 1794 | |
| 1795 | static u32 scorpion_get_pmresrn_event(unsigned int region) |
| 1796 | { |
| 1797 | static const u32 pmresrn_table[] = { SCORPION_LPM0_GROUP0, |
| 1798 | SCORPION_LPM1_GROUP0, |
| 1799 | SCORPION_LPM2_GROUP0, |
| 1800 | SCORPION_L2LPM_GROUP0 }; |
| 1801 | return pmresrn_table[region]; |
| 1802 | } |
| 1803 | |
| 1804 | static void scorpion_evt_setup(int idx, u32 config_base) |
| 1805 | { |
| 1806 | u32 val; |
| 1807 | u32 mask; |
| 1808 | u32 vval, fval; |
| 1809 | unsigned int region = EVENT_REGION(config_base); |
| 1810 | unsigned int group = EVENT_GROUP(config_base); |
| 1811 | unsigned int code = EVENT_CODE(config_base); |
| 1812 | unsigned int group_shift; |
| 1813 | bool venum_event = EVENT_VENUM(config_base); |
| 1814 | |
| 1815 | group_shift = group * 8; |
| 1816 | mask = 0xff << group_shift; |
| 1817 | |
| 1818 | /* Configure evtsel for the region and group */ |
| 1819 | if (venum_event) |
| 1820 | val = SCORPION_VLPM_GROUP0; |
| 1821 | else |
| 1822 | val = scorpion_get_pmresrn_event(region); |
| 1823 | val += group; |
| 1824 | /* Mix in mode-exclusion bits */ |
| 1825 | val |= config_base & (ARMV7_EXCLUDE_USER | ARMV7_EXCLUDE_PL1); |
| 1826 | armv7_pmnc_write_evtsel(idx, val); |
| 1827 | |
| 1828 | asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); |
| 1829 | |
| 1830 | if (venum_event) { |
| 1831 | venum_pre_pmresr(&vval, &fval); |
| 1832 | val = venum_read_pmresr(); |
| 1833 | val &= ~mask; |
| 1834 | val |= code << group_shift; |
| 1835 | val |= PMRESRn_EN; |
| 1836 | venum_write_pmresr(val); |
| 1837 | venum_post_pmresr(vval, fval); |
| 1838 | } else { |
| 1839 | val = scorpion_read_pmresrn(region); |
| 1840 | val &= ~mask; |
| 1841 | val |= code << group_shift; |
| 1842 | val |= PMRESRn_EN; |
| 1843 | scorpion_write_pmresrn(region, val); |
| 1844 | } |
| 1845 | } |
| 1846 | |
| 1847 | static void scorpion_clearpmu(u32 config_base) |
| 1848 | { |
| 1849 | u32 val; |
| 1850 | u32 vval, fval; |
| 1851 | unsigned int region = EVENT_REGION(config_base); |
| 1852 | unsigned int group = EVENT_GROUP(config_base); |
| 1853 | bool venum_event = EVENT_VENUM(config_base); |
| 1854 | |
| 1855 | if (venum_event) { |
| 1856 | venum_pre_pmresr(&vval, &fval); |
| 1857 | val = venum_read_pmresr(); |
| 1858 | val = clear_pmresrn_group(val, group); |
| 1859 | venum_write_pmresr(val); |
| 1860 | venum_post_pmresr(vval, fval); |
| 1861 | } else { |
| 1862 | val = scorpion_read_pmresrn(region); |
| 1863 | val = clear_pmresrn_group(val, group); |
| 1864 | scorpion_write_pmresrn(region, val); |
| 1865 | } |
| 1866 | } |
| 1867 | |
| 1868 | static void scorpion_pmu_disable_event(struct perf_event *event) |
| 1869 | { |
| 1870 | unsigned long flags; |
| 1871 | struct hw_perf_event *hwc = &event->hw; |
| 1872 | int idx = hwc->idx; |
| 1873 | struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); |
| 1874 | struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events); |
| 1875 | |
| 1876 | /* Disable counter and interrupt */ |
| 1877 | raw_spin_lock_irqsave(&events->pmu_lock, flags); |
| 1878 | |
| 1879 | /* Disable counter */ |
| 1880 | armv7_pmnc_disable_counter(idx); |
| 1881 | |
| 1882 | /* |
| 1883 | * Clear pmresr code (if destined for PMNx counters) |
| 1884 | */ |
| 1885 | if (hwc->config_base & KRAIT_EVENT_MASK) |
| 1886 | scorpion_clearpmu(hwc->config_base); |
| 1887 | |
| 1888 | /* Disable interrupt for this counter */ |
| 1889 | armv7_pmnc_disable_intens(idx); |
| 1890 | |
| 1891 | raw_spin_unlock_irqrestore(&events->pmu_lock, flags); |
| 1892 | } |
| 1893 | |
| 1894 | static void scorpion_pmu_enable_event(struct perf_event *event) |
| 1895 | { |
| 1896 | unsigned long flags; |
| 1897 | struct hw_perf_event *hwc = &event->hw; |
| 1898 | int idx = hwc->idx; |
| 1899 | struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); |
| 1900 | struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events); |
| 1901 | |
| 1902 | /* |
| 1903 | * Enable counter and interrupt, and set the counter to count |
| 1904 | * the event that we're interested in. |
| 1905 | */ |
| 1906 | raw_spin_lock_irqsave(&events->pmu_lock, flags); |
| 1907 | |
| 1908 | /* Disable counter */ |
| 1909 | armv7_pmnc_disable_counter(idx); |
| 1910 | |
| 1911 | /* |
| 1912 | * Set event (if destined for PMNx counters) |
| 1913 | * We don't set the event for the cycle counter because we |
| 1914 | * don't have the ability to perform event filtering. |
| 1915 | */ |
| 1916 | if (hwc->config_base & KRAIT_EVENT_MASK) |
| 1917 | scorpion_evt_setup(idx, hwc->config_base); |
| 1918 | else if (idx != ARMV7_IDX_CYCLE_COUNTER) |
| 1919 | armv7_pmnc_write_evtsel(idx, hwc->config_base); |
| 1920 | |
| 1921 | /* Enable interrupt for this counter */ |
| 1922 | armv7_pmnc_enable_intens(idx); |
| 1923 | |
| 1924 | /* Enable counter */ |
| 1925 | armv7_pmnc_enable_counter(idx); |
| 1926 | |
| 1927 | raw_spin_unlock_irqrestore(&events->pmu_lock, flags); |
| 1928 | } |
| 1929 | |
| 1930 | static void scorpion_pmu_reset(void *info) |
| 1931 | { |
| 1932 | u32 vval, fval; |
| 1933 | struct arm_pmu *cpu_pmu = info; |
| 1934 | u32 idx, nb_cnt = cpu_pmu->num_events; |
| 1935 | |
| 1936 | armv7pmu_reset(info); |
| 1937 | |
| 1938 | /* Clear all pmresrs */ |
| 1939 | scorpion_write_pmresrn(0, 0); |
| 1940 | scorpion_write_pmresrn(1, 0); |
| 1941 | scorpion_write_pmresrn(2, 0); |
| 1942 | scorpion_write_pmresrn(3, 0); |
| 1943 | |
| 1944 | venum_pre_pmresr(&vval, &fval); |
| 1945 | venum_write_pmresr(0); |
| 1946 | venum_post_pmresr(vval, fval); |
| 1947 | |
| 1948 | /* Reset PMxEVNCTCR to sane default */ |
| 1949 | for (idx = ARMV7_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) { |
| 1950 | armv7_pmnc_select_counter(idx); |
| 1951 | asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); |
| 1952 | } |
| 1953 | } |
| 1954 | |
| 1955 | static int scorpion_event_to_bit(struct perf_event *event, unsigned int region, |
| 1956 | unsigned int group) |
| 1957 | { |
| 1958 | int bit; |
| 1959 | struct hw_perf_event *hwc = &event->hw; |
| 1960 | struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); |
| 1961 | |
| 1962 | if (hwc->config_base & VENUM_EVENT) |
| 1963 | bit = SCORPION_VLPM_GROUP0; |
| 1964 | else |
| 1965 | bit = scorpion_get_pmresrn_event(region); |
| 1966 | bit -= scorpion_get_pmresrn_event(0); |
| 1967 | bit += group; |
| 1968 | /* |
| 1969 | * Lower bits are reserved for use by the counters (see |
| 1970 | * armv7pmu_get_event_idx() for more info) |
| 1971 | */ |
| 1972 | bit += ARMV7_IDX_COUNTER_LAST(cpu_pmu) + 1; |
| 1973 | |
| 1974 | return bit; |
| 1975 | } |
| 1976 | |
| 1977 | /* |
| 1978 | * We check for column exclusion constraints here. |
| 1979 | * Two events cant use the same group within a pmresr register. |
| 1980 | */ |
| 1981 | static int scorpion_pmu_get_event_idx(struct pmu_hw_events *cpuc, |
| 1982 | struct perf_event *event) |
| 1983 | { |
| 1984 | int idx; |
| 1985 | int bit = -1; |
| 1986 | struct hw_perf_event *hwc = &event->hw; |
| 1987 | unsigned int region = EVENT_REGION(hwc->config_base); |
| 1988 | unsigned int group = EVENT_GROUP(hwc->config_base); |
| 1989 | bool venum_event = EVENT_VENUM(hwc->config_base); |
| 1990 | bool scorpion_event = EVENT_CPU(hwc->config_base); |
| 1991 | |
| 1992 | if (venum_event || scorpion_event) { |
| 1993 | /* Ignore invalid events */ |
| 1994 | if (group > 3 || region > 3) |
| 1995 | return -EINVAL; |
| 1996 | |
| 1997 | bit = scorpion_event_to_bit(event, region, group); |
| 1998 | if (test_and_set_bit(bit, cpuc->used_mask)) |
| 1999 | return -EAGAIN; |
| 2000 | } |
| 2001 | |
| 2002 | idx = armv7pmu_get_event_idx(cpuc, event); |
| 2003 | if (idx < 0 && bit >= 0) |
| 2004 | clear_bit(bit, cpuc->used_mask); |
| 2005 | |
| 2006 | return idx; |
| 2007 | } |
| 2008 | |
| 2009 | static void scorpion_pmu_clear_event_idx(struct pmu_hw_events *cpuc, |
| 2010 | struct perf_event *event) |
| 2011 | { |
| 2012 | int bit; |
| 2013 | struct hw_perf_event *hwc = &event->hw; |
| 2014 | unsigned int region = EVENT_REGION(hwc->config_base); |
| 2015 | unsigned int group = EVENT_GROUP(hwc->config_base); |
| 2016 | bool venum_event = EVENT_VENUM(hwc->config_base); |
| 2017 | bool scorpion_event = EVENT_CPU(hwc->config_base); |
| 2018 | |
| 2019 | if (venum_event || scorpion_event) { |
| 2020 | bit = scorpion_event_to_bit(event, region, group); |
| 2021 | clear_bit(bit, cpuc->used_mask); |
| 2022 | } |
| 2023 | } |
| 2024 | |
| 2025 | static int scorpion_pmu_init(struct arm_pmu *cpu_pmu) |
| 2026 | { |
| 2027 | armv7pmu_init(cpu_pmu); |
| 2028 | cpu_pmu->name = "armv7_scorpion"; |
| 2029 | cpu_pmu->map_event = scorpion_map_event; |
Stephen Boyd | 341e42c | 2015-02-27 16:11:35 -0800 | [diff] [blame] | 2030 | cpu_pmu->reset = scorpion_pmu_reset; |
| 2031 | cpu_pmu->enable = scorpion_pmu_enable_event; |
| 2032 | cpu_pmu->disable = scorpion_pmu_disable_event; |
| 2033 | cpu_pmu->get_event_idx = scorpion_pmu_get_event_idx; |
| 2034 | cpu_pmu->clear_event_idx = scorpion_pmu_clear_event_idx; |
Raghavendra Rao Ananta | 31ff143 | 2018-05-09 19:49:48 -0700 | [diff] [blame] | 2035 | return armv7_probe_pmu(cpu_pmu); |
Stephen Boyd | 341e42c | 2015-02-27 16:11:35 -0800 | [diff] [blame] | 2036 | } |
| 2037 | |
| 2038 | static int scorpion_mp_pmu_init(struct arm_pmu *cpu_pmu) |
| 2039 | { |
| 2040 | armv7pmu_init(cpu_pmu); |
| 2041 | cpu_pmu->name = "armv7_scorpion_mp"; |
| 2042 | cpu_pmu->map_event = scorpion_map_event; |
Stephen Boyd | 341e42c | 2015-02-27 16:11:35 -0800 | [diff] [blame] | 2043 | cpu_pmu->reset = scorpion_pmu_reset; |
| 2044 | cpu_pmu->enable = scorpion_pmu_enable_event; |
| 2045 | cpu_pmu->disable = scorpion_pmu_disable_event; |
| 2046 | cpu_pmu->get_event_idx = scorpion_pmu_get_event_idx; |
| 2047 | cpu_pmu->clear_event_idx = scorpion_pmu_clear_event_idx; |
Raghavendra Rao Ananta | 31ff143 | 2018-05-09 19:49:48 -0700 | [diff] [blame] | 2048 | return armv7_probe_pmu(cpu_pmu); |
Stephen Boyd | 341e42c | 2015-02-27 16:11:35 -0800 | [diff] [blame] | 2049 | } |
Mark Rutland | 29ba0f3 | 2015-05-26 17:23:38 +0100 | [diff] [blame] | 2050 | |
| 2051 | static const struct of_device_id armv7_pmu_of_device_ids[] = { |
| 2052 | {.compatible = "arm,cortex-a17-pmu", .data = armv7_a17_pmu_init}, |
| 2053 | {.compatible = "arm,cortex-a15-pmu", .data = armv7_a15_pmu_init}, |
| 2054 | {.compatible = "arm,cortex-a12-pmu", .data = armv7_a12_pmu_init}, |
| 2055 | {.compatible = "arm,cortex-a9-pmu", .data = armv7_a9_pmu_init}, |
| 2056 | {.compatible = "arm,cortex-a8-pmu", .data = armv7_a8_pmu_init}, |
| 2057 | {.compatible = "arm,cortex-a7-pmu", .data = armv7_a7_pmu_init}, |
| 2058 | {.compatible = "arm,cortex-a5-pmu", .data = armv7_a5_pmu_init}, |
| 2059 | {.compatible = "qcom,krait-pmu", .data = krait_pmu_init}, |
| 2060 | {.compatible = "qcom,scorpion-pmu", .data = scorpion_pmu_init}, |
| 2061 | {.compatible = "qcom,scorpion-mp-pmu", .data = scorpion_mp_pmu_init}, |
blong | 9eb77b9 | 2018-06-20 17:33:16 +0800 | [diff] [blame] | 2062 | {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_pmu_init}, |
Mark Rutland | 29ba0f3 | 2015-05-26 17:23:38 +0100 | [diff] [blame] | 2063 | {}, |
| 2064 | }; |
| 2065 | |
| 2066 | static const struct pmu_probe_info armv7_pmu_probe_table[] = { |
| 2067 | ARM_PMU_PROBE(ARM_CPU_PART_CORTEX_A8, armv7_a8_pmu_init), |
| 2068 | ARM_PMU_PROBE(ARM_CPU_PART_CORTEX_A9, armv7_a9_pmu_init), |
| 2069 | { /* sentinel value */ } |
| 2070 | }; |
| 2071 | |
| 2072 | |
| 2073 | static int armv7_pmu_device_probe(struct platform_device *pdev) |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 2074 | { |
Raghavendra Rao Ananta | ad9b5da | 2018-05-23 16:58:49 -0700 | [diff] [blame] | 2075 | int ret; |
| 2076 | struct armv7_pmu_idle_nb *pmu_idle_nb; |
| 2077 | |
| 2078 | pmu_idle_nb = devm_kzalloc(&pdev->dev, sizeof(*pmu_idle_nb), |
| 2079 | GFP_KERNEL); |
| 2080 | if (!pmu_idle_nb) |
| 2081 | return -ENOMEM; |
| 2082 | |
| 2083 | ret = arm_pmu_device_probe(pdev, armv7_pmu_of_device_ids, |
Mark Rutland | 29ba0f3 | 2015-05-26 17:23:38 +0100 | [diff] [blame] | 2084 | armv7_pmu_probe_table); |
Raghavendra Rao Ananta | ad9b5da | 2018-05-23 16:58:49 -0700 | [diff] [blame] | 2085 | if (ret) |
| 2086 | return ret; |
| 2087 | |
| 2088 | pmu_idle_nb->cpu_pmu = (struct arm_pmu *) platform_get_drvdata(pdev); |
| 2089 | pmu_idle_nb->perf_cpu_idle_nb.notifier_call = armv7_pmu_idle_notifier; |
| 2090 | idle_notifier_register(&pmu_idle_nb->perf_cpu_idle_nb); |
| 2091 | |
| 2092 | return 0; |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 2093 | } |
| 2094 | |
Mark Rutland | 29ba0f3 | 2015-05-26 17:23:38 +0100 | [diff] [blame] | 2095 | static struct platform_driver armv7_pmu_driver = { |
| 2096 | .driver = { |
| 2097 | .name = "armv7-pmu", |
| 2098 | .of_match_table = armv7_pmu_of_device_ids, |
| 2099 | }, |
| 2100 | .probe = armv7_pmu_device_probe, |
| 2101 | }; |
Will Deacon | 0c205cb | 2011-06-03 17:40:15 +0100 | [diff] [blame] | 2102 | |
Mark Rutland | 29ba0f3 | 2015-05-26 17:23:38 +0100 | [diff] [blame] | 2103 | static int __init register_armv7_pmu_driver(void) |
Will Deacon | 0c205cb | 2011-06-03 17:40:15 +0100 | [diff] [blame] | 2104 | { |
Mark Rutland | 29ba0f3 | 2015-05-26 17:23:38 +0100 | [diff] [blame] | 2105 | return platform_driver_register(&armv7_pmu_driver); |
Will Deacon | 0c205cb | 2011-06-03 17:40:15 +0100 | [diff] [blame] | 2106 | } |
Mark Rutland | 29ba0f3 | 2015-05-26 17:23:38 +0100 | [diff] [blame] | 2107 | device_initcall(register_armv7_pmu_driver); |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 2108 | #endif /* CONFIG_CPU_V7 */ |