| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 1 | /* |
| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 2 | * This file is licensed under the terms of the GNU General Public |
| 3 | * License version 2. This program is licensed "as is" without any |
| 4 | * warranty of any kind, whether express or implied. |
| 5 | */ |
| 6 | |
| 7 | #ifndef __ASM_ARCH_BRIDGE_REGS_H |
| 8 | #define __ASM_ARCH_BRIDGE_REGS_H |
| 9 | |
| Arnd Bergmann | 4c811b9 | 2015-12-02 22:27:06 +0100 | [diff] [blame] | 10 | #include "mv78xx0.h" |
| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 11 | |
| Thomas Petazzoni | 5ae9f5d | 2012-09-11 14:27:16 +0200 | [diff] [blame] | 12 | #define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) |
| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 13 | #define L2_WRITETHROUGH 0x00020000 |
| 14 | |
| Thomas Petazzoni | 5ae9f5d | 2012-09-11 14:27:16 +0200 | [diff] [blame] | 15 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) |
| Ezequiel Garcia | 868eb61 | 2014-02-10 20:00:25 -0300 | [diff] [blame] | 16 | #define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108) |
| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 17 | #define SOFT_RESET_OUT_EN 0x00000004 |
| 18 | |
| Thomas Petazzoni | 5ae9f5d | 2012-09-11 14:27:16 +0200 | [diff] [blame] | 19 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) |
| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 20 | #define SOFT_RESET 0x00000001 |
| 21 | |
| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 22 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) |
| 23 | |
| Thomas Petazzoni | 5ae9f5d | 2012-09-11 14:27:16 +0200 | [diff] [blame] | 24 | #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) |
| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 25 | #define IRQ_CAUSE_ERR_OFF 0x0000 |
| 26 | #define IRQ_CAUSE_LOW_OFF 0x0004 |
| 27 | #define IRQ_CAUSE_HIGH_OFF 0x0008 |
| 28 | #define IRQ_MASK_ERR_OFF 0x000c |
| 29 | #define IRQ_MASK_LOW_OFF 0x0010 |
| 30 | #define IRQ_MASK_HIGH_OFF 0x0014 |
| 31 | |
| Thomas Petazzoni | 5ae9f5d | 2012-09-11 14:27:16 +0200 | [diff] [blame] | 32 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) |
| 33 | #define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) |
| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 34 | |
| 35 | #endif |