| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 1 | /* |
| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 2 | * Orion CPU Bridge Registers |
| 3 | * |
| 4 | * This file is licensed under the terms of the GNU General Public |
| 5 | * License version 2. This program is licensed "as is" without any |
| 6 | * warranty of any kind, whether express or implied. |
| 7 | */ |
| 8 | |
| 9 | #ifndef __ASM_ARCH_BRIDGE_REGS_H |
| 10 | #define __ASM_ARCH_BRIDGE_REGS_H |
| 11 | |
| Arnd Bergmann | c22c2c6 | 2015-12-02 22:27:08 +0100 | [diff] [blame] | 12 | #include "orion5x.h" |
| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 13 | |
| Thomas Petazzoni | 2332656 | 2012-09-11 14:27:17 +0200 | [diff] [blame] | 14 | #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100) |
| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 15 | |
| Thomas Petazzoni | 2332656 | 2012-09-11 14:27:17 +0200 | [diff] [blame] | 16 | #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104) |
| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 17 | |
| Thomas Petazzoni | 2332656 | 2012-09-11 14:27:17 +0200 | [diff] [blame] | 18 | #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108) |
| Ezequiel Garcia | 868eb61 | 2014-02-10 20:00:25 -0300 | [diff] [blame] | 19 | #define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108) |
| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 20 | |
| Thomas Petazzoni | 2332656 | 2012-09-11 14:27:17 +0200 | [diff] [blame] | 21 | #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c) |
| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 22 | |
| Thomas Petazzoni | 2332656 | 2012-09-11 14:27:17 +0200 | [diff] [blame] | 23 | #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110) |
| Lennert Buytenhek | 4ee1f6b | 2010-10-15 16:50:26 +0200 | [diff] [blame] | 24 | |
| Thomas Petazzoni | 2332656 | 2012-09-11 14:27:17 +0200 | [diff] [blame] | 25 | #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C) |
| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 26 | |
| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 27 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) |
| 28 | |
| Thomas Petazzoni | 2332656 | 2012-09-11 14:27:17 +0200 | [diff] [blame] | 29 | #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200) |
| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 30 | |
| Thomas Petazzoni | 2332656 | 2012-09-11 14:27:17 +0200 | [diff] [blame] | 31 | #define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204) |
| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 32 | |
| Thomas Petazzoni | 2332656 | 2012-09-11 14:27:17 +0200 | [diff] [blame] | 33 | #define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300) |
| 34 | #define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE + 0x300) |
| Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 35 | #endif |