Joseph Lo | 0b25e25 | 2012-10-31 17:41:15 +0800 | [diff] [blame] | 1 | /* |
| 2 | * CPU idle driver for Tegra CPUs |
| 3 | * |
| 4 | * Copyright (c) 2010-2012, NVIDIA Corporation. |
| 5 | * Copyright (c) 2011 Google, Inc. |
| 6 | * Author: Colin Cross <ccross@android.com> |
| 7 | * Gary King <gking@nvidia.com> |
| 8 | * |
| 9 | * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com> |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or |
| 14 | * (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 17 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 19 | * more details. |
| 20 | */ |
| 21 | |
Thierry Reding | a0524ac | 2014-07-11 09:44:49 +0200 | [diff] [blame] | 22 | #include <linux/clk/tegra.h> |
Thomas Gleixner | a0b4122 | 2015-04-03 02:32:14 +0200 | [diff] [blame] | 23 | #include <linux/tick.h> |
Joseph Lo | 0b25e25 | 2012-10-31 17:41:15 +0800 | [diff] [blame] | 24 | #include <linux/cpuidle.h> |
Joseph Lo | 5c1350b | 2013-01-15 22:10:38 +0000 | [diff] [blame] | 25 | #include <linux/cpu_pm.h> |
Thierry Reding | a0524ac | 2014-07-11 09:44:49 +0200 | [diff] [blame] | 26 | #include <linux/kernel.h> |
| 27 | #include <linux/module.h> |
Joseph Lo | 0b25e25 | 2012-10-31 17:41:15 +0800 | [diff] [blame] | 28 | |
| 29 | #include <asm/cpuidle.h> |
Joseph Lo | 5c1350b | 2013-01-15 22:10:38 +0000 | [diff] [blame] | 30 | #include <asm/smp_plat.h> |
Thierry Reding | a0524ac | 2014-07-11 09:44:49 +0200 | [diff] [blame] | 31 | #include <asm/suspend.h> |
Joseph Lo | 5c1350b | 2013-01-15 22:10:38 +0000 | [diff] [blame] | 32 | |
Thierry Reding | 755c47e | 2016-04-28 14:52:45 +0200 | [diff] [blame] | 33 | #include "cpuidle.h" |
Thierry Reding | a0524ac | 2014-07-11 09:44:49 +0200 | [diff] [blame] | 34 | #include "flowctrl.h" |
Joseph Lo | 1d32860 | 2013-01-16 17:33:55 +0000 | [diff] [blame] | 35 | #include "iomap.h" |
| 36 | #include "irq.h" |
Thierry Reding | a0524ac | 2014-07-11 09:44:49 +0200 | [diff] [blame] | 37 | #include "pm.h" |
Dmitry Osipenko | 4d48edb | 2015-01-15 13:58:57 +0300 | [diff] [blame] | 38 | #include "reset.h" |
Thierry Reding | a0524ac | 2014-07-11 09:44:49 +0200 | [diff] [blame] | 39 | #include "sleep.h" |
Joseph Lo | 5c1350b | 2013-01-15 22:10:38 +0000 | [diff] [blame] | 40 | |
| 41 | #ifdef CONFIG_PM_SLEEP |
Joseph Lo | 1d32860 | 2013-01-16 17:33:55 +0000 | [diff] [blame] | 42 | static bool abort_flag; |
| 43 | static atomic_t abort_barrier; |
| 44 | static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, |
| 45 | struct cpuidle_driver *drv, |
| 46 | int index); |
Daniel Lezcano | 14ad7a1 | 2013-04-03 12:15:17 +0000 | [diff] [blame] | 47 | #define TEGRA20_MAX_STATES 2 |
| 48 | #else |
| 49 | #define TEGRA20_MAX_STATES 1 |
Joseph Lo | 5c1350b | 2013-01-15 22:10:38 +0000 | [diff] [blame] | 50 | #endif |
| 51 | |
Joseph Lo | 0b25e25 | 2012-10-31 17:41:15 +0800 | [diff] [blame] | 52 | static struct cpuidle_driver tegra_idle_driver = { |
| 53 | .name = "tegra_idle", |
| 54 | .owner = THIS_MODULE, |
Daniel Lezcano | 14ad7a1 | 2013-04-03 12:15:17 +0000 | [diff] [blame] | 55 | .states = { |
| 56 | ARM_CPUIDLE_WFI_STATE_PWR(600), |
| 57 | #ifdef CONFIG_PM_SLEEP |
| 58 | { |
| 59 | .enter = tegra20_idle_lp2_coupled, |
| 60 | .exit_latency = 5000, |
| 61 | .target_residency = 10000, |
| 62 | .power_usage = 0, |
Daniel Lezcano | b82b6cc | 2014-11-12 16:03:50 +0100 | [diff] [blame] | 63 | .flags = CPUIDLE_FLAG_COUPLED, |
Daniel Lezcano | 14ad7a1 | 2013-04-03 12:15:17 +0000 | [diff] [blame] | 64 | .name = "powered-down", |
| 65 | .desc = "CPU power gated", |
| 66 | }, |
| 67 | #endif |
| 68 | }, |
| 69 | .state_count = TEGRA20_MAX_STATES, |
| 70 | .safe_state_index = 0, |
Joseph Lo | 0b25e25 | 2012-10-31 17:41:15 +0800 | [diff] [blame] | 71 | }; |
| 72 | |
Joseph Lo | 5c1350b | 2013-01-15 22:10:38 +0000 | [diff] [blame] | 73 | #ifdef CONFIG_PM_SLEEP |
| 74 | #ifdef CONFIG_SMP |
Joseph Lo | 1d32860 | 2013-01-16 17:33:55 +0000 | [diff] [blame] | 75 | static int tegra20_reset_sleeping_cpu_1(void) |
| 76 | { |
| 77 | int ret = 0; |
| 78 | |
| 79 | tegra_pen_lock(); |
| 80 | |
Dmitry Osipenko | 4d48edb | 2015-01-15 13:58:57 +0300 | [diff] [blame] | 81 | if (readb(tegra20_cpu1_resettable_status) == CPU_RESETTABLE) |
Joseph Lo | 1d32860 | 2013-01-16 17:33:55 +0000 | [diff] [blame] | 82 | tegra20_cpu_shutdown(1); |
| 83 | else |
| 84 | ret = -EINVAL; |
| 85 | |
| 86 | tegra_pen_unlock(); |
| 87 | |
| 88 | return ret; |
| 89 | } |
| 90 | |
| 91 | static void tegra20_wake_cpu1_from_reset(void) |
| 92 | { |
| 93 | tegra_pen_lock(); |
| 94 | |
| 95 | tegra20_cpu_clear_resettable(); |
| 96 | |
| 97 | /* enable cpu clock on cpu */ |
| 98 | tegra_enable_cpu_clock(1); |
| 99 | |
| 100 | /* take the CPU out of reset */ |
| 101 | tegra_cpu_out_of_reset(1); |
| 102 | |
| 103 | /* unhalt the cpu */ |
| 104 | flowctrl_write_cpu_halt(1, 0); |
| 105 | |
| 106 | tegra_pen_unlock(); |
| 107 | } |
| 108 | |
| 109 | static int tegra20_reset_cpu_1(void) |
| 110 | { |
| 111 | if (!cpu_online(1) || !tegra20_reset_sleeping_cpu_1()) |
| 112 | return 0; |
| 113 | |
| 114 | tegra20_wake_cpu1_from_reset(); |
| 115 | return -EBUSY; |
| 116 | } |
| 117 | #else |
| 118 | static inline void tegra20_wake_cpu1_from_reset(void) |
| 119 | { |
| 120 | } |
| 121 | |
| 122 | static inline int tegra20_reset_cpu_1(void) |
| 123 | { |
| 124 | return 0; |
| 125 | } |
| 126 | #endif |
| 127 | |
| 128 | static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev, |
| 129 | struct cpuidle_driver *drv, |
| 130 | int index) |
| 131 | { |
Joseph Lo | 1d32860 | 2013-01-16 17:33:55 +0000 | [diff] [blame] | 132 | while (tegra20_cpu_is_resettable_soon()) |
| 133 | cpu_relax(); |
| 134 | |
| 135 | if (tegra20_reset_cpu_1() || !tegra_cpu_rail_off_ready()) |
| 136 | return false; |
| 137 | |
Thomas Gleixner | a0b4122 | 2015-04-03 02:32:14 +0200 | [diff] [blame] | 138 | tick_broadcast_enter(); |
Joseph Lo | 1d32860 | 2013-01-16 17:33:55 +0000 | [diff] [blame] | 139 | |
Joseph Lo | 4d82d05 | 2013-04-02 01:20:50 +0000 | [diff] [blame] | 140 | tegra_idle_lp2_last(); |
Joseph Lo | 1d32860 | 2013-01-16 17:33:55 +0000 | [diff] [blame] | 141 | |
Thomas Gleixner | a0b4122 | 2015-04-03 02:32:14 +0200 | [diff] [blame] | 142 | tick_broadcast_exit(); |
Joseph Lo | 1d32860 | 2013-01-16 17:33:55 +0000 | [diff] [blame] | 143 | |
| 144 | if (cpu_online(1)) |
| 145 | tegra20_wake_cpu1_from_reset(); |
| 146 | |
| 147 | return true; |
| 148 | } |
| 149 | |
| 150 | #ifdef CONFIG_SMP |
Joseph Lo | 5c1350b | 2013-01-15 22:10:38 +0000 | [diff] [blame] | 151 | static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev, |
| 152 | struct cpuidle_driver *drv, |
| 153 | int index) |
| 154 | { |
Thomas Gleixner | a0b4122 | 2015-04-03 02:32:14 +0200 | [diff] [blame] | 155 | tick_broadcast_enter(); |
Joseph Lo | 5c1350b | 2013-01-15 22:10:38 +0000 | [diff] [blame] | 156 | |
| 157 | cpu_suspend(0, tegra20_sleep_cpu_secondary_finish); |
| 158 | |
| 159 | tegra20_cpu_clear_resettable(); |
| 160 | |
Thomas Gleixner | a0b4122 | 2015-04-03 02:32:14 +0200 | [diff] [blame] | 161 | tick_broadcast_exit(); |
Joseph Lo | 5c1350b | 2013-01-15 22:10:38 +0000 | [diff] [blame] | 162 | |
| 163 | return true; |
| 164 | } |
| 165 | #else |
| 166 | static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev, |
| 167 | struct cpuidle_driver *drv, |
| 168 | int index) |
| 169 | { |
| 170 | return true; |
| 171 | } |
| 172 | #endif |
| 173 | |
Joseph Lo | 1d32860 | 2013-01-16 17:33:55 +0000 | [diff] [blame] | 174 | static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, |
| 175 | struct cpuidle_driver *drv, |
| 176 | int index) |
Joseph Lo | 5c1350b | 2013-01-15 22:10:38 +0000 | [diff] [blame] | 177 | { |
Joseph Lo | 5c1350b | 2013-01-15 22:10:38 +0000 | [diff] [blame] | 178 | bool entered_lp2 = false; |
| 179 | |
Joseph Lo | 1d32860 | 2013-01-16 17:33:55 +0000 | [diff] [blame] | 180 | if (tegra_pending_sgi()) |
| 181 | ACCESS_ONCE(abort_flag) = true; |
| 182 | |
| 183 | cpuidle_coupled_parallel_barrier(dev, &abort_barrier); |
| 184 | |
| 185 | if (abort_flag) { |
| 186 | cpuidle_coupled_parallel_barrier(dev, &abort_barrier); |
| 187 | abort_flag = false; /* clean flag for next coming */ |
| 188 | return -EINTR; |
| 189 | } |
| 190 | |
Joseph Lo | 5c1350b | 2013-01-15 22:10:38 +0000 | [diff] [blame] | 191 | local_fiq_disable(); |
| 192 | |
Joseph Lo | 8f6a0b6 | 2013-06-04 18:47:35 +0800 | [diff] [blame] | 193 | tegra_set_cpu_in_lp2(); |
Joseph Lo | 5c1350b | 2013-01-15 22:10:38 +0000 | [diff] [blame] | 194 | cpu_pm_enter(); |
| 195 | |
Joseph Lo | 8f6a0b6 | 2013-06-04 18:47:35 +0800 | [diff] [blame] | 196 | if (dev->cpu == 0) |
Joseph Lo | 1d32860 | 2013-01-16 17:33:55 +0000 | [diff] [blame] | 197 | entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index); |
Joseph Lo | 5c1350b | 2013-01-15 22:10:38 +0000 | [diff] [blame] | 198 | else |
| 199 | entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index); |
| 200 | |
| 201 | cpu_pm_exit(); |
Joseph Lo | 8f6a0b6 | 2013-06-04 18:47:35 +0800 | [diff] [blame] | 202 | tegra_clear_cpu_in_lp2(); |
Joseph Lo | 5c1350b | 2013-01-15 22:10:38 +0000 | [diff] [blame] | 203 | |
| 204 | local_fiq_enable(); |
| 205 | |
| 206 | smp_rmb(); |
| 207 | |
| 208 | return entered_lp2 ? index : 0; |
| 209 | } |
| 210 | #endif |
| 211 | |
Stephen Warren | b4f1737 | 2013-05-06 14:19:19 -0600 | [diff] [blame] | 212 | /* |
| 213 | * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether |
| 214 | * they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around |
| 215 | * this, simply disable LP2 if the PCI driver and DT node are both enabled. |
| 216 | */ |
| 217 | void tegra20_cpuidle_pcie_irqs_in_use(void) |
| 218 | { |
| 219 | pr_info_once( |
| 220 | "Disabling cpuidle LP2 state, since PCIe IRQs are in use\n"); |
| 221 | tegra_idle_driver.states[1].disabled = true; |
| 222 | } |
| 223 | |
Joseph Lo | 0b25e25 | 2012-10-31 17:41:15 +0800 | [diff] [blame] | 224 | int __init tegra20_cpuidle_init(void) |
| 225 | { |
Daniel Lezcano | c5106c9 | 2013-04-23 08:54:40 +0000 | [diff] [blame] | 226 | return cpuidle_register(&tegra_idle_driver, cpu_possible_mask); |
Joseph Lo | 0b25e25 | 2012-10-31 17:41:15 +0800 | [diff] [blame] | 227 | } |