Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 1 | /* |
| 2 | * AArch64 loadable module support. |
| 3 | * |
| 4 | * Copyright (C) 2012 ARM Limited |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | * |
| 18 | * Author: Will Deacon <will.deacon@arm.com> |
| 19 | */ |
| 20 | |
| 21 | #include <linux/bitops.h> |
| 22 | #include <linux/elf.h> |
| 23 | #include <linux/gfp.h> |
Andrey Ryabinin | 39d114d | 2015-10-12 18:52:58 +0300 | [diff] [blame] | 24 | #include <linux/kasan.h> |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 25 | #include <linux/kernel.h> |
| 26 | #include <linux/mm.h> |
| 27 | #include <linux/moduleloader.h> |
| 28 | #include <linux/vmalloc.h> |
Paul Walmsley | 2c2b282 | 2015-01-05 17:38:41 -0700 | [diff] [blame] | 29 | #include <asm/alternative.h> |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 30 | #include <asm/insn.h> |
Andre Przywara | 932ded4 | 2014-11-28 13:40:45 +0000 | [diff] [blame] | 31 | #include <asm/sections.h> |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 32 | |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 33 | void *module_alloc(unsigned long size) |
| 34 | { |
Florian Fainelli | fd491d3 | 2017-04-27 11:19:02 -0700 | [diff] [blame] | 35 | gfp_t gfp_mask = GFP_KERNEL; |
Andrey Ryabinin | 39d114d | 2015-10-12 18:52:58 +0300 | [diff] [blame] | 36 | void *p; |
Ard Biesheuvel | dd86250 | 2019-06-25 19:08:54 +0200 | [diff] [blame] | 37 | u64 module_alloc_end = module_alloc_base + MODULES_VSIZE; |
| 38 | |
| 39 | if (IS_ENABLED(CONFIG_KASAN)) |
| 40 | /* don't exceed the static module region - see below */ |
| 41 | module_alloc_end = MODULES_END; |
Andrey Ryabinin | 39d114d | 2015-10-12 18:52:58 +0300 | [diff] [blame] | 42 | |
Florian Fainelli | fd491d3 | 2017-04-27 11:19:02 -0700 | [diff] [blame] | 43 | /* Silence the initial allocation */ |
| 44 | if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS)) |
| 45 | gfp_mask |= __GFP_NOWARN; |
| 46 | |
Ard Biesheuvel | f80fb3a | 2016-01-26 14:12:01 +0100 | [diff] [blame] | 47 | p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base, |
jianzhou | dd97575 | 2019-08-07 16:36:14 +0800 | [diff] [blame] | 48 | module_alloc_end, gfp_mask, PAGE_KERNEL_EXEC, 0, |
Andrey Ryabinin | 39d114d | 2015-10-12 18:52:58 +0300 | [diff] [blame] | 49 | NUMA_NO_NODE, __builtin_return_address(0)); |
| 50 | |
Ard Biesheuvel | fd045f6 | 2015-11-24 12:37:35 +0100 | [diff] [blame] | 51 | if (!p && IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) && |
| 52 | !IS_ENABLED(CONFIG_KASAN)) |
| 53 | /* |
| 54 | * KASAN can only deal with module allocations being served |
| 55 | * from the reserved module region, since the remainder of |
| 56 | * the vmalloc region is already backed by zero shadow pages, |
| 57 | * and punching holes into it is non-trivial. Since the module |
| 58 | * region is not randomized when KASAN is enabled, it is even |
| 59 | * less likely that the module region gets exhausted, so we |
| 60 | * can simply omit this fallback in that case. |
| 61 | */ |
| 62 | p = __vmalloc_node_range(size, MODULE_ALIGN, VMALLOC_START, |
| 63 | VMALLOC_END, GFP_KERNEL, PAGE_KERNEL_EXEC, 0, |
| 64 | NUMA_NO_NODE, __builtin_return_address(0)); |
| 65 | |
Andrey Ryabinin | 39d114d | 2015-10-12 18:52:58 +0300 | [diff] [blame] | 66 | if (p && (kasan_module_alloc(p, size) < 0)) { |
| 67 | vfree(p); |
| 68 | return NULL; |
| 69 | } |
| 70 | |
| 71 | return p; |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 72 | } |
| 73 | |
| 74 | enum aarch64_reloc_op { |
| 75 | RELOC_OP_NONE, |
| 76 | RELOC_OP_ABS, |
| 77 | RELOC_OP_PREL, |
| 78 | RELOC_OP_PAGE, |
| 79 | }; |
| 80 | |
| 81 | static u64 do_reloc(enum aarch64_reloc_op reloc_op, void *place, u64 val) |
| 82 | { |
| 83 | switch (reloc_op) { |
| 84 | case RELOC_OP_ABS: |
| 85 | return val; |
| 86 | case RELOC_OP_PREL: |
| 87 | return val - (u64)place; |
| 88 | case RELOC_OP_PAGE: |
| 89 | return (val & ~0xfff) - ((u64)place & ~0xfff); |
| 90 | case RELOC_OP_NONE: |
| 91 | return 0; |
| 92 | } |
| 93 | |
| 94 | pr_err("do_reloc: unknown relocation operation %d\n", reloc_op); |
| 95 | return 0; |
| 96 | } |
| 97 | |
| 98 | static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int len) |
| 99 | { |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 100 | s64 sval = do_reloc(op, place, val); |
| 101 | |
| 102 | switch (len) { |
| 103 | case 16: |
| 104 | *(s16 *)place = sval; |
Ard Biesheuvel | f930896 | 2016-01-05 10:18:52 +0100 | [diff] [blame] | 105 | if (sval < S16_MIN || sval > U16_MAX) |
| 106 | return -ERANGE; |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 107 | break; |
| 108 | case 32: |
| 109 | *(s32 *)place = sval; |
Ard Biesheuvel | f930896 | 2016-01-05 10:18:52 +0100 | [diff] [blame] | 110 | if (sval < S32_MIN || sval > U32_MAX) |
| 111 | return -ERANGE; |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 112 | break; |
| 113 | case 64: |
| 114 | *(s64 *)place = sval; |
| 115 | break; |
| 116 | default: |
| 117 | pr_err("Invalid length (%d) for data relocation\n", len); |
| 118 | return 0; |
| 119 | } |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 120 | return 0; |
| 121 | } |
| 122 | |
Ard Biesheuvel | b24a557 | 2016-01-05 10:18:51 +0100 | [diff] [blame] | 123 | enum aarch64_insn_movw_imm_type { |
| 124 | AARCH64_INSN_IMM_MOVNZ, |
| 125 | AARCH64_INSN_IMM_MOVKZ, |
| 126 | }; |
| 127 | |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 128 | static int reloc_insn_movw(enum aarch64_reloc_op op, void *place, u64 val, |
Ard Biesheuvel | b24a557 | 2016-01-05 10:18:51 +0100 | [diff] [blame] | 129 | int lsb, enum aarch64_insn_movw_imm_type imm_type) |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 130 | { |
Ard Biesheuvel | b24a557 | 2016-01-05 10:18:51 +0100 | [diff] [blame] | 131 | u64 imm; |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 132 | s64 sval; |
| 133 | u32 insn = le32_to_cpu(*(u32 *)place); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 134 | |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 135 | sval = do_reloc(op, place, val); |
Ard Biesheuvel | b24a557 | 2016-01-05 10:18:51 +0100 | [diff] [blame] | 136 | imm = sval >> lsb; |
Will Deacon | 122e2fa | 2013-11-05 10:16:52 +0000 | [diff] [blame] | 137 | |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 138 | if (imm_type == AARCH64_INSN_IMM_MOVNZ) { |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 139 | /* |
| 140 | * For signed MOVW relocations, we have to manipulate the |
| 141 | * instruction encoding depending on whether or not the |
| 142 | * immediate is less than zero. |
| 143 | */ |
| 144 | insn &= ~(3 << 29); |
Ard Biesheuvel | b24a557 | 2016-01-05 10:18:51 +0100 | [diff] [blame] | 145 | if (sval >= 0) { |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 146 | /* >=0: Set the instruction to MOVZ (opcode 10b). */ |
| 147 | insn |= 2 << 29; |
| 148 | } else { |
| 149 | /* |
| 150 | * <0: Set the instruction to MOVN (opcode 00b). |
| 151 | * Since we've masked the opcode already, we |
| 152 | * don't need to do anything other than |
| 153 | * inverting the new immediate field. |
| 154 | */ |
| 155 | imm = ~imm; |
| 156 | } |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 157 | } |
| 158 | |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 159 | /* Update the instruction with the new encoding. */ |
Ard Biesheuvel | b24a557 | 2016-01-05 10:18:51 +0100 | [diff] [blame] | 160 | insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm); |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 161 | *(u32 *)place = cpu_to_le32(insn); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 162 | |
Ard Biesheuvel | b24a557 | 2016-01-05 10:18:51 +0100 | [diff] [blame] | 163 | if (imm > U16_MAX) |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 164 | return -ERANGE; |
| 165 | |
| 166 | return 0; |
| 167 | } |
| 168 | |
| 169 | static int reloc_insn_imm(enum aarch64_reloc_op op, void *place, u64 val, |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 170 | int lsb, int len, enum aarch64_insn_imm_type imm_type) |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 171 | { |
| 172 | u64 imm, imm_mask; |
| 173 | s64 sval; |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 174 | u32 insn = le32_to_cpu(*(u32 *)place); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 175 | |
| 176 | /* Calculate the relocation value. */ |
| 177 | sval = do_reloc(op, place, val); |
| 178 | sval >>= lsb; |
| 179 | |
| 180 | /* Extract the value bits and shift them to bit 0. */ |
| 181 | imm_mask = (BIT(lsb + len) - 1) >> lsb; |
| 182 | imm = sval & imm_mask; |
| 183 | |
| 184 | /* Update the instruction's immediate field. */ |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 185 | insn = aarch64_insn_encode_immediate(imm_type, insn, imm); |
| 186 | *(u32 *)place = cpu_to_le32(insn); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 187 | |
| 188 | /* |
| 189 | * Extract the upper value bits (including the sign bit) and |
| 190 | * shift them to bit 0. |
| 191 | */ |
| 192 | sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1); |
| 193 | |
| 194 | /* |
| 195 | * Overflow has occurred if the upper bits are not all equal to |
| 196 | * the sign bit of the value. |
| 197 | */ |
| 198 | if ((u64)(sval + 1) >= 2) |
| 199 | return -ERANGE; |
| 200 | |
| 201 | return 0; |
| 202 | } |
| 203 | |
| 204 | int apply_relocate_add(Elf64_Shdr *sechdrs, |
| 205 | const char *strtab, |
| 206 | unsigned int symindex, |
| 207 | unsigned int relsec, |
| 208 | struct module *me) |
| 209 | { |
| 210 | unsigned int i; |
| 211 | int ovf; |
| 212 | bool overflow_check; |
| 213 | Elf64_Sym *sym; |
| 214 | void *loc; |
| 215 | u64 val; |
| 216 | Elf64_Rela *rel = (void *)sechdrs[relsec].sh_addr; |
| 217 | |
| 218 | for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { |
| 219 | /* loc corresponds to P in the AArch64 ELF document. */ |
| 220 | loc = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr |
| 221 | + rel[i].r_offset; |
| 222 | |
| 223 | /* sym is the ELF symbol we're referring to. */ |
| 224 | sym = (Elf64_Sym *)sechdrs[symindex].sh_addr |
| 225 | + ELF64_R_SYM(rel[i].r_info); |
| 226 | |
| 227 | /* val corresponds to (S + A) in the AArch64 ELF document. */ |
| 228 | val = sym->st_value + rel[i].r_addend; |
| 229 | |
| 230 | /* Check for overflow by default. */ |
| 231 | overflow_check = true; |
| 232 | |
| 233 | /* Perform the static relocation. */ |
| 234 | switch (ELF64_R_TYPE(rel[i].r_info)) { |
| 235 | /* Null relocations. */ |
| 236 | case R_ARM_NONE: |
| 237 | case R_AARCH64_NONE: |
| 238 | ovf = 0; |
| 239 | break; |
| 240 | |
| 241 | /* Data relocations. */ |
| 242 | case R_AARCH64_ABS64: |
| 243 | overflow_check = false; |
| 244 | ovf = reloc_data(RELOC_OP_ABS, loc, val, 64); |
| 245 | break; |
| 246 | case R_AARCH64_ABS32: |
| 247 | ovf = reloc_data(RELOC_OP_ABS, loc, val, 32); |
| 248 | break; |
| 249 | case R_AARCH64_ABS16: |
| 250 | ovf = reloc_data(RELOC_OP_ABS, loc, val, 16); |
| 251 | break; |
| 252 | case R_AARCH64_PREL64: |
| 253 | overflow_check = false; |
| 254 | ovf = reloc_data(RELOC_OP_PREL, loc, val, 64); |
| 255 | break; |
| 256 | case R_AARCH64_PREL32: |
| 257 | ovf = reloc_data(RELOC_OP_PREL, loc, val, 32); |
| 258 | break; |
| 259 | case R_AARCH64_PREL16: |
| 260 | ovf = reloc_data(RELOC_OP_PREL, loc, val, 16); |
| 261 | break; |
| 262 | |
| 263 | /* MOVW instruction relocations. */ |
| 264 | case R_AARCH64_MOVW_UABS_G0_NC: |
| 265 | overflow_check = false; |
| 266 | case R_AARCH64_MOVW_UABS_G0: |
| 267 | ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0, |
Ard Biesheuvel | b24a557 | 2016-01-05 10:18:51 +0100 | [diff] [blame] | 268 | AARCH64_INSN_IMM_MOVKZ); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 269 | break; |
| 270 | case R_AARCH64_MOVW_UABS_G1_NC: |
| 271 | overflow_check = false; |
| 272 | case R_AARCH64_MOVW_UABS_G1: |
| 273 | ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16, |
Ard Biesheuvel | b24a557 | 2016-01-05 10:18:51 +0100 | [diff] [blame] | 274 | AARCH64_INSN_IMM_MOVKZ); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 275 | break; |
| 276 | case R_AARCH64_MOVW_UABS_G2_NC: |
| 277 | overflow_check = false; |
| 278 | case R_AARCH64_MOVW_UABS_G2: |
| 279 | ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32, |
Ard Biesheuvel | b24a557 | 2016-01-05 10:18:51 +0100 | [diff] [blame] | 280 | AARCH64_INSN_IMM_MOVKZ); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 281 | break; |
| 282 | case R_AARCH64_MOVW_UABS_G3: |
| 283 | /* We're using the top bits so we can't overflow. */ |
| 284 | overflow_check = false; |
| 285 | ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 48, |
Ard Biesheuvel | b24a557 | 2016-01-05 10:18:51 +0100 | [diff] [blame] | 286 | AARCH64_INSN_IMM_MOVKZ); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 287 | break; |
| 288 | case R_AARCH64_MOVW_SABS_G0: |
| 289 | ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0, |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 290 | AARCH64_INSN_IMM_MOVNZ); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 291 | break; |
| 292 | case R_AARCH64_MOVW_SABS_G1: |
| 293 | ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16, |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 294 | AARCH64_INSN_IMM_MOVNZ); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 295 | break; |
| 296 | case R_AARCH64_MOVW_SABS_G2: |
| 297 | ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32, |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 298 | AARCH64_INSN_IMM_MOVNZ); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 299 | break; |
| 300 | case R_AARCH64_MOVW_PREL_G0_NC: |
| 301 | overflow_check = false; |
| 302 | ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0, |
Ard Biesheuvel | b24a557 | 2016-01-05 10:18:51 +0100 | [diff] [blame] | 303 | AARCH64_INSN_IMM_MOVKZ); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 304 | break; |
| 305 | case R_AARCH64_MOVW_PREL_G0: |
| 306 | ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0, |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 307 | AARCH64_INSN_IMM_MOVNZ); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 308 | break; |
| 309 | case R_AARCH64_MOVW_PREL_G1_NC: |
| 310 | overflow_check = false; |
| 311 | ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16, |
Ard Biesheuvel | b24a557 | 2016-01-05 10:18:51 +0100 | [diff] [blame] | 312 | AARCH64_INSN_IMM_MOVKZ); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 313 | break; |
| 314 | case R_AARCH64_MOVW_PREL_G1: |
| 315 | ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16, |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 316 | AARCH64_INSN_IMM_MOVNZ); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 317 | break; |
| 318 | case R_AARCH64_MOVW_PREL_G2_NC: |
| 319 | overflow_check = false; |
| 320 | ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32, |
Ard Biesheuvel | b24a557 | 2016-01-05 10:18:51 +0100 | [diff] [blame] | 321 | AARCH64_INSN_IMM_MOVKZ); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 322 | break; |
| 323 | case R_AARCH64_MOVW_PREL_G2: |
| 324 | ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32, |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 325 | AARCH64_INSN_IMM_MOVNZ); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 326 | break; |
| 327 | case R_AARCH64_MOVW_PREL_G3: |
| 328 | /* We're using the top bits so we can't overflow. */ |
| 329 | overflow_check = false; |
| 330 | ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 48, |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 331 | AARCH64_INSN_IMM_MOVNZ); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 332 | break; |
| 333 | |
| 334 | /* Immediate instruction relocations. */ |
| 335 | case R_AARCH64_LD_PREL_LO19: |
| 336 | ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19, |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 337 | AARCH64_INSN_IMM_19); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 338 | break; |
| 339 | case R_AARCH64_ADR_PREL_LO21: |
| 340 | ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21, |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 341 | AARCH64_INSN_IMM_ADR); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 342 | break; |
Will Deacon | df057cc | 2015-03-17 12:15:02 +0000 | [diff] [blame] | 343 | #ifndef CONFIG_ARM64_ERRATUM_843419 |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 344 | case R_AARCH64_ADR_PREL_PG_HI21_NC: |
| 345 | overflow_check = false; |
| 346 | case R_AARCH64_ADR_PREL_PG_HI21: |
| 347 | ovf = reloc_insn_imm(RELOC_OP_PAGE, loc, val, 12, 21, |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 348 | AARCH64_INSN_IMM_ADR); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 349 | break; |
Will Deacon | df057cc | 2015-03-17 12:15:02 +0000 | [diff] [blame] | 350 | #endif |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 351 | case R_AARCH64_ADD_ABS_LO12_NC: |
| 352 | case R_AARCH64_LDST8_ABS_LO12_NC: |
| 353 | overflow_check = false; |
| 354 | ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 0, 12, |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 355 | AARCH64_INSN_IMM_12); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 356 | break; |
| 357 | case R_AARCH64_LDST16_ABS_LO12_NC: |
| 358 | overflow_check = false; |
| 359 | ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 1, 11, |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 360 | AARCH64_INSN_IMM_12); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 361 | break; |
| 362 | case R_AARCH64_LDST32_ABS_LO12_NC: |
| 363 | overflow_check = false; |
| 364 | ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 2, 10, |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 365 | AARCH64_INSN_IMM_12); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 366 | break; |
| 367 | case R_AARCH64_LDST64_ABS_LO12_NC: |
| 368 | overflow_check = false; |
| 369 | ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 3, 9, |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 370 | AARCH64_INSN_IMM_12); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 371 | break; |
| 372 | case R_AARCH64_LDST128_ABS_LO12_NC: |
| 373 | overflow_check = false; |
| 374 | ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 4, 8, |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 375 | AARCH64_INSN_IMM_12); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 376 | break; |
| 377 | case R_AARCH64_TSTBR14: |
| 378 | ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 14, |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 379 | AARCH64_INSN_IMM_14); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 380 | break; |
| 381 | case R_AARCH64_CONDBR19: |
| 382 | ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19, |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 383 | AARCH64_INSN_IMM_19); |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 384 | break; |
| 385 | case R_AARCH64_JUMP26: |
| 386 | case R_AARCH64_CALL26: |
| 387 | ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 26, |
Jiang Liu | c84fced | 2014-01-07 22:17:10 +0800 | [diff] [blame] | 388 | AARCH64_INSN_IMM_26); |
Ard Biesheuvel | fd045f6 | 2015-11-24 12:37:35 +0100 | [diff] [blame] | 389 | |
| 390 | if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) && |
| 391 | ovf == -ERANGE) { |
Ard Biesheuvel | 92abb7f | 2017-02-21 22:12:57 +0000 | [diff] [blame] | 392 | val = module_emit_plt_entry(me, loc, &rel[i], sym); |
Ard Biesheuvel | fd045f6 | 2015-11-24 12:37:35 +0100 | [diff] [blame] | 393 | ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, |
| 394 | 26, AARCH64_INSN_IMM_26); |
| 395 | } |
Will Deacon | 257cb25 | 2012-03-05 11:49:33 +0000 | [diff] [blame] | 396 | break; |
| 397 | |
| 398 | default: |
| 399 | pr_err("module %s: unsupported RELA relocation: %llu\n", |
| 400 | me->name, ELF64_R_TYPE(rel[i].r_info)); |
| 401 | return -ENOEXEC; |
| 402 | } |
| 403 | |
| 404 | if (overflow_check && ovf == -ERANGE) |
| 405 | goto overflow; |
| 406 | |
| 407 | } |
| 408 | |
| 409 | return 0; |
| 410 | |
| 411 | overflow: |
| 412 | pr_err("module %s: overflow in relocation type %d val %Lx\n", |
| 413 | me->name, (int)ELF64_R_TYPE(rel[i].r_info), val); |
| 414 | return -ENOEXEC; |
| 415 | } |
Andre Przywara | 932ded4 | 2014-11-28 13:40:45 +0000 | [diff] [blame] | 416 | |
| 417 | int module_finalize(const Elf_Ehdr *hdr, |
| 418 | const Elf_Shdr *sechdrs, |
| 419 | struct module *me) |
| 420 | { |
| 421 | const Elf_Shdr *s, *se; |
| 422 | const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset; |
| 423 | |
| 424 | for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) { |
| 425 | if (strcmp(".altinstructions", secstrs + s->sh_name) == 0) { |
| 426 | apply_alternatives((void *)s->sh_addr, s->sh_size); |
| 427 | return 0; |
| 428 | } |
| 429 | } |
| 430 | |
| 431 | return 0; |
| 432 | } |