Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | #ifndef __ASM_TLB_H |
| 2 | #define __ASM_TLB_H |
| 3 | |
Paul Burton | 1031398 | 2016-11-12 01:26:07 +0000 | [diff] [blame] | 4 | #include <asm/cpu-features.h> |
| 5 | #include <asm/mipsregs.h> |
| 6 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | /* |
| 8 | * MIPS doesn't need any special per-pte or per-vma handling, except |
| 9 | * we need to flush cache for area to be unmapped. |
| 10 | */ |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 11 | #define tlb_start_vma(tlb, vma) \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12 | do { \ |
| 13 | if (!tlb->fullmm) \ |
| 14 | flush_cache_range(vma, vma->vm_start, vma->vm_end); \ |
| 15 | } while (0) |
| 16 | #define tlb_end_vma(tlb, vma) do { } while (0) |
| 17 | #define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0) |
| 18 | |
| 19 | /* |
| 20 | * .. because we flush the whole mm when it fills up. |
| 21 | */ |
| 22 | #define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) |
| 23 | |
Leonid Yegoshin | 6e7f8b8 | 2013-11-14 16:12:25 +0000 | [diff] [blame] | 24 | #define UNIQUE_ENTRYHI(idx) \ |
| 25 | ((CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) | \ |
| 26 | (cpu_has_tlbinv ? MIPS_ENTRYHI_EHINV : 0)) |
Markos Chandras | c01905e | 2013-11-14 16:12:22 +0000 | [diff] [blame] | 27 | |
Paul Burton | 1031398 | 2016-11-12 01:26:07 +0000 | [diff] [blame] | 28 | static inline unsigned int num_wired_entries(void) |
| 29 | { |
| 30 | unsigned int wired = read_c0_wired(); |
| 31 | |
| 32 | if (cpu_has_mips_r6) |
| 33 | wired &= MIPSR6_WIRED_WIRED; |
| 34 | |
| 35 | return wired; |
| 36 | } |
| 37 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | #include <asm-generic/tlb.h> |
| 39 | |
| 40 | #endif /* __ASM_TLB_H */ |