Paul Burton | 9c38cf4 | 2014-01-15 10:31:52 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Imagination Technologies |
| 3 | * Author: Paul Burton <paul.burton@imgtec.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License as published by the |
| 7 | * Free Software Foundation; either version 2 of the License, or (at your |
| 8 | * option) any later version. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/errno.h> |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 12 | #include <linux/percpu.h> |
| 13 | #include <linux/spinlock.h> |
Paul Burton | 9c38cf4 | 2014-01-15 10:31:52 +0000 | [diff] [blame] | 14 | |
| 15 | #include <asm/mips-cm.h> |
| 16 | #include <asm/mips-cpc.h> |
| 17 | |
| 18 | void __iomem *mips_cpc_base; |
| 19 | |
Paul Burton | 76ae658 | 2014-02-14 09:28:06 +0000 | [diff] [blame] | 20 | static DEFINE_PER_CPU_ALIGNED(spinlock_t, cpc_core_lock); |
| 21 | |
| 22 | static DEFINE_PER_CPU_ALIGNED(unsigned long, cpc_core_lock_flags); |
| 23 | |
Paul Burton | 682c1e5 | 2016-10-15 23:03:43 +0100 | [diff] [blame] | 24 | phys_addr_t __weak mips_cpc_default_phys_base(void) |
| 25 | { |
| 26 | return 0; |
| 27 | } |
| 28 | |
Bjorn Helgaas | 8dedde6 | 2015-07-12 18:10:56 -0500 | [diff] [blame] | 29 | /** |
| 30 | * mips_cpc_phys_base - retrieve the physical base address of the CPC |
| 31 | * |
| 32 | * This function returns the physical base address of the Cluster Power |
| 33 | * Controller memory mapped registers, or 0 if no Cluster Power Controller |
| 34 | * is present. |
| 35 | */ |
| 36 | static phys_addr_t mips_cpc_phys_base(void) |
Paul Burton | 9c38cf4 | 2014-01-15 10:31:52 +0000 | [diff] [blame] | 37 | { |
Markos Chandras | 391057d | 2015-07-09 10:40:46 +0100 | [diff] [blame] | 38 | unsigned long cpc_base; |
Paul Burton | 9c38cf4 | 2014-01-15 10:31:52 +0000 | [diff] [blame] | 39 | |
| 40 | if (!mips_cm_present()) |
| 41 | return 0; |
| 42 | |
| 43 | if (!(read_gcr_cpc_status() & CM_GCR_CPC_STATUS_EX_MSK)) |
| 44 | return 0; |
| 45 | |
| 46 | /* If the CPC is already enabled, leave it so */ |
| 47 | cpc_base = read_gcr_cpc_base(); |
| 48 | if (cpc_base & CM_GCR_CPC_BASE_CPCEN_MSK) |
| 49 | return cpc_base & CM_GCR_CPC_BASE_CPCBASE_MSK; |
| 50 | |
Paul Burton | 682c1e5 | 2016-10-15 23:03:43 +0100 | [diff] [blame] | 51 | /* Otherwise, use the default address */ |
Paul Burton | 9c38cf4 | 2014-01-15 10:31:52 +0000 | [diff] [blame] | 52 | cpc_base = mips_cpc_default_phys_base(); |
Paul Burton | 682c1e5 | 2016-10-15 23:03:43 +0100 | [diff] [blame] | 53 | if (!cpc_base) |
| 54 | return cpc_base; |
| 55 | |
| 56 | /* Enable the CPC, mapped at the default address */ |
Paul Burton | 9c38cf4 | 2014-01-15 10:31:52 +0000 | [diff] [blame] | 57 | write_gcr_cpc_base(cpc_base | CM_GCR_CPC_BASE_CPCEN_MSK); |
| 58 | return cpc_base; |
| 59 | } |
| 60 | |
| 61 | int mips_cpc_probe(void) |
| 62 | { |
Ralf Baechle | 15d45cc | 2014-11-22 00:22:09 +0100 | [diff] [blame] | 63 | phys_addr_t addr; |
Matt Redfearn | 6b89d22 | 2016-09-07 10:45:09 +0100 | [diff] [blame] | 64 | unsigned int cpu; |
Paul Burton | 76ae658 | 2014-02-14 09:28:06 +0000 | [diff] [blame] | 65 | |
| 66 | for_each_possible_cpu(cpu) |
| 67 | spin_lock_init(&per_cpu(cpc_core_lock, cpu)); |
Paul Burton | 9c38cf4 | 2014-01-15 10:31:52 +0000 | [diff] [blame] | 68 | |
| 69 | addr = mips_cpc_phys_base(); |
| 70 | if (!addr) |
| 71 | return -ENODEV; |
| 72 | |
| 73 | mips_cpc_base = ioremap_nocache(addr, 0x8000); |
| 74 | if (!mips_cpc_base) |
| 75 | return -ENXIO; |
| 76 | |
| 77 | return 0; |
| 78 | } |
Paul Burton | 76ae658 | 2014-02-14 09:28:06 +0000 | [diff] [blame] | 79 | |
| 80 | void mips_cpc_lock_other(unsigned int core) |
| 81 | { |
Matt Redfearn | 6b89d22 | 2016-09-07 10:45:09 +0100 | [diff] [blame] | 82 | unsigned int curr_core; |
Matt Redfearn | d621942 | 2016-09-07 10:45:10 +0100 | [diff] [blame] | 83 | |
| 84 | if (mips_cm_revision() >= CM_REV_CM3) |
| 85 | /* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */ |
| 86 | return; |
| 87 | |
Paul Burton | 76ae658 | 2014-02-14 09:28:06 +0000 | [diff] [blame] | 88 | preempt_disable(); |
| 89 | curr_core = current_cpu_data.core; |
| 90 | spin_lock_irqsave(&per_cpu(cpc_core_lock, curr_core), |
| 91 | per_cpu(cpc_core_lock_flags, curr_core)); |
| 92 | write_cpc_cl_other(core << CPC_Cx_OTHER_CORENUM_SHF); |
Paul Burton | 78a54c4 | 2015-09-22 11:12:18 -0700 | [diff] [blame] | 93 | |
| 94 | /* |
| 95 | * Ensure the core-other region reflects the appropriate core & |
| 96 | * VP before any accesses to it occur. |
| 97 | */ |
| 98 | mb(); |
Paul Burton | 76ae658 | 2014-02-14 09:28:06 +0000 | [diff] [blame] | 99 | } |
| 100 | |
| 101 | void mips_cpc_unlock_other(void) |
| 102 | { |
Matt Redfearn | d621942 | 2016-09-07 10:45:10 +0100 | [diff] [blame] | 103 | unsigned int curr_core; |
| 104 | |
| 105 | if (mips_cm_revision() >= CM_REV_CM3) |
| 106 | /* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */ |
| 107 | return; |
| 108 | |
| 109 | curr_core = current_cpu_data.core; |
Paul Burton | 76ae658 | 2014-02-14 09:28:06 +0000 | [diff] [blame] | 110 | spin_unlock_irqrestore(&per_cpu(cpc_core_lock, curr_core), |
| 111 | per_cpu(cpc_core_lock_flags, curr_core)); |
| 112 | preempt_enable(); |
| 113 | } |