Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle |
Justin P. Mattock | 79add62 | 2011-04-04 14:15:29 -0700 | [diff] [blame] | 7 | * Copyright (C) 1996 David S. Miller (davem@davemloft.net) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | * Copyright (C) 1994, 1995, 1996, by Andreas Busse |
| 9 | * Copyright (C) 1999 Silicon Graphics, Inc. |
| 10 | * Copyright (C) 2000 MIPS Technologies, Inc. |
| 11 | * written by Carsten Langgaard, carstenl@mips.com |
| 12 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | #include <asm/asm.h> |
| 14 | #include <asm/cachectl.h> |
| 15 | #include <asm/fpregdef.h> |
| 16 | #include <asm/mipsregs.h> |
Sam Ravnborg | 048eb58 | 2005-09-09 22:32:31 +0200 | [diff] [blame] | 17 | #include <asm/asm-offsets.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | #include <asm/regdef.h> |
| 19 | #include <asm/stackframe.h> |
| 20 | #include <asm/thread_info.h> |
| 21 | |
| 22 | #include <asm/asmmacro.h> |
| 23 | |
Manuel Lauss | 842dfc1 | 2014-11-07 14:13:54 +0100 | [diff] [blame] | 24 | /* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */ |
| 25 | #undef fp |
| 26 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 27 | /* |
| 28 | * Offset to the current process status flags, the first 32 bytes of the |
| 29 | * stack are not used. |
| 30 | */ |
| 31 | #define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS) |
| 32 | |
David Daney | a36d822 | 2014-05-28 23:52:04 +0200 | [diff] [blame] | 33 | #ifndef USE_ALTERNATE_RESUME_IMPL |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | * task_struct *resume(task_struct *prev, task_struct *next, |
Paul Burton | 1a3d595 | 2015-08-03 08:49:30 -0700 | [diff] [blame] | 36 | * struct thread_info *next_ti) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | */ |
| 38 | .align 5 |
| 39 | LEAF(resume) |
Atsushi Nemoto | 5323180 | 2007-04-14 02:37:26 +0900 | [diff] [blame] | 40 | mfc0 t1, CP0_STATUS |
| 41 | LONG_S t1, THREAD_STATUS(a0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 42 | cpu_save_nonscratch a0 |
| 43 | LONG_S ra, THREAD_REG31(a0) |
| 44 | |
Gregory Fong | 1400eb6 | 2013-06-17 19:36:07 +0000 | [diff] [blame] | 45 | #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) |
James Hogan | 8b3c569 | 2013-10-07 12:14:26 +0100 | [diff] [blame] | 46 | PTR_LA t8, __stack_chk_guard |
Gregory Fong | 1400eb6 | 2013-06-17 19:36:07 +0000 | [diff] [blame] | 47 | LONG_L t9, TASK_STACK_CANARY(a1) |
| 48 | LONG_S t9, 0(t8) |
| 49 | #endif |
| 50 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 51 | /* |
| 52 | * The order of restoring the registers takes care of the race |
| 53 | * updating $28, $29 and kernelsp without disabling ints. |
| 54 | */ |
| 55 | move $28, a2 |
| 56 | cpu_restore_nonscratch a1 |
| 57 | |
Ralf Baechle | 3bd3966 | 2007-07-11 08:32:21 +0100 | [diff] [blame] | 58 | PTR_ADDU t0, $28, _THREAD_SIZE - 32 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 59 | set_saved_sp t0, t1, t2 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 60 | mfc0 t1, CP0_STATUS /* Do we really need this? */ |
| 61 | li a3, 0xff01 |
| 62 | and t1, a3 |
| 63 | LONG_L a2, THREAD_STATUS(a1) |
| 64 | nor a3, $0, a3 |
| 65 | and a2, a3 |
| 66 | or a2, t1 |
| 67 | mtc0 a2, CP0_STATUS |
| 68 | move v0, a0 |
| 69 | jr ra |
| 70 | END(resume) |
| 71 | |
David Daney | a36d822 | 2014-05-28 23:52:04 +0200 | [diff] [blame] | 72 | #endif /* USE_ALTERNATE_RESUME_IMPL */ |
| 73 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 74 | /* |
| 75 | * Save a thread's fp context. |
| 76 | */ |
| 77 | LEAF(_save_fp) |
Leonid Yegoshin | 207083b | 2014-11-24 11:54:19 +0000 | [diff] [blame] | 78 | #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \ |
| 79 | defined(CONFIG_CPU_MIPS32_R6) |
Atsushi Nemoto | c138e12 | 2006-05-23 00:47:41 +0900 | [diff] [blame] | 80 | mfc0 t0, CP0_STATUS |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 81 | #endif |
Atsushi Nemoto | c138e12 | 2006-05-23 00:47:41 +0900 | [diff] [blame] | 82 | fpu_save_double a0 t0 t1 # clobbers t1 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 | jr ra |
| 84 | END(_save_fp) |
| 85 | |
| 86 | /* |
| 87 | * Restore a thread's fp context. |
| 88 | */ |
| 89 | LEAF(_restore_fp) |
Leonid Yegoshin | 207083b | 2014-11-24 11:54:19 +0000 | [diff] [blame] | 90 | #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \ |
| 91 | defined(CONFIG_CPU_MIPS32_R6) |
Atsushi Nemoto | c138e12 | 2006-05-23 00:47:41 +0900 | [diff] [blame] | 92 | mfc0 t0, CP0_STATUS |
| 93 | #endif |
| 94 | fpu_restore_double a0 t0 t1 # clobbers t1 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 95 | jr ra |
| 96 | END(_restore_fp) |
| 97 | |
Paul Burton | 1db1af8 | 2014-01-27 15:23:11 +0000 | [diff] [blame] | 98 | #ifdef CONFIG_CPU_HAS_MSA |
| 99 | |
| 100 | /* |
| 101 | * Save a thread's MSA vector context. |
| 102 | */ |
| 103 | LEAF(_save_msa) |
| 104 | msa_save_all a0 |
| 105 | jr ra |
| 106 | END(_save_msa) |
| 107 | |
| 108 | /* |
| 109 | * Restore a thread's MSA vector context. |
| 110 | */ |
| 111 | LEAF(_restore_msa) |
| 112 | msa_restore_all a0 |
| 113 | jr ra |
| 114 | END(_restore_msa) |
| 115 | |
Paul Burton | c901775 | 2014-07-30 08:53:20 +0100 | [diff] [blame] | 116 | LEAF(_init_msa_upper) |
| 117 | msa_init_all_upper |
| 118 | jr ra |
| 119 | END(_init_msa_upper) |
| 120 | |
Paul Burton | 1db1af8 | 2014-01-27 15:23:11 +0000 | [diff] [blame] | 121 | #endif |
| 122 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 123 | /* |
| 124 | * Load the FPU with signalling NANS. This bit pattern we're using has |
| 125 | * the property that no matter whether considered as single or as double |
| 126 | * precision represents signaling NANS. |
| 127 | * |
Maciej W. Rozycki | 9b26616 | 2015-04-03 23:27:48 +0100 | [diff] [blame] | 128 | * The value to initialize fcr31 to comes in $a0. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 129 | */ |
| 130 | |
Manuel Lauss | 842dfc1 | 2014-11-07 14:13:54 +0100 | [diff] [blame] | 131 | .set push |
| 132 | SET_HARDFLOAT |
| 133 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 134 | LEAF(_init_fpu) |
| 135 | mfc0 t0, CP0_STATUS |
| 136 | li t1, ST0_CU1 |
| 137 | or t0, t1 |
| 138 | mtc0 t0, CP0_STATUS |
Chris Dearman | f9509c8 | 2007-05-17 21:36:55 +0100 | [diff] [blame] | 139 | enable_fpu_hazard |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 140 | |
Maciej W. Rozycki | 9b26616 | 2015-04-03 23:27:48 +0100 | [diff] [blame] | 141 | ctc1 a0, fcr31 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 142 | |
| 143 | li t1, -1 # SNaN |
| 144 | |
Ralf Baechle | 875d43e | 2005-09-03 15:56:16 -0700 | [diff] [blame] | 145 | #ifdef CONFIG_64BIT |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 146 | sll t0, t0, 5 |
| 147 | bgez t0, 1f # 16 / 32 register mode? |
| 148 | |
| 149 | dmtc1 t1, $f1 |
| 150 | dmtc1 t1, $f3 |
| 151 | dmtc1 t1, $f5 |
| 152 | dmtc1 t1, $f7 |
| 153 | dmtc1 t1, $f9 |
| 154 | dmtc1 t1, $f11 |
| 155 | dmtc1 t1, $f13 |
| 156 | dmtc1 t1, $f15 |
| 157 | dmtc1 t1, $f17 |
| 158 | dmtc1 t1, $f19 |
| 159 | dmtc1 t1, $f21 |
| 160 | dmtc1 t1, $f23 |
| 161 | dmtc1 t1, $f25 |
| 162 | dmtc1 t1, $f27 |
| 163 | dmtc1 t1, $f29 |
| 164 | dmtc1 t1, $f31 |
| 165 | 1: |
| 166 | #endif |
Ralf Baechle | 42a3b4f | 2005-09-03 15:56:17 -0700 | [diff] [blame] | 167 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 168 | #ifdef CONFIG_CPU_MIPS32 |
| 169 | mtc1 t1, $f0 |
| 170 | mtc1 t1, $f1 |
| 171 | mtc1 t1, $f2 |
| 172 | mtc1 t1, $f3 |
| 173 | mtc1 t1, $f4 |
| 174 | mtc1 t1, $f5 |
| 175 | mtc1 t1, $f6 |
| 176 | mtc1 t1, $f7 |
| 177 | mtc1 t1, $f8 |
| 178 | mtc1 t1, $f9 |
| 179 | mtc1 t1, $f10 |
| 180 | mtc1 t1, $f11 |
| 181 | mtc1 t1, $f12 |
| 182 | mtc1 t1, $f13 |
| 183 | mtc1 t1, $f14 |
| 184 | mtc1 t1, $f15 |
| 185 | mtc1 t1, $f16 |
| 186 | mtc1 t1, $f17 |
| 187 | mtc1 t1, $f18 |
| 188 | mtc1 t1, $f19 |
| 189 | mtc1 t1, $f20 |
| 190 | mtc1 t1, $f21 |
| 191 | mtc1 t1, $f22 |
| 192 | mtc1 t1, $f23 |
| 193 | mtc1 t1, $f24 |
| 194 | mtc1 t1, $f25 |
| 195 | mtc1 t1, $f26 |
| 196 | mtc1 t1, $f27 |
| 197 | mtc1 t1, $f28 |
| 198 | mtc1 t1, $f29 |
| 199 | mtc1 t1, $f30 |
| 200 | mtc1 t1, $f31 |
Paul Burton | 597ce17 | 2013-11-22 13:12:07 +0000 | [diff] [blame] | 201 | |
Leonid Yegoshin | 207083b | 2014-11-24 11:54:19 +0000 | [diff] [blame] | 202 | #if defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS32_R6) |
Paul Burton | 597ce17 | 2013-11-22 13:12:07 +0000 | [diff] [blame] | 203 | .set push |
Leonid Yegoshin | 207083b | 2014-11-24 11:54:19 +0000 | [diff] [blame] | 204 | .set MIPS_ISA_LEVEL_RAW |
Manuel Lauss | 842dfc1 | 2014-11-07 14:13:54 +0100 | [diff] [blame] | 205 | .set fp=64 |
Paul Burton | 597ce17 | 2013-11-22 13:12:07 +0000 | [diff] [blame] | 206 | sll t0, t0, 5 # is Status.FR set? |
| 207 | bgez t0, 1f # no: skip setting upper 32b |
| 208 | |
| 209 | mthc1 t1, $f0 |
| 210 | mthc1 t1, $f1 |
| 211 | mthc1 t1, $f2 |
| 212 | mthc1 t1, $f3 |
| 213 | mthc1 t1, $f4 |
| 214 | mthc1 t1, $f5 |
| 215 | mthc1 t1, $f6 |
| 216 | mthc1 t1, $f7 |
| 217 | mthc1 t1, $f8 |
| 218 | mthc1 t1, $f9 |
| 219 | mthc1 t1, $f10 |
| 220 | mthc1 t1, $f11 |
| 221 | mthc1 t1, $f12 |
| 222 | mthc1 t1, $f13 |
| 223 | mthc1 t1, $f14 |
| 224 | mthc1 t1, $f15 |
| 225 | mthc1 t1, $f16 |
| 226 | mthc1 t1, $f17 |
| 227 | mthc1 t1, $f18 |
| 228 | mthc1 t1, $f19 |
| 229 | mthc1 t1, $f20 |
| 230 | mthc1 t1, $f21 |
| 231 | mthc1 t1, $f22 |
| 232 | mthc1 t1, $f23 |
| 233 | mthc1 t1, $f24 |
| 234 | mthc1 t1, $f25 |
| 235 | mthc1 t1, $f26 |
| 236 | mthc1 t1, $f27 |
| 237 | mthc1 t1, $f28 |
| 238 | mthc1 t1, $f29 |
| 239 | mthc1 t1, $f30 |
| 240 | mthc1 t1, $f31 |
| 241 | 1: .set pop |
Leonid Yegoshin | 207083b | 2014-11-24 11:54:19 +0000 | [diff] [blame] | 242 | #endif /* CONFIG_CPU_MIPS32_R2 || CONFIG_CPU_MIPS32_R6 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 243 | #else |
Leonid Yegoshin | 207083b | 2014-11-24 11:54:19 +0000 | [diff] [blame] | 244 | .set MIPS_ISA_ARCH_LEVEL_RAW |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 245 | dmtc1 t1, $f0 |
| 246 | dmtc1 t1, $f2 |
| 247 | dmtc1 t1, $f4 |
| 248 | dmtc1 t1, $f6 |
| 249 | dmtc1 t1, $f8 |
| 250 | dmtc1 t1, $f10 |
| 251 | dmtc1 t1, $f12 |
| 252 | dmtc1 t1, $f14 |
| 253 | dmtc1 t1, $f16 |
| 254 | dmtc1 t1, $f18 |
| 255 | dmtc1 t1, $f20 |
| 256 | dmtc1 t1, $f22 |
| 257 | dmtc1 t1, $f24 |
| 258 | dmtc1 t1, $f26 |
| 259 | dmtc1 t1, $f28 |
| 260 | dmtc1 t1, $f30 |
| 261 | #endif |
| 262 | jr ra |
| 263 | END(_init_fpu) |
Manuel Lauss | 842dfc1 | 2014-11-07 14:13:54 +0100 | [diff] [blame] | 264 | |
| 265 | .set pop /* SET_HARDFLOAT */ |