| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | 1. Need to figure out why PCI writes to the IOC3 hang, and if it is okay |
| 2 | not to write to the IOC3 ever. |
| 3 | 2. Need to figure out RRB allocation in bridge_startup(). |
| 4 | 3. Need to figure out why address swaizzling is needed in inw/outw for |
| 5 | Qlogic scsi controllers. |
| 6 | 4. Need to integrate ip27-klconfig.c:find_lboard and |
| 7 | ip27-init.c:find_lbaord_real. DONE |
| 8 | 5. Is it okay to set calias space on all nodes as 0, instead of 8k as |
| 9 | in irix? |
| 10 | 6. Investigate why things do not work without the setup_test() call |
| 11 | being invoked on all nodes in ip27-memory.c. |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12 | 8. Too many do_page_faults invoked - investigate. |
| 13 | 9. start_thread must turn off UX64 ... and define tlb_refill_debug. |
| 14 | 10. Need a bad pmd table, bad pte table. __bad_pmd_table/__bad_pagetable |
| 15 | does not agree with pgd_bad/pmd_bad. |
| Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 16 | 11. All intrs (ip27_do_irq handlers) are targeted at cpu A on the node. |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 17 | This might need to change later. Only the timer intr is set up to be |
| 18 | received on both Cpu A and B. (ip27_do_irq()/bridge_startup()) |
| 19 | 13. Cache flushing (specially the SMP version) has to be investigated. |