Blame - arch/powerpc/kernel/cpu_setup_power.S - kernel/msm-4.9

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Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	1	/*
				2	* This file contains low level CPU setup functions.
				3	* Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
				4	*
				5	* This program is free software; you can redistribute it and/or
				6	* modify it under the terms of the GNU General Public License
				7	* as published by the Free Software Foundation; either version
				8	* 2 of the License, or (at your option) any later version.
				9	*
				10	*/
				11
				12	#include <asm/processor.h>
				13	#include <asm/page.h>
				14	#include <asm/cputable.h>
				15	#include <asm/ppc_asm.h>
				16	#include <asm/asm-offsets.h>
				17	#include <asm/cache.h>
Aneesh Kumar K.V	f64e808	2016-03-01 12:59:20 +0530	[diff] [blame]	18	#include <asm/book3s/64/mmu-hash.h>
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	19
				20	/* Entry: r3 = crap, r4 = ptr to cputable entry
				21	*
				22	* Note that we can be called twice for pseudo-PVRs
				23	*/
				24	_GLOBAL(__setup_cpu_power7)
				25	mflr r11
				26	bl __init_hvmode_206
				27	mtlr r11
				28	beqlr
Benjamin Herrenschmidt	b144871	2011-03-01 15:46:09 +1100	[diff] [blame]	29	li r0,0
				30	mtspr SPRN_LPID,r0
Michael Neuling	09ae0d2	2018-05-18 11:37:42 +1000	[diff] [blame]	31	mtspr SPRN_PCR,r0
Michael Neuling	f7c32c2	2012-11-05 14:40:18 +1100	[diff] [blame]	32	mfspr r3,SPRN_LPCR
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	33	bl __init_LPCR
Mahesh Salgaonkar	0440705	2013-10-30 20:04:56 +0530	[diff] [blame]	34	bl __init_tlb_power7
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	35	mtlr r11
				36	blr
				37
				38	_GLOBAL(__restore_cpu_power7)
				39	mflr r11
				40	mfmsr r3
				41	rldicl. r0,r3,4,63
				42	beqlr
Benjamin Herrenschmidt	b144871	2011-03-01 15:46:09 +1100	[diff] [blame]	43	li r0,0
				44	mtspr SPRN_LPID,r0
Michael Neuling	09ae0d2	2018-05-18 11:37:42 +1000	[diff] [blame]	45	mtspr SPRN_PCR,r0
Michael Neuling	f7c32c2	2012-11-05 14:40:18 +1100	[diff] [blame]	46	mfspr r3,SPRN_LPCR
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	47	bl __init_LPCR
Mahesh Salgaonkar	0440705	2013-10-30 20:04:56 +0530	[diff] [blame]	48	bl __init_tlb_power7
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	49	mtlr r11
				50	blr
				51
Michael Neuling	aec937b	2012-10-30 19:34:14 +0000	[diff] [blame]	52	_GLOBAL(__setup_cpu_power8)
				53	mflr r11
Michael Neuling	57d2316	2013-03-04 19:45:50 +0000	[diff] [blame]	54	bl __init_FSCR
Michael Ellerman	240686c	2013-04-25 19:28:22 +0000	[diff] [blame]	55	bl __init_PMU
Madhavan Srinivasan	393eb79	2016-06-26 23:07:06 +0530	[diff] [blame]	56	bl __init_PMU_ISA207
Michael Neuling	aec937b	2012-10-30 19:34:14 +0000	[diff] [blame]	57	bl __init_hvmode_206
				58	mtlr r11
				59	beqlr
				60	li r0,0
				61	mtspr SPRN_LPID,r0
Michael Neuling	09ae0d2	2018-05-18 11:37:42 +1000	[diff] [blame]	62	mtspr SPRN_PCR,r0
Michael Neuling	f7c32c2	2012-11-05 14:40:18 +1100	[diff] [blame]	63	mfspr r3,SPRN_LPCR
Michael Neuling	d4e58e5	2014-06-11 15:59:28 +1000	[diff] [blame]	64	ori r3, r3, LPCR_PECEDH
Michael Neuling	aec937b	2012-10-30 19:34:14 +0000	[diff] [blame]	65	bl __init_LPCR
Michael Neuling	2a3563b	2013-03-05 17:35:24 +0000	[diff] [blame]	66	bl __init_HFSCR
Mahesh Salgaonkar	0440705	2013-10-30 20:04:56 +0530	[diff] [blame]	67	bl __init_tlb_power8
Michael Ellerman	240686c	2013-04-25 19:28:22 +0000	[diff] [blame]	68	bl __init_PMU_HV
Madhavan Srinivasan	393eb79	2016-06-26 23:07:06 +0530	[diff] [blame]	69	bl __init_PMU_HV_ISA207
Michael Neuling	aec937b	2012-10-30 19:34:14 +0000	[diff] [blame]	70	mtlr r11
				71	blr
				72
				73	_GLOBAL(__restore_cpu_power8)
				74	mflr r11
Michael Neuling	57d2316	2013-03-04 19:45:50 +0000	[diff] [blame]	75	bl __init_FSCR
Michael Ellerman	240686c	2013-04-25 19:28:22 +0000	[diff] [blame]	76	bl __init_PMU
Madhavan Srinivasan	393eb79	2016-06-26 23:07:06 +0530	[diff] [blame]	77	bl __init_PMU_ISA207
				78	mfmsr r3
				79	rldicl. r0,r3,4,63
				80	mtlr r11
				81	beqlr
				82	li r0,0
				83	mtspr SPRN_LPID,r0
Michael Neuling	09ae0d2	2018-05-18 11:37:42 +1000	[diff] [blame]	84	mtspr SPRN_PCR,r0
Madhavan Srinivasan	393eb79	2016-06-26 23:07:06 +0530	[diff] [blame]	85	mfspr r3,SPRN_LPCR
				86	ori r3, r3, LPCR_PECEDH
				87	bl __init_LPCR
				88	bl __init_HFSCR
				89	bl __init_tlb_power8
				90	bl __init_PMU_HV
				91	bl __init_PMU_HV_ISA207
				92	mtlr r11
				93	blr
				94
				95	_GLOBAL(__setup_cpu_power9)
				96	mflr r11
				97	bl __init_FSCR
				98	bl __init_PMU
				99	bl __init_hvmode_206
				100	mtlr r11
				101	beqlr
				102	li r0,0
				103	mtspr SPRN_LPID,r0
Nicholas Piggin	8950c98	2017-12-06 18:21:14 +1000	[diff] [blame]	104	mtspr SPRN_PID,r0
Michael Neuling	09ae0d2	2018-05-18 11:37:42 +1000	[diff] [blame]	105	mtspr SPRN_PCR,r0
Madhavan Srinivasan	393eb79	2016-06-26 23:07:06 +0530	[diff] [blame]	106	mfspr r3,SPRN_LPCR
Benjamin Herrenschmidt	7a43906	2016-11-21 18:08:05 +1100	[diff] [blame]	107	LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH \| LPCR_PECE_HVEE \| LPCR_HVICE)
				108	or r3, r3, r4
Aneesh Kumar K.V	075be78	2017-02-22 10:42:02 +0530	[diff] [blame]	109	LOAD_REG_IMMEDIATE(r4, LPCR_UPRT \| LPCR_HR)
				110	andc r3, r3, r4
Madhavan Srinivasan	393eb79	2016-06-26 23:07:06 +0530	[diff] [blame]	111	bl __init_LPCR
				112	bl __init_HFSCR
				113	bl __init_tlb_power9
				114	bl __init_PMU_HV
				115	mtlr r11
				116	blr
				117
				118	_GLOBAL(__restore_cpu_power9)
				119	mflr r11
				120	bl __init_FSCR
				121	bl __init_PMU
Michael Neuling	aec937b	2012-10-30 19:34:14 +0000	[diff] [blame]	122	mfmsr r3
				123	rldicl. r0,r3,4,63
Michael Neuling	8c2a381	2013-04-24 21:00:37 +0000	[diff] [blame]	124	mtlr r11
Michael Neuling	aec937b	2012-10-30 19:34:14 +0000	[diff] [blame]	125	beqlr
				126	li r0,0
				127	mtspr SPRN_LPID,r0
Nicholas Piggin	8950c98	2017-12-06 18:21:14 +1000	[diff] [blame]	128	mtspr SPRN_PID,r0
Michael Neuling	09ae0d2	2018-05-18 11:37:42 +1000	[diff] [blame]	129	mtspr SPRN_PCR,r0
Michael Neuling	f7c32c2	2012-11-05 14:40:18 +1100	[diff] [blame]	130	mfspr r3,SPRN_LPCR
Benjamin Herrenschmidt	7a43906	2016-11-21 18:08:05 +1100	[diff] [blame]	131	LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH \| LPCR_PECE_HVEE \| LPCR_HVICE)
				132	or r3, r3, r4
Aneesh Kumar K.V	075be78	2017-02-22 10:42:02 +0530	[diff] [blame]	133	LOAD_REG_IMMEDIATE(r4, LPCR_UPRT \| LPCR_HR)
				134	andc r3, r3, r4
Michael Neuling	aec937b	2012-10-30 19:34:14 +0000	[diff] [blame]	135	bl __init_LPCR
Michael Neuling	2a3563b	2013-03-05 17:35:24 +0000	[diff] [blame]	136	bl __init_HFSCR
Madhavan Srinivasan	393eb79	2016-06-26 23:07:06 +0530	[diff] [blame]	137	bl __init_tlb_power9
Michael Ellerman	240686c	2013-04-25 19:28:22 +0000	[diff] [blame]	138	bl __init_PMU_HV
Michael Neuling	aec937b	2012-10-30 19:34:14 +0000	[diff] [blame]	139	mtlr r11
				140	blr
				141
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	142	__init_hvmode_206:
Paul Mackerras	969391c	2011-06-29 00:26:11 +0000	[diff] [blame]	143	/* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	144	mfmsr r3
				145	rldicl. r0,r3,4,63
				146	bnelr
				147	ld r5,CPU_SPEC_FEATURES(r4)
Paul Mackerras	969391c	2011-06-29 00:26:11 +0000	[diff] [blame]	148	LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	149	xor r5,r5,r6
				150	std r5,CPU_SPEC_FEATURES(r4)
				151	blr
				152
				153	__init_LPCR:
				154	/* Setup a sane LPCR:
Michael Neuling	f7c32c2	2012-11-05 14:40:18 +1100	[diff] [blame]	155	* Called with initial LPCR in R3
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	156	*
Benjamin Herrenschmidt	a5d4f3a	2011-04-05 14:20:31 +1000	[diff] [blame]	157	* LPES = 0b01 (HSRR0/1 used for 0x500)
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	158	* PECE = 0b111
Benjamin Herrenschmidt	895796a	2011-01-24 13:25:55 +1100	[diff] [blame]	159	* DPFD = 4
Paul Mackerras	923c53c	2011-06-29 00:20:24 +0000	[diff] [blame]	160	* HDICE = 0
				161	* VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
				162	* VRMASD = 0b10000 (L=1, LP=00)
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	163	*
				164	* Other bits untouched for now
				165	*/
Paul Mackerras	923c53c	2011-06-29 00:20:24 +0000	[diff] [blame]	166	li r5,1
				167	rldimi r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	168	ori r3,r3,(LPCR_PECE0\|LPCR_PECE1\|LPCR_PECE2)
Benjamin Herrenschmidt	895796a	2011-01-24 13:25:55 +1100	[diff] [blame]	169	li r5,4
Paul Mackerras	923c53c	2011-06-29 00:20:24 +0000	[diff] [blame]	170	rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
				171	clrrdi r3,r3,1 /* clear HDICE */
				172	li r5,4
				173	rldimi r3,r5, LPCR_VC_SH, 0
				174	li r5,0x10
				175	rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	176	mtspr SPRN_LPCR,r3
				177	isync
				178	blr
Benjamin Herrenschmidt	b144871	2011-03-01 15:46:09 +1100	[diff] [blame]	179
Ian Munsie	2468dcf	2013-02-07 15:46:58 +0000	[diff] [blame]	180	__init_FSCR:
				181	mfspr r3,SPRN_FSCR
Michael Neuling	1ddf499	2013-04-30 20:17:03 +0000	[diff] [blame]	182	ori r3,r3,FSCR_TAR\|FSCR_DSCR\|FSCR_EBB
Ian Munsie	2468dcf	2013-02-07 15:46:58 +0000	[diff] [blame]	183	mtspr SPRN_FSCR,r3
				184	blr
				185
Michael Neuling	2a3563b	2013-03-05 17:35:24 +0000	[diff] [blame]	186	__init_HFSCR:
				187	mfspr r3,SPRN_HFSCR
Anshuman Khandual	53b56ca	2013-04-25 20:54:55 +0000	[diff] [blame]	188	ori r3,r3,HFSCR_TAR\|HFSCR_TM\|HFSCR_BHRB\|HFSCR_PM\|\
Michael Neuling	1ddf499	2013-04-30 20:17:03 +0000	[diff] [blame]	189	HFSCR_DSCR\|HFSCR_VECVSX\|HFSCR_FP\|HFSCR_EBB
Michael Neuling	2a3563b	2013-03-05 17:35:24 +0000	[diff] [blame]	190	mtspr SPRN_HFSCR,r3
				191	blr
				192
Mahesh Salgaonkar	0440705	2013-10-30 20:04:56 +0530	[diff] [blame]	193	/*
				194	* Clear the TLB using the specified IS form of tlbiel instruction
				195	* (invalidate by congruence class). P7 has 128 CCs., P8 has 512.
Mahesh Salgaonkar	0440705	2013-10-30 20:04:56 +0530	[diff] [blame]	196	*/
				197	__init_tlb_power7:
Michael Neuling	15b1624	2016-02-19 11:16:23 +1100	[diff] [blame]	198	li r6,POWER7_TLB_SETS
Mahesh Salgaonkar	0440705	2013-10-30 20:04:56 +0530	[diff] [blame]	199	mtctr r6
Mahesh Salgaonkar	45706bb	2014-12-19 08:41:05 +0530	[diff] [blame]	200	li r7,0xc00 /* IS field = 0b11 */
Mahesh Salgaonkar	0440705	2013-10-30 20:04:56 +0530	[diff] [blame]	201	ptesync
				202	2: tlbiel r7
				203	addi r7,r7,0x1000
				204	bdnz 2b
				205	ptesync
				206	1: blr
				207
				208	__init_tlb_power8:
Michael Neuling	15b1624	2016-02-19 11:16:23 +1100	[diff] [blame]	209	li r6,POWER8_TLB_SETS
Benjamin Herrenschmidt	b144871	2011-03-01 15:46:09 +1100	[diff] [blame]	210	mtctr r6
Mahesh Salgaonkar	45706bb	2014-12-19 08:41:05 +0530	[diff] [blame]	211	li r7,0xc00 /* IS field = 0b11 */
Benjamin Herrenschmidt	b144871	2011-03-01 15:46:09 +1100	[diff] [blame]	212	ptesync
				213	2: tlbiel r7
				214	addi r7,r7,0x1000
				215	bdnz 2b
				216	ptesync
				217	1: blr
Michael Ellerman	240686c	2013-04-25 19:28:22 +0000	[diff] [blame]	218
Michael Neuling	c3ab300	2016-02-19 11:16:24 +1100	[diff] [blame]	219	__init_tlb_power9:
				220	li r6,POWER9_TLB_SETS_HASH
				221	mtctr r6
				222	li r7,0xc00 /* IS field = 0b11 */
				223	ptesync
				224	2: tlbiel r7
				225	addi r7,r7,0x1000
				226	bdnz 2b
				227	ptesync
				228	1: blr
				229
Michael Ellerman	240686c	2013-04-25 19:28:22 +0000	[diff] [blame]	230	__init_PMU_HV:
				231	li r5,0
				232	mtspr SPRN_MMCRC,r5
Madhavan Srinivasan	393eb79	2016-06-26 23:07:06 +0530	[diff] [blame]	233	blr
				234
				235	__init_PMU_HV_ISA207:
				236	li r5,0
Michael Ellerman	240686c	2013-04-25 19:28:22 +0000	[diff] [blame]	237	mtspr SPRN_MMCRH,r5
				238	blr
				239
				240	__init_PMU:
				241	li r5,0
Michael Ellerman	240686c	2013-04-25 19:28:22 +0000	[diff] [blame]	242	mtspr SPRN_MMCRA,r5
				243	mtspr SPRN_MMCR0,r5
				244	mtspr SPRN_MMCR1,r5
				245	mtspr SPRN_MMCR2,r5
				246	blr
Madhavan Srinivasan	393eb79	2016-06-26 23:07:06 +0530	[diff] [blame]	247
				248	__init_PMU_ISA207:
				249	li r5,0
				250	mtspr SPRN_MMCRS,r5
				251	blr