Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1 | /* |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 2 | * PowerPC version |
| 3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
| 4 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP |
| 5 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> |
| 6 | * Adapted for Power Macintosh by Paul Mackerras. |
| 7 | * Low-level exception handlers and MMU support |
| 8 | * rewritten by Paul Mackerras. |
| 9 | * Copyright (C) 1996 Paul Mackerras. |
| 10 | * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net). |
| 11 | * |
| 12 | * This file contains the system call entry code, context switch |
| 13 | * code, and exception/interrupt return code for PowerPC. |
| 14 | * |
| 15 | * This program is free software; you can redistribute it and/or |
| 16 | * modify it under the terms of the GNU General Public License |
| 17 | * as published by the Free Software Foundation; either version |
| 18 | * 2 of the License, or (at your option) any later version. |
| 19 | */ |
| 20 | |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 21 | #include <linux/errno.h> |
Michael Ellerman | c352594 | 2015-07-23 20:21:01 +1000 | [diff] [blame] | 22 | #include <linux/err.h> |
Michael Ellerman | 85baa09 | 2016-03-24 22:04:05 +1100 | [diff] [blame] | 23 | #include <linux/magic.h> |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 24 | #include <asm/unistd.h> |
| 25 | #include <asm/processor.h> |
| 26 | #include <asm/page.h> |
| 27 | #include <asm/mmu.h> |
| 28 | #include <asm/thread_info.h> |
Michael Ellerman | 98f6ded | 2019-04-11 21:46:15 +1000 | [diff] [blame] | 29 | #include <asm/code-patching-asm.h> |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 30 | #include <asm/ppc_asm.h> |
| 31 | #include <asm/asm-offsets.h> |
| 32 | #include <asm/cputable.h> |
Stephen Rothwell | 3f639ee | 2006-09-25 18:19:00 +1000 | [diff] [blame] | 33 | #include <asm/firmware.h> |
David Woodhouse | 007d88d | 2007-01-01 18:45:34 +0000 | [diff] [blame] | 34 | #include <asm/bug.h> |
Benjamin Herrenschmidt | ec2b36b | 2008-04-17 14:34:59 +1000 | [diff] [blame] | 35 | #include <asm/ptrace.h> |
Benjamin Herrenschmidt | 945feb1 | 2008-04-17 14:35:01 +1000 | [diff] [blame] | 36 | #include <asm/irqflags.h> |
Abhishek Sagar | 395a59d | 2008-06-21 23:47:27 +0530 | [diff] [blame] | 37 | #include <asm/ftrace.h> |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 38 | #include <asm/hw_irq.h> |
Li Zhong | 5d1c574 | 2013-05-13 16:16:43 +0000 | [diff] [blame] | 39 | #include <asm/context_tracking.h> |
Sam bobroff | b4b56f9 | 2015-06-12 11:06:32 +1000 | [diff] [blame] | 40 | #include <asm/tm.h> |
Chris Smart | 8a64904 | 2016-04-26 10:28:50 +1000 | [diff] [blame] | 41 | #include <asm/ppc-opcode.h> |
Michael Ellerman | 86dfa51 | 2019-04-11 21:46:03 +1000 | [diff] [blame] | 42 | #include <asm/barrier.h> |
Al Viro | 9445aa1 | 2016-01-13 23:33:46 -0500 | [diff] [blame] | 43 | #include <asm/export.h> |
Nicholas Piggin | e41b3b8 | 2018-01-10 03:07:15 +1100 | [diff] [blame] | 44 | #ifdef CONFIG_PPC_BOOK3S |
| 45 | #include <asm/exception-64s.h> |
| 46 | #else |
| 47 | #include <asm/exception-64e.h> |
| 48 | #endif |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 49 | |
| 50 | /* |
| 51 | * System calls. |
| 52 | */ |
| 53 | .section ".toc","aw" |
Anton Blanchard | c857c43 | 2014-02-04 16:05:53 +1100 | [diff] [blame] | 54 | SYS_CALL_TABLE: |
| 55 | .tc sys_call_table[TC],sys_call_table |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 56 | |
| 57 | /* This value is used to mark exception frames on the stack. */ |
| 58 | exception_marker: |
Benjamin Herrenschmidt | ec2b36b | 2008-04-17 14:34:59 +1000 | [diff] [blame] | 59 | .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 60 | |
| 61 | .section ".text" |
| 62 | .align 7 |
| 63 | |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 64 | .globl system_call_common |
| 65 | system_call_common: |
Sam bobroff | b4b56f9 | 2015-06-12 11:06:32 +1000 | [diff] [blame] | 66 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
| 67 | BEGIN_FTR_SECTION |
| 68 | extrdi. r10, r12, 1, (63-MSR_TS_T_LG) /* transaction active? */ |
| 69 | bne tabort_syscall |
| 70 | END_FTR_SECTION_IFSET(CPU_FTR_TM) |
| 71 | #endif |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 72 | andi. r10,r12,MSR_PR |
| 73 | mr r10,r1 |
| 74 | addi r1,r1,-INT_FRAME_SIZE |
| 75 | beq- 1f |
| 76 | ld r1,PACAKSAVE(r13) |
| 77 | 1: std r10,0(r1) |
| 78 | std r11,_NIP(r1) |
| 79 | std r12,_MSR(r1) |
| 80 | std r0,GPR0(r1) |
| 81 | std r10,GPR1(r1) |
Haren Myneni | 5d75b26 | 2012-12-06 21:46:37 +0000 | [diff] [blame] | 82 | beq 2f /* if from kernel mode */ |
Diana Craciun | dd8bf94 | 2019-04-11 21:46:23 +1000 | [diff] [blame] | 83 | #ifdef CONFIG_PPC_FSL_BOOK3E |
| 84 | START_BTB_FLUSH_SECTION |
| 85 | BTB_FLUSH(r10) |
| 86 | END_BTB_FLUSH_SECTION |
| 87 | #endif |
Christophe Leroy | c223c90 | 2016-05-17 08:33:46 +0200 | [diff] [blame] | 88 | ACCOUNT_CPU_USER_ENTRY(r13, r10, r11) |
Haren Myneni | 5d75b26 | 2012-12-06 21:46:37 +0000 | [diff] [blame] | 89 | 2: std r2,GPR2(r1) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 90 | std r3,GPR3(r1) |
Anton Blanchard | fd6c40f | 2012-04-05 03:44:48 +0000 | [diff] [blame] | 91 | mfcr r2 |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 92 | std r4,GPR4(r1) |
| 93 | std r5,GPR5(r1) |
| 94 | std r6,GPR6(r1) |
| 95 | std r7,GPR7(r1) |
| 96 | std r8,GPR8(r1) |
| 97 | li r11,0 |
| 98 | std r11,GPR9(r1) |
| 99 | std r11,GPR10(r1) |
| 100 | std r11,GPR11(r1) |
| 101 | std r11,GPR12(r1) |
Anton Blanchard | 823df43 | 2012-04-04 18:24:29 +0000 | [diff] [blame] | 102 | std r11,_XER(r1) |
Anton Blanchard | 8208741 | 2012-04-04 18:26:39 +0000 | [diff] [blame] | 103 | std r11,_CTR(r1) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 104 | std r9,GPR13(r1) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 105 | mflr r10 |
Anton Blanchard | fd6c40f | 2012-04-05 03:44:48 +0000 | [diff] [blame] | 106 | /* |
| 107 | * This clears CR0.SO (bit 28), which is the error indication on |
| 108 | * return from this system call. |
| 109 | */ |
| 110 | rldimi r2,r11,28,(63-28) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 111 | li r11,0xc01 |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 112 | std r10,_LINK(r1) |
| 113 | std r11,_TRAP(r1) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 114 | std r3,ORIG_GPR3(r1) |
Anton Blanchard | fd6c40f | 2012-04-05 03:44:48 +0000 | [diff] [blame] | 115 | std r2,_CCR(r1) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 116 | ld r2,PACATOC(r13) |
| 117 | addi r9,r1,STACK_FRAME_OVERHEAD |
| 118 | ld r11,exception_marker@toc(r2) |
| 119 | std r11,-16(r9) /* "regshere" marker */ |
Frederic Weisbecker | abf917c | 2012-07-25 07:56:04 +0200 | [diff] [blame] | 120 | #if defined(CONFIG_VIRT_CPU_ACCOUNTING_NATIVE) && defined(CONFIG_PPC_SPLPAR) |
Paul Mackerras | cf9efce | 2010-08-26 19:56:43 +0000 | [diff] [blame] | 121 | BEGIN_FW_FTR_SECTION |
| 122 | beq 33f |
| 123 | /* if from user, see if there are any DTL entries to process */ |
| 124 | ld r10,PACALPPACAPTR(r13) /* get ptr to VPA */ |
| 125 | ld r11,PACA_DTL_RIDX(r13) /* get log read index */ |
Anton Blanchard | 7ffcf8e | 2013-08-07 02:01:46 +1000 | [diff] [blame] | 126 | addi r10,r10,LPPACA_DTLIDX |
| 127 | LDX_BE r10,0,r10 /* get log write index */ |
Paul Mackerras | cf9efce | 2010-08-26 19:56:43 +0000 | [diff] [blame] | 128 | cmpd cr1,r11,r10 |
| 129 | beq+ cr1,33f |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 130 | bl accumulate_stolen_time |
Paul Mackerras | cf9efce | 2010-08-26 19:56:43 +0000 | [diff] [blame] | 131 | REST_GPR(0,r1) |
| 132 | REST_4GPRS(3,r1) |
| 133 | REST_2GPRS(7,r1) |
| 134 | addi r9,r1,STACK_FRAME_OVERHEAD |
| 135 | 33: |
| 136 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR) |
Frederic Weisbecker | abf917c | 2012-07-25 07:56:04 +0200 | [diff] [blame] | 137 | #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE && CONFIG_PPC_SPLPAR */ |
Paul Mackerras | cf9efce | 2010-08-26 19:56:43 +0000 | [diff] [blame] | 138 | |
Benjamin Herrenschmidt | 1421ae0 | 2012-03-01 15:40:23 +1100 | [diff] [blame] | 139 | /* |
| 140 | * A syscall should always be called with interrupts enabled |
| 141 | * so we just unconditionally hard-enable here. When some kind |
| 142 | * of irq tracing is used, we additionally check that condition |
| 143 | * is correct |
| 144 | */ |
| 145 | #if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_BUG) |
| 146 | lbz r10,PACASOFTIRQEN(r13) |
| 147 | xori r10,r10,1 |
| 148 | 1: tdnei r10,0 |
| 149 | EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING |
| 150 | #endif |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 151 | |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 152 | #ifdef CONFIG_PPC_BOOK3E |
| 153 | wrteei 1 |
| 154 | #else |
Nicholas Piggin | 49d09bf | 2016-09-15 19:04:46 +1000 | [diff] [blame] | 155 | li r11,MSR_RI |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 156 | ori r11,r11,MSR_EE |
| 157 | mtmsrd r11,1 |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 158 | #endif /* CONFIG_PPC_BOOK3E */ |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 159 | |
Benjamin Herrenschmidt | 1421ae0 | 2012-03-01 15:40:23 +1100 | [diff] [blame] | 160 | /* We do need to set SOFTE in the stack frame or the return |
| 161 | * from interrupt will be painful |
| 162 | */ |
| 163 | li r10,1 |
| 164 | std r10,SOFTE(r1) |
| 165 | |
Stuart Yoder | 9778b69 | 2012-07-05 04:41:35 +0000 | [diff] [blame] | 166 | CURRENT_THREAD_INFO(r11, r1) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 167 | ld r10,TI_FLAGS(r11) |
Michael Ellerman | 10ea834 | 2015-01-15 12:01:42 +1100 | [diff] [blame] | 168 | andi. r11,r10,_TIF_SYSCALL_DOTRACE |
Michael Ellerman | d383741 | 2015-07-23 20:21:02 +1000 | [diff] [blame] | 169 | bne syscall_dotrace /* does not return */ |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 170 | cmpldi 0,r0,NR_syscalls |
| 171 | bge- syscall_enosys |
| 172 | |
| 173 | system_call: /* label this so stack traces look sane */ |
| 174 | /* |
| 175 | * Need to vector to 32 Bit or default sys_call_table here, |
| 176 | * based on caller's run-mode / personality. |
| 177 | */ |
Anton Blanchard | c857c43 | 2014-02-04 16:05:53 +1100 | [diff] [blame] | 178 | ld r11,SYS_CALL_TABLE@toc(2) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 179 | andi. r10,r10,_TIF_32BIT |
| 180 | beq 15f |
| 181 | addi r11,r11,8 /* use 32-bit syscall entries */ |
| 182 | clrldi r3,r3,32 |
| 183 | clrldi r4,r4,32 |
| 184 | clrldi r5,r5,32 |
| 185 | clrldi r6,r6,32 |
| 186 | clrldi r7,r7,32 |
| 187 | clrldi r8,r8,32 |
| 188 | 15: |
| 189 | slwi r0,r0,4 |
Michael Ellerman | 86dfa51 | 2019-04-11 21:46:03 +1000 | [diff] [blame] | 190 | |
| 191 | barrier_nospec_asm |
| 192 | /* |
| 193 | * Prevent the load of the handler below (based on the user-passed |
| 194 | * system call number) being speculatively executed until the test |
| 195 | * against NR_syscalls and branch to .Lsyscall_enosys above has |
| 196 | * committed. |
| 197 | */ |
| 198 | |
Anton Blanchard | cc7efbf | 2014-02-04 16:07:47 +1100 | [diff] [blame] | 199 | ldx r12,r11,r0 /* Fetch system call handler [ptr] */ |
| 200 | mtctr r12 |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 201 | bctrl /* Call handler */ |
| 202 | |
Michael Ellerman | 4c3b216 | 2014-12-05 21:16:59 +1100 | [diff] [blame] | 203 | .Lsyscall_exit: |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 204 | std r3,RESULT(r1) |
Stuart Yoder | 9778b69 | 2012-07-05 04:41:35 +0000 | [diff] [blame] | 205 | CURRENT_THREAD_INFO(r12, r1) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 206 | |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 207 | ld r8,_MSR(r1) |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 208 | #ifdef CONFIG_PPC_BOOK3S |
| 209 | /* No MSR:RI on BookE */ |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 210 | andi. r10,r8,MSR_RI |
| 211 | beq- unrecov_restore |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 212 | #endif |
Benjamin Herrenschmidt | 1421ae0 | 2012-03-01 15:40:23 +1100 | [diff] [blame] | 213 | /* |
| 214 | * Disable interrupts so current_thread_info()->flags can't change, |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 215 | * and so that we don't get interrupted after loading SRR0/1. |
| 216 | */ |
| 217 | #ifdef CONFIG_PPC_BOOK3E |
| 218 | wrteei 0 |
| 219 | #else |
Anton Blanchard | ac1dc36 | 2012-05-29 12:22:00 +0000 | [diff] [blame] | 220 | /* |
| 221 | * For performance reasons we clear RI the same time that we |
| 222 | * clear EE. We only need to clear RI just before we restore r13 |
| 223 | * below, but batching it with EE saves us one expensive mtmsrd call. |
| 224 | * We have to be careful to restore RI if we branch anywhere from |
| 225 | * here (eg syscall_exit_work). |
| 226 | */ |
Nicholas Piggin | 49d09bf | 2016-09-15 19:04:46 +1000 | [diff] [blame] | 227 | li r11,0 |
Anton Blanchard | ac1dc36 | 2012-05-29 12:22:00 +0000 | [diff] [blame] | 228 | mtmsrd r11,1 |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 229 | #endif /* CONFIG_PPC_BOOK3E */ |
| 230 | |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 231 | ld r9,TI_FLAGS(r12) |
Michael Ellerman | c352594 | 2015-07-23 20:21:01 +1000 | [diff] [blame] | 232 | li r11,-MAX_ERRNO |
Michael Ellerman | 10ea834 | 2015-01-15 12:01:42 +1100 | [diff] [blame] | 233 | andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 234 | bne- syscall_exit_work |
Cyril Bur | 70fe3d9 | 2016-02-29 17:53:47 +1100 | [diff] [blame] | 235 | |
| 236 | andi. r0,r8,MSR_FP |
| 237 | beq 2f |
| 238 | #ifdef CONFIG_ALTIVEC |
| 239 | andis. r0,r8,MSR_VEC@h |
| 240 | bne 3f |
| 241 | #endif |
| 242 | 2: addi r3,r1,STACK_FRAME_OVERHEAD |
Cyril Bur | 6e669f0 | 2016-03-16 13:29:30 +1100 | [diff] [blame] | 243 | #ifdef CONFIG_PPC_BOOK3S |
Nicholas Piggin | 49d09bf | 2016-09-15 19:04:46 +1000 | [diff] [blame] | 244 | li r10,MSR_RI |
Cyril Bur | 6e669f0 | 2016-03-16 13:29:30 +1100 | [diff] [blame] | 245 | mtmsrd r10,1 /* Restore RI */ |
| 246 | #endif |
Cyril Bur | 70fe3d9 | 2016-02-29 17:53:47 +1100 | [diff] [blame] | 247 | bl restore_math |
Cyril Bur | 6e669f0 | 2016-03-16 13:29:30 +1100 | [diff] [blame] | 248 | #ifdef CONFIG_PPC_BOOK3S |
Nicholas Piggin | 49d09bf | 2016-09-15 19:04:46 +1000 | [diff] [blame] | 249 | li r11,0 |
Cyril Bur | 6e669f0 | 2016-03-16 13:29:30 +1100 | [diff] [blame] | 250 | mtmsrd r11,1 |
| 251 | #endif |
Cyril Bur | 70fe3d9 | 2016-02-29 17:53:47 +1100 | [diff] [blame] | 252 | ld r8,_MSR(r1) |
| 253 | ld r3,RESULT(r1) |
| 254 | li r11,-MAX_ERRNO |
| 255 | |
| 256 | 3: cmpld r3,r11 |
David Woodhouse | 401d1f0 | 2005-11-15 18:52:18 +0000 | [diff] [blame] | 257 | ld r5,_CCR(r1) |
| 258 | bge- syscall_error |
Anton Blanchard | d14299d | 2012-04-04 18:23:27 +0000 | [diff] [blame] | 259 | .Lsyscall_error_cont: |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 260 | ld r7,_NIP(r1) |
Anton Blanchard | f89451f | 2010-08-11 01:40:27 +0000 | [diff] [blame] | 261 | BEGIN_FTR_SECTION |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 262 | stdcx. r0,0,r1 /* to clear the reservation */ |
Anton Blanchard | f89451f | 2010-08-11 01:40:27 +0000 | [diff] [blame] | 263 | END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 264 | andi. r6,r8,MSR_PR |
| 265 | ld r4,_LINK(r1) |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 266 | |
Paul Mackerras | c6622f6 | 2006-02-24 10:06:59 +1100 | [diff] [blame] | 267 | beq- 1f |
Christophe Leroy | c223c90 | 2016-05-17 08:33:46 +0200 | [diff] [blame] | 268 | ACCOUNT_CPU_USER_EXIT(r13, r11, r12) |
Michael Ellerman | d030a4b | 2015-11-25 14:25:17 +1100 | [diff] [blame] | 269 | |
| 270 | BEGIN_FTR_SECTION |
| 271 | HMT_MEDIUM_LOW |
| 272 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) |
| 273 | |
Paul Mackerras | c6622f6 | 2006-02-24 10:06:59 +1100 | [diff] [blame] | 274 | ld r13,GPR13(r1) /* only restore r13 if returning to usermode */ |
Nicholas Piggin | 00e4062 | 2018-01-10 03:07:15 +1100 | [diff] [blame] | 275 | ld r2,GPR2(r1) |
| 276 | ld r1,GPR1(r1) |
| 277 | mtlr r4 |
| 278 | mtcr r5 |
| 279 | mtspr SPRN_SRR0,r7 |
| 280 | mtspr SPRN_SRR1,r8 |
| 281 | RFI_TO_USER |
| 282 | b . /* prevent speculative execution */ |
| 283 | |
| 284 | /* exit to kernel */ |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 285 | 1: ld r2,GPR2(r1) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 286 | ld r1,GPR1(r1) |
| 287 | mtlr r4 |
| 288 | mtcr r5 |
| 289 | mtspr SPRN_SRR0,r7 |
| 290 | mtspr SPRN_SRR1,r8 |
Nicholas Piggin | 00e4062 | 2018-01-10 03:07:15 +1100 | [diff] [blame] | 291 | RFI_TO_KERNEL |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 292 | b . /* prevent speculative execution */ |
| 293 | |
David Woodhouse | 401d1f0 | 2005-11-15 18:52:18 +0000 | [diff] [blame] | 294 | syscall_error: |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 295 | oris r5,r5,0x1000 /* Set SO bit in CR */ |
David Woodhouse | 401d1f0 | 2005-11-15 18:52:18 +0000 | [diff] [blame] | 296 | neg r3,r3 |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 297 | std r5,_CCR(r1) |
Anton Blanchard | d14299d | 2012-04-04 18:23:27 +0000 | [diff] [blame] | 298 | b .Lsyscall_error_cont |
David Woodhouse | 401d1f0 | 2005-11-15 18:52:18 +0000 | [diff] [blame] | 299 | |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 300 | /* Traced system call support */ |
| 301 | syscall_dotrace: |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 302 | bl save_nvgprs |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 303 | addi r3,r1,STACK_FRAME_OVERHEAD |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 304 | bl do_syscall_trace_enter |
Michael Ellerman | d383741 | 2015-07-23 20:21:02 +1000 | [diff] [blame] | 305 | |
Roland McGrath | 4f72c42 | 2008-07-27 16:51:03 +1000 | [diff] [blame] | 306 | /* |
Michael Ellerman | d383741 | 2015-07-23 20:21:02 +1000 | [diff] [blame] | 307 | * We use the return value of do_syscall_trace_enter() as the syscall |
| 308 | * number. If the syscall was rejected for any reason do_syscall_trace_enter() |
| 309 | * returns an invalid syscall number and the test below against |
| 310 | * NR_syscalls will fail. |
Roland McGrath | 4f72c42 | 2008-07-27 16:51:03 +1000 | [diff] [blame] | 311 | */ |
| 312 | mr r0,r3 |
Michael Ellerman | d383741 | 2015-07-23 20:21:02 +1000 | [diff] [blame] | 313 | |
| 314 | /* Restore argument registers just clobbered and/or possibly changed. */ |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 315 | ld r3,GPR3(r1) |
| 316 | ld r4,GPR4(r1) |
| 317 | ld r5,GPR5(r1) |
| 318 | ld r6,GPR6(r1) |
| 319 | ld r7,GPR7(r1) |
| 320 | ld r8,GPR8(r1) |
Michael Ellerman | d383741 | 2015-07-23 20:21:02 +1000 | [diff] [blame] | 321 | |
| 322 | /* Repopulate r9 and r10 for the system_call path */ |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 323 | addi r9,r1,STACK_FRAME_OVERHEAD |
Stuart Yoder | 9778b69 | 2012-07-05 04:41:35 +0000 | [diff] [blame] | 324 | CURRENT_THREAD_INFO(r10, r1) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 325 | ld r10,TI_FLAGS(r10) |
Michael Ellerman | d383741 | 2015-07-23 20:21:02 +1000 | [diff] [blame] | 326 | |
| 327 | cmpldi r0,NR_syscalls |
| 328 | blt+ system_call |
| 329 | |
| 330 | /* Return code is already in r3 thanks to do_syscall_trace_enter() */ |
| 331 | b .Lsyscall_exit |
| 332 | |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 333 | |
David Woodhouse | 401d1f0 | 2005-11-15 18:52:18 +0000 | [diff] [blame] | 334 | syscall_enosys: |
| 335 | li r3,-ENOSYS |
Michael Ellerman | 4c3b216 | 2014-12-05 21:16:59 +1100 | [diff] [blame] | 336 | b .Lsyscall_exit |
David Woodhouse | 401d1f0 | 2005-11-15 18:52:18 +0000 | [diff] [blame] | 337 | |
| 338 | syscall_exit_work: |
Anton Blanchard | ac1dc36 | 2012-05-29 12:22:00 +0000 | [diff] [blame] | 339 | #ifdef CONFIG_PPC_BOOK3S |
Nicholas Piggin | 49d09bf | 2016-09-15 19:04:46 +1000 | [diff] [blame] | 340 | li r10,MSR_RI |
Anton Blanchard | ac1dc36 | 2012-05-29 12:22:00 +0000 | [diff] [blame] | 341 | mtmsrd r10,1 /* Restore RI */ |
| 342 | #endif |
David Woodhouse | 401d1f0 | 2005-11-15 18:52:18 +0000 | [diff] [blame] | 343 | /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr. |
| 344 | If TIF_NOERROR is set, just save r3 as it is. */ |
| 345 | |
| 346 | andi. r0,r9,_TIF_RESTOREALL |
Paul Mackerras | 1bd7933 | 2006-03-08 13:24:22 +1100 | [diff] [blame] | 347 | beq+ 0f |
| 348 | REST_NVGPRS(r1) |
| 349 | b 2f |
Michael Ellerman | c352594 | 2015-07-23 20:21:01 +1000 | [diff] [blame] | 350 | 0: cmpld r3,r11 /* r11 is -MAX_ERRNO */ |
David Woodhouse | 401d1f0 | 2005-11-15 18:52:18 +0000 | [diff] [blame] | 351 | blt+ 1f |
| 352 | andi. r0,r9,_TIF_NOERROR |
| 353 | bne- 1f |
| 354 | ld r5,_CCR(r1) |
| 355 | neg r3,r3 |
| 356 | oris r5,r5,0x1000 /* Set SO bit in CR */ |
| 357 | std r5,_CCR(r1) |
| 358 | 1: std r3,GPR3(r1) |
| 359 | 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK) |
| 360 | beq 4f |
| 361 | |
Paul Mackerras | 1bd7933 | 2006-03-08 13:24:22 +1100 | [diff] [blame] | 362 | /* Clear per-syscall TIF flags if any are set. */ |
David Woodhouse | 401d1f0 | 2005-11-15 18:52:18 +0000 | [diff] [blame] | 363 | |
| 364 | li r11,_TIF_PERSYSCALL_MASK |
| 365 | addi r12,r12,TI_FLAGS |
| 366 | 3: ldarx r10,0,r12 |
| 367 | andc r10,r10,r11 |
| 368 | stdcx. r10,0,r12 |
| 369 | bne- 3b |
| 370 | subi r12,r12,TI_FLAGS |
Paul Mackerras | 1bd7933 | 2006-03-08 13:24:22 +1100 | [diff] [blame] | 371 | |
| 372 | 4: /* Anything else left to do? */ |
Michael Ellerman | d8725ce | 2015-11-25 14:25:18 +1100 | [diff] [blame] | 373 | BEGIN_FTR_SECTION |
| 374 | lis r3,INIT_PPR@highest /* Set thread.ppr = 3 */ |
| 375 | ld r10,PACACURRENT(r13) |
| 376 | sldi r3,r3,32 /* bits 11-13 are used for ppr */ |
| 377 | std r3,TASKTHREADPPR(r10) |
| 378 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) |
| 379 | |
Michael Ellerman | 10ea834 | 2015-01-15 12:01:42 +1100 | [diff] [blame] | 380 | andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP) |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 381 | beq ret_from_except_lite |
David Woodhouse | 401d1f0 | 2005-11-15 18:52:18 +0000 | [diff] [blame] | 382 | |
| 383 | /* Re-enable interrupts */ |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 384 | #ifdef CONFIG_PPC_BOOK3E |
| 385 | wrteei 1 |
| 386 | #else |
Nicholas Piggin | 49d09bf | 2016-09-15 19:04:46 +1000 | [diff] [blame] | 387 | li r10,MSR_RI |
David Woodhouse | 401d1f0 | 2005-11-15 18:52:18 +0000 | [diff] [blame] | 388 | ori r10,r10,MSR_EE |
| 389 | mtmsrd r10,1 |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 390 | #endif /* CONFIG_PPC_BOOK3E */ |
David Woodhouse | 401d1f0 | 2005-11-15 18:52:18 +0000 | [diff] [blame] | 391 | |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 392 | bl save_nvgprs |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 393 | addi r3,r1,STACK_FRAME_OVERHEAD |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 394 | bl do_syscall_trace_leave |
| 395 | b ret_from_except |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 396 | |
Sam bobroff | b4b56f9 | 2015-06-12 11:06:32 +1000 | [diff] [blame] | 397 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
| 398 | tabort_syscall: |
| 399 | /* Firstly we need to enable TM in the kernel */ |
| 400 | mfmsr r10 |
Nicholas Piggin | cc7786d | 2016-07-25 14:26:51 +1000 | [diff] [blame] | 401 | li r9, 1 |
| 402 | rldimi r10, r9, MSR_TM_LG, 63-MSR_TM_LG |
Sam bobroff | b4b56f9 | 2015-06-12 11:06:32 +1000 | [diff] [blame] | 403 | mtmsrd r10, 0 |
| 404 | |
| 405 | /* tabort, this dooms the transaction, nothing else */ |
Nicholas Piggin | cc7786d | 2016-07-25 14:26:51 +1000 | [diff] [blame] | 406 | li r9, (TM_CAUSE_SYSCALL|TM_CAUSE_PERSISTENT) |
| 407 | TABORT(R9) |
Sam bobroff | b4b56f9 | 2015-06-12 11:06:32 +1000 | [diff] [blame] | 408 | |
| 409 | /* |
| 410 | * Return directly to userspace. We have corrupted user register state, |
| 411 | * but userspace will never see that register state. Execution will |
| 412 | * resume after the tbegin of the aborted transaction with the |
| 413 | * checkpointed register state. |
| 414 | */ |
Nicholas Piggin | cc7786d | 2016-07-25 14:26:51 +1000 | [diff] [blame] | 415 | li r9, MSR_RI |
| 416 | andc r10, r10, r9 |
Sam bobroff | b4b56f9 | 2015-06-12 11:06:32 +1000 | [diff] [blame] | 417 | mtmsrd r10, 1 |
| 418 | mtspr SPRN_SRR0, r11 |
| 419 | mtspr SPRN_SRR1, r12 |
Nicholas Piggin | efe8bc0 | 2018-02-22 23:35:44 +1100 | [diff] [blame] | 420 | RFI_TO_USER |
Sam bobroff | b4b56f9 | 2015-06-12 11:06:32 +1000 | [diff] [blame] | 421 | b . /* prevent speculative execution */ |
| 422 | #endif |
| 423 | |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 424 | /* Save non-volatile GPRs, if not already saved. */ |
| 425 | _GLOBAL(save_nvgprs) |
| 426 | ld r11,_TRAP(r1) |
| 427 | andi. r0,r11,1 |
| 428 | beqlr- |
| 429 | SAVE_NVGPRS(r1) |
| 430 | clrrdi r0,r11,1 |
| 431 | std r0,_TRAP(r1) |
| 432 | blr |
| 433 | |
David Woodhouse | 401d1f0 | 2005-11-15 18:52:18 +0000 | [diff] [blame] | 434 | |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 435 | /* |
| 436 | * The sigsuspend and rt_sigsuspend system calls can call do_signal |
| 437 | * and thus put the process into the stopped state where we might |
| 438 | * want to examine its user state with ptrace. Therefore we need |
| 439 | * to save all the nonvolatile registers (r14 - r31) before calling |
| 440 | * the C code. Similarly, fork, vfork and clone need the full |
| 441 | * register state on the stack so that it can be copied to the child. |
| 442 | */ |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 443 | |
| 444 | _GLOBAL(ppc_fork) |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 445 | bl save_nvgprs |
| 446 | bl sys_fork |
Michael Ellerman | 4c3b216 | 2014-12-05 21:16:59 +1100 | [diff] [blame] | 447 | b .Lsyscall_exit |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 448 | |
| 449 | _GLOBAL(ppc_vfork) |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 450 | bl save_nvgprs |
| 451 | bl sys_vfork |
Michael Ellerman | 4c3b216 | 2014-12-05 21:16:59 +1100 | [diff] [blame] | 452 | b .Lsyscall_exit |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 453 | |
| 454 | _GLOBAL(ppc_clone) |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 455 | bl save_nvgprs |
| 456 | bl sys_clone |
Michael Ellerman | 4c3b216 | 2014-12-05 21:16:59 +1100 | [diff] [blame] | 457 | b .Lsyscall_exit |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 458 | |
Paul Mackerras | 1bd7933 | 2006-03-08 13:24:22 +1100 | [diff] [blame] | 459 | _GLOBAL(ppc32_swapcontext) |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 460 | bl save_nvgprs |
| 461 | bl compat_sys_swapcontext |
Michael Ellerman | 4c3b216 | 2014-12-05 21:16:59 +1100 | [diff] [blame] | 462 | b .Lsyscall_exit |
Paul Mackerras | 1bd7933 | 2006-03-08 13:24:22 +1100 | [diff] [blame] | 463 | |
| 464 | _GLOBAL(ppc64_swapcontext) |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 465 | bl save_nvgprs |
| 466 | bl sys_swapcontext |
Michael Ellerman | 4c3b216 | 2014-12-05 21:16:59 +1100 | [diff] [blame] | 467 | b .Lsyscall_exit |
Paul Mackerras | 1bd7933 | 2006-03-08 13:24:22 +1100 | [diff] [blame] | 468 | |
Michael Ellerman | 529d235 | 2015-03-28 21:35:16 +1100 | [diff] [blame] | 469 | _GLOBAL(ppc_switch_endian) |
| 470 | bl save_nvgprs |
| 471 | bl sys_switch_endian |
| 472 | b .Lsyscall_exit |
| 473 | |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 474 | _GLOBAL(ret_from_fork) |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 475 | bl schedule_tail |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 476 | REST_NVGPRS(r1) |
| 477 | li r3,0 |
Michael Ellerman | 4c3b216 | 2014-12-05 21:16:59 +1100 | [diff] [blame] | 478 | b .Lsyscall_exit |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 479 | |
Al Viro | 58254e1 | 2012-09-12 18:32:42 -0400 | [diff] [blame] | 480 | _GLOBAL(ret_from_kernel_thread) |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 481 | bl schedule_tail |
Al Viro | 58254e1 | 2012-09-12 18:32:42 -0400 | [diff] [blame] | 482 | REST_NVGPRS(r1) |
Al Viro | 58254e1 | 2012-09-12 18:32:42 -0400 | [diff] [blame] | 483 | mtlr r14 |
| 484 | mr r3,r15 |
Michael Ellerman | f55d966 | 2016-06-06 22:26:10 +0530 | [diff] [blame] | 485 | #ifdef PPC64_ELF_ABI_v2 |
Anton Blanchard | 7cedd60 | 2014-02-04 16:08:51 +1100 | [diff] [blame] | 486 | mr r12,r14 |
| 487 | #endif |
Al Viro | 58254e1 | 2012-09-12 18:32:42 -0400 | [diff] [blame] | 488 | blrl |
| 489 | li r3,0 |
Michael Ellerman | 4c3b216 | 2014-12-05 21:16:59 +1100 | [diff] [blame] | 490 | b .Lsyscall_exit |
Al Viro | be6abfa | 2012-08-31 15:48:05 -0400 | [diff] [blame] | 491 | |
Michael Ellerman | 98f6ded | 2019-04-11 21:46:15 +1000 | [diff] [blame] | 492 | #ifdef CONFIG_PPC_BOOK3S_64 |
| 493 | |
| 494 | #define FLUSH_COUNT_CACHE \ |
| 495 | 1: nop; \ |
| 496 | patch_site 1b, patch__call_flush_count_cache |
| 497 | |
| 498 | |
| 499 | #define BCCTR_FLUSH .long 0x4c400420 |
| 500 | |
| 501 | .macro nops number |
| 502 | .rept \number |
| 503 | nop |
| 504 | .endr |
| 505 | .endm |
| 506 | |
| 507 | .balign 32 |
| 508 | .global flush_count_cache |
| 509 | flush_count_cache: |
| 510 | /* Save LR into r9 */ |
| 511 | mflr r9 |
| 512 | |
Michael Ellerman | 113408c | 2019-11-13 21:05:41 +1100 | [diff] [blame] | 513 | // Flush the link stack |
Michael Ellerman | 98f6ded | 2019-04-11 21:46:15 +1000 | [diff] [blame] | 514 | .rept 64 |
| 515 | bl .+4 |
| 516 | .endr |
| 517 | b 1f |
| 518 | nops 6 |
| 519 | |
| 520 | .balign 32 |
| 521 | /* Restore LR */ |
| 522 | 1: mtlr r9 |
Michael Ellerman | 113408c | 2019-11-13 21:05:41 +1100 | [diff] [blame] | 523 | |
| 524 | // If we're just flushing the link stack, return here |
| 525 | 3: nop |
| 526 | patch_site 3b patch__flush_link_stack_return |
| 527 | |
Michael Ellerman | 98f6ded | 2019-04-11 21:46:15 +1000 | [diff] [blame] | 528 | li r9,0x7fff |
| 529 | mtctr r9 |
| 530 | |
| 531 | BCCTR_FLUSH |
| 532 | |
| 533 | 2: nop |
| 534 | patch_site 2b patch__flush_count_cache_return |
| 535 | |
| 536 | nops 3 |
| 537 | |
| 538 | .rept 278 |
| 539 | .balign 32 |
| 540 | BCCTR_FLUSH |
| 541 | nops 7 |
| 542 | .endr |
| 543 | |
| 544 | blr |
| 545 | #else |
| 546 | #define FLUSH_COUNT_CACHE |
| 547 | #endif /* CONFIG_PPC_BOOK3S_64 */ |
| 548 | |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 549 | /* |
| 550 | * This routine switches between two different tasks. The process |
| 551 | * state of one is saved on its kernel stack. Then the state |
| 552 | * of the other is restored from its kernel stack. The memory |
| 553 | * management hardware is updated to the second process's state. |
| 554 | * Finally, we can return to the second process, via ret_from_except. |
| 555 | * On entry, r3 points to the THREAD for the current task, r4 |
| 556 | * points to the THREAD for the new task. |
| 557 | * |
| 558 | * Note: there are two ways to get to the "going out" portion |
| 559 | * of this code; either by coming in via the entry (_switch) |
| 560 | * or via "fork" which must set up an environment equivalent |
| 561 | * to the "_switch" path. If you change this you'll have to change |
| 562 | * the fork code also. |
| 563 | * |
| 564 | * The code which creates the new task context is in 'copy_thread' |
Jon Mason | 2ef9481 | 2006-01-23 10:58:20 -0600 | [diff] [blame] | 565 | * in arch/powerpc/kernel/process.c |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 566 | */ |
| 567 | .align 7 |
| 568 | _GLOBAL(_switch) |
| 569 | mflr r0 |
| 570 | std r0,16(r1) |
| 571 | stdu r1,-SWITCH_FRAME_SIZE(r1) |
| 572 | /* r3-r13 are caller saved -- Cort */ |
| 573 | SAVE_8GPRS(14, r1) |
| 574 | SAVE_10GPRS(22, r1) |
Anton Blanchard | 68bfa96 | 2015-10-29 11:43:56 +1100 | [diff] [blame] | 575 | std r0,_NIP(r1) /* Return to switch caller */ |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 576 | mfcr r23 |
| 577 | std r23,_CCR(r1) |
| 578 | std r1,KSP(r3) /* Set old stack pointer */ |
| 579 | |
Michael Ellerman | 98f6ded | 2019-04-11 21:46:15 +1000 | [diff] [blame] | 580 | FLUSH_COUNT_CACHE |
| 581 | |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 582 | #ifdef CONFIG_SMP |
| 583 | /* We need a sync somewhere here to make sure that if the |
| 584 | * previous task gets rescheduled on another CPU, it sees all |
| 585 | * stores it has performed on this one. |
| 586 | */ |
| 587 | sync |
| 588 | #endif /* CONFIG_SMP */ |
| 589 | |
Anton Blanchard | f89451f | 2010-08-11 01:40:27 +0000 | [diff] [blame] | 590 | /* |
| 591 | * If we optimise away the clear of the reservation in system |
| 592 | * calls because we know the CPU tracks the address of the |
| 593 | * reservation, then we need to clear it here to cover the |
| 594 | * case that the kernel context switch path has no larx |
| 595 | * instructions. |
| 596 | */ |
| 597 | BEGIN_FTR_SECTION |
| 598 | ldarx r6,0,r1 |
| 599 | END_FTR_SECTION_IFSET(CPU_FTR_STCX_CHECKS_ADDRESS) |
| 600 | |
Chris Smart | 8a64904 | 2016-04-26 10:28:50 +1000 | [diff] [blame] | 601 | BEGIN_FTR_SECTION |
| 602 | /* |
| 603 | * A cp_abort (copy paste abort) here ensures that when context switching, a |
| 604 | * copy from one process can't leak into the paste of another. |
| 605 | */ |
| 606 | PPC_CP_ABORT |
| 607 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) |
| 608 | |
Michael Neuling | a515348 | 2013-05-29 19:34:27 +0000 | [diff] [blame] | 609 | #ifdef CONFIG_PPC_BOOK3S |
| 610 | /* Cancel all explict user streams as they will have no use after context |
| 611 | * switch and will stop the HW from creating streams itself |
| 612 | */ |
| 613 | DCBT_STOP_ALL_STREAM_IDS(r6) |
| 614 | #endif |
| 615 | |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 616 | addi r6,r4,-THREAD /* Convert THREAD to 'current' */ |
| 617 | std r6,PACACURRENT(r13) /* Set new 'current' */ |
| 618 | |
| 619 | ld r8,KSP(r4) /* new stack pointer */ |
Aneesh Kumar K.V | caca285 | 2016-04-29 23:26:07 +1000 | [diff] [blame] | 620 | #ifdef CONFIG_PPC_STD_MMU_64 |
| 621 | BEGIN_MMU_FTR_SECTION |
| 622 | b 2f |
Aneesh Kumar K.V | 5a25b6f | 2016-07-27 13:19:01 +1000 | [diff] [blame] | 623 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 624 | BEGIN_FTR_SECTION |
| 625 | clrrdi r6,r8,28 /* get its ESID */ |
| 626 | clrrdi r9,r1,28 /* get current sp ESID */ |
Michael Ellerman | 13b3d13 | 2014-07-10 12:29:20 +1000 | [diff] [blame] | 627 | FTR_SECTION_ELSE |
Paul Mackerras | 1189be6 | 2007-10-11 20:37:10 +1000 | [diff] [blame] | 628 | clrrdi r6,r8,40 /* get its 1T ESID */ |
| 629 | clrrdi r9,r1,40 /* get current sp 1T ESID */ |
Michael Ellerman | 13b3d13 | 2014-07-10 12:29:20 +1000 | [diff] [blame] | 630 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_1T_SEGMENT) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 631 | clrldi. r0,r6,2 /* is new ESID c00000000? */ |
| 632 | cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */ |
| 633 | cror eq,4*cr1+eq,eq |
| 634 | beq 2f /* if yes, don't slbie it */ |
| 635 | |
| 636 | /* Bolt in the new stack SLB entry */ |
| 637 | ld r7,KSP_VSID(r4) /* Get new stack's VSID */ |
| 638 | oris r0,r6,(SLB_ESID_V)@h |
| 639 | ori r0,r0,(SLB_NUM_BOLTED-1)@l |
Paul Mackerras | 1189be6 | 2007-10-11 20:37:10 +1000 | [diff] [blame] | 640 | BEGIN_FTR_SECTION |
| 641 | li r9,MMU_SEGSIZE_1T /* insert B field */ |
| 642 | oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h |
| 643 | rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0 |
Matt Evans | 44ae3ab | 2011-04-06 19:48:50 +0000 | [diff] [blame] | 644 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT) |
Michael Neuling | 2f6093c | 2006-08-07 16:19:19 +1000 | [diff] [blame] | 645 | |
Michael Neuling | 00efee7 | 2007-08-24 16:58:37 +1000 | [diff] [blame] | 646 | /* Update the last bolted SLB. No write barriers are needed |
| 647 | * here, provided we only update the current CPU's SLB shadow |
| 648 | * buffer. |
| 649 | */ |
Michael Neuling | 2f6093c | 2006-08-07 16:19:19 +1000 | [diff] [blame] | 650 | ld r9,PACA_SLBSHADOWPTR(r13) |
Michael Neuling | 11a27ad | 2006-08-09 17:00:30 +1000 | [diff] [blame] | 651 | li r12,0 |
Anton Blanchard | 7ffcf8e | 2013-08-07 02:01:46 +1000 | [diff] [blame] | 652 | std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */ |
| 653 | li r12,SLBSHADOW_STACKVSID |
| 654 | STDX_BE r7,r12,r9 /* Save VSID */ |
| 655 | li r12,SLBSHADOW_STACKESID |
| 656 | STDX_BE r0,r12,r9 /* Save ESID */ |
Michael Neuling | 2f6093c | 2006-08-07 16:19:19 +1000 | [diff] [blame] | 657 | |
Matt Evans | 44ae3ab | 2011-04-06 19:48:50 +0000 | [diff] [blame] | 658 | /* No need to check for MMU_FTR_NO_SLBIE_B here, since when |
Olof Johansson | f66bce5 | 2007-10-16 00:58:59 +1000 | [diff] [blame] | 659 | * we have 1TB segments, the only CPUs known to have the errata |
| 660 | * only support less than 1TB of system memory and we'll never |
| 661 | * actually hit this code path. |
| 662 | */ |
| 663 | |
Aneesh Kumar K.V | 10e4604 | 2018-05-30 18:48:04 +0530 | [diff] [blame] | 664 | isync |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 665 | slbie r6 |
| 666 | slbie r6 /* Workaround POWER5 < DD2.1 issue */ |
| 667 | slbmte r7,r0 |
| 668 | isync |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 669 | 2: |
Aneesh Kumar K.V | caca285 | 2016-04-29 23:26:07 +1000 | [diff] [blame] | 670 | #endif /* CONFIG_PPC_STD_MMU_64 */ |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 671 | |
Stuart Yoder | 9778b69 | 2012-07-05 04:41:35 +0000 | [diff] [blame] | 672 | CURRENT_THREAD_INFO(r7, r8) /* base of new stack */ |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 673 | /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE |
| 674 | because we don't need to leave the 288-byte ABI gap at the |
| 675 | top of the kernel stack. */ |
| 676 | addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE |
| 677 | |
| 678 | mr r1,r8 /* start using new stack pointer */ |
| 679 | std r7,PACAKSAVE(r13) |
| 680 | |
Anton Blanchard | 7143328 | 2012-09-03 16:51:10 +0000 | [diff] [blame] | 681 | ld r6,_CCR(r1) |
| 682 | mtcrf 0xFF,r6 |
| 683 | |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 684 | /* r3-r13 are destroyed -- Cort */ |
| 685 | REST_8GPRS(14, r1) |
| 686 | REST_10GPRS(22, r1) |
| 687 | |
| 688 | /* convert old thread to its task_struct for return value */ |
| 689 | addi r3,r3,-THREAD |
| 690 | ld r7,_NIP(r1) /* Return to _switch caller in new task */ |
| 691 | mtlr r7 |
| 692 | addi r1,r1,SWITCH_FRAME_SIZE |
| 693 | blr |
| 694 | |
| 695 | .align 7 |
| 696 | _GLOBAL(ret_from_except) |
| 697 | ld r11,_TRAP(r1) |
| 698 | andi. r0,r11,1 |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 699 | bne ret_from_except_lite |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 700 | REST_NVGPRS(r1) |
| 701 | |
| 702 | _GLOBAL(ret_from_except_lite) |
| 703 | /* |
| 704 | * Disable interrupts so that current_thread_info()->flags |
| 705 | * can't change between when we test it and when we return |
| 706 | * from the interrupt. |
| 707 | */ |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 708 | #ifdef CONFIG_PPC_BOOK3E |
| 709 | wrteei 0 |
| 710 | #else |
Nicholas Piggin | 49d09bf | 2016-09-15 19:04:46 +1000 | [diff] [blame] | 711 | li r10,MSR_RI |
Benjamin Herrenschmidt | d9ada91 | 2012-03-02 11:33:52 +1100 | [diff] [blame] | 712 | mtmsrd r10,1 /* Update machine state */ |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 713 | #endif /* CONFIG_PPC_BOOK3E */ |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 714 | |
Stuart Yoder | 9778b69 | 2012-07-05 04:41:35 +0000 | [diff] [blame] | 715 | CURRENT_THREAD_INFO(r9, r1) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 716 | ld r3,_MSR(r1) |
Bharat Bhushan | 13d543c | 2013-05-22 09:50:59 +0530 | [diff] [blame] | 717 | #ifdef CONFIG_PPC_BOOK3E |
| 718 | ld r10,PACACURRENT(r13) |
| 719 | #endif /* CONFIG_PPC_BOOK3E */ |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 720 | ld r4,TI_FLAGS(r9) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 721 | andi. r3,r3,MSR_PR |
Tiejun Chen | c58ce2b | 2012-06-06 20:56:43 +0000 | [diff] [blame] | 722 | beq resume_kernel |
Bharat Bhushan | 13d543c | 2013-05-22 09:50:59 +0530 | [diff] [blame] | 723 | #ifdef CONFIG_PPC_BOOK3E |
| 724 | lwz r3,(THREAD+THREAD_DBCR0)(r10) |
| 725 | #endif /* CONFIG_PPC_BOOK3E */ |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 726 | |
| 727 | /* Check current_thread_info()->flags */ |
Tiejun Chen | c58ce2b | 2012-06-06 20:56:43 +0000 | [diff] [blame] | 728 | andi. r0,r4,_TIF_USER_WORK_MASK |
Bharat Bhushan | 13d543c | 2013-05-22 09:50:59 +0530 | [diff] [blame] | 729 | bne 1f |
Cyril Bur | 70fe3d9 | 2016-02-29 17:53:47 +1100 | [diff] [blame] | 730 | #ifdef CONFIG_PPC_BOOK3E |
Bharat Bhushan | 13d543c | 2013-05-22 09:50:59 +0530 | [diff] [blame] | 731 | /* |
| 732 | * Check to see if the dbcr0 register is set up to debug. |
| 733 | * Use the internal debug mode bit to do this. |
| 734 | */ |
| 735 | andis. r0,r3,DBCR0_IDM@h |
Tiejun Chen | c58ce2b | 2012-06-06 20:56:43 +0000 | [diff] [blame] | 736 | beq restore |
Bharat Bhushan | 13d543c | 2013-05-22 09:50:59 +0530 | [diff] [blame] | 737 | mfmsr r0 |
| 738 | rlwinm r0,r0,0,~MSR_DE /* Clear MSR.DE */ |
| 739 | mtmsr r0 |
| 740 | mtspr SPRN_DBCR0,r3 |
| 741 | li r10, -1 |
| 742 | mtspr SPRN_DBSR,r10 |
| 743 | b restore |
| 744 | #else |
Cyril Bur | 70fe3d9 | 2016-02-29 17:53:47 +1100 | [diff] [blame] | 745 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 746 | bl restore_math |
| 747 | b restore |
Bharat Bhushan | 13d543c | 2013-05-22 09:50:59 +0530 | [diff] [blame] | 748 | #endif |
| 749 | 1: andi. r0,r4,_TIF_NEED_RESCHED |
| 750 | beq 2f |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 751 | bl restore_interrupts |
Li Zhong | 5d1c574 | 2013-05-13 16:16:43 +0000 | [diff] [blame] | 752 | SCHEDULE_USER |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 753 | b ret_from_except_lite |
Paul Mackerras | d31626f | 2014-01-13 15:56:29 +1100 | [diff] [blame] | 754 | 2: |
| 755 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
| 756 | andi. r0,r4,_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM |
| 757 | bne 3f /* only restore TM if nothing else to do */ |
| 758 | addi r3,r1,STACK_FRAME_OVERHEAD |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 759 | bl restore_tm_state |
Paul Mackerras | d31626f | 2014-01-13 15:56:29 +1100 | [diff] [blame] | 760 | b restore |
| 761 | 3: |
| 762 | #endif |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 763 | bl save_nvgprs |
Anton Blanchard | 808be31 | 2014-10-31 16:50:57 +1100 | [diff] [blame] | 764 | /* |
| 765 | * Use a non volatile GPR to save and restore our thread_info flags |
| 766 | * across the call to restore_interrupts. |
| 767 | */ |
| 768 | mr r30,r4 |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 769 | bl restore_interrupts |
Anton Blanchard | 808be31 | 2014-10-31 16:50:57 +1100 | [diff] [blame] | 770 | mr r4,r30 |
Tiejun Chen | c58ce2b | 2012-06-06 20:56:43 +0000 | [diff] [blame] | 771 | addi r3,r1,STACK_FRAME_OVERHEAD |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 772 | bl do_notify_resume |
| 773 | b ret_from_except |
Tiejun Chen | c58ce2b | 2012-06-06 20:56:43 +0000 | [diff] [blame] | 774 | |
| 775 | resume_kernel: |
Tiejun Chen | a9c4e54 | 2012-09-16 23:54:30 +0000 | [diff] [blame] | 776 | /* check current_thread_info, _TIF_EMULATE_STACK_STORE */ |
Kevin Hao | 0edfdd1 | 2013-09-26 16:41:34 +0800 | [diff] [blame] | 777 | andis. r8,r4,_TIF_EMULATE_STACK_STORE@h |
Tiejun Chen | a9c4e54 | 2012-09-16 23:54:30 +0000 | [diff] [blame] | 778 | beq+ 1f |
| 779 | |
| 780 | addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */ |
| 781 | |
Ravi Bangoria | 1bd55ab | 2017-04-11 10:38:13 +0530 | [diff] [blame] | 782 | ld r3,GPR1(r1) |
Tiejun Chen | a9c4e54 | 2012-09-16 23:54:30 +0000 | [diff] [blame] | 783 | subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */ |
| 784 | mr r4,r1 /* src: current exception frame */ |
| 785 | mr r1,r3 /* Reroute the trampoline frame to r1 */ |
| 786 | |
| 787 | /* Copy from the original to the trampoline. */ |
| 788 | li r5,INT_FRAME_SIZE/8 /* size: INT_FRAME_SIZE */ |
| 789 | li r6,0 /* start offset: 0 */ |
| 790 | mtctr r5 |
| 791 | 2: ldx r0,r6,r4 |
| 792 | stdx r0,r6,r3 |
| 793 | addi r6,r6,8 |
| 794 | bdnz 2b |
| 795 | |
Ravi Bangoria | 1bd55ab | 2017-04-11 10:38:13 +0530 | [diff] [blame] | 796 | /* Do real store operation to complete stdu */ |
| 797 | ld r5,GPR1(r1) |
Tiejun Chen | a9c4e54 | 2012-09-16 23:54:30 +0000 | [diff] [blame] | 798 | std r8,0(r5) |
| 799 | |
| 800 | /* Clear _TIF_EMULATE_STACK_STORE flag */ |
| 801 | lis r11,_TIF_EMULATE_STACK_STORE@h |
| 802 | addi r5,r9,TI_FLAGS |
Kevin Hao | d8b9229 | 2013-04-09 22:31:24 +0000 | [diff] [blame] | 803 | 0: ldarx r4,0,r5 |
Tiejun Chen | a9c4e54 | 2012-09-16 23:54:30 +0000 | [diff] [blame] | 804 | andc r4,r4,r11 |
| 805 | stdcx. r4,0,r5 |
| 806 | bne- 0b |
| 807 | 1: |
| 808 | |
Tiejun Chen | c58ce2b | 2012-06-06 20:56:43 +0000 | [diff] [blame] | 809 | #ifdef CONFIG_PREEMPT |
| 810 | /* Check if we need to preempt */ |
| 811 | andi. r0,r4,_TIF_NEED_RESCHED |
| 812 | beq+ restore |
| 813 | /* Check that preempt_count() == 0 and interrupts are enabled */ |
| 814 | lwz r8,TI_PREEMPT(r9) |
| 815 | cmpwi cr1,r8,0 |
| 816 | ld r0,SOFTE(r1) |
| 817 | cmpdi r0,0 |
| 818 | crandc eq,cr1*4+eq,eq |
| 819 | bne restore |
| 820 | |
| 821 | /* |
| 822 | * Here we are preempting the current task. We want to make |
Tiejun Chen | de021bb | 2013-07-16 11:09:30 +0800 | [diff] [blame] | 823 | * sure we are soft-disabled first and reconcile irq state. |
Tiejun Chen | c58ce2b | 2012-06-06 20:56:43 +0000 | [diff] [blame] | 824 | */ |
Tiejun Chen | de021bb | 2013-07-16 11:09:30 +0800 | [diff] [blame] | 825 | RECONCILE_IRQ_STATE(r3,r4) |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 826 | 1: bl preempt_schedule_irq |
Tiejun Chen | c58ce2b | 2012-06-06 20:56:43 +0000 | [diff] [blame] | 827 | |
| 828 | /* Re-test flags and eventually loop */ |
Stuart Yoder | 9778b69 | 2012-07-05 04:41:35 +0000 | [diff] [blame] | 829 | CURRENT_THREAD_INFO(r9, r1) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 830 | ld r4,TI_FLAGS(r9) |
Tiejun Chen | c58ce2b | 2012-06-06 20:56:43 +0000 | [diff] [blame] | 831 | andi. r0,r4,_TIF_NEED_RESCHED |
| 832 | bne 1b |
Tiejun Chen | 572177d | 2013-01-06 00:49:34 +0000 | [diff] [blame] | 833 | |
| 834 | /* |
| 835 | * arch_local_irq_restore() from preempt_schedule_irq above may |
| 836 | * enable hard interrupt but we really should disable interrupts |
| 837 | * when we return from the interrupt, and so that we don't get |
| 838 | * interrupted after loading SRR0/1. |
| 839 | */ |
| 840 | #ifdef CONFIG_PPC_BOOK3E |
| 841 | wrteei 0 |
| 842 | #else |
Nicholas Piggin | 49d09bf | 2016-09-15 19:04:46 +1000 | [diff] [blame] | 843 | li r10,MSR_RI |
Tiejun Chen | 572177d | 2013-01-06 00:49:34 +0000 | [diff] [blame] | 844 | mtmsrd r10,1 /* Update machine state */ |
| 845 | #endif /* CONFIG_PPC_BOOK3E */ |
Tiejun Chen | c58ce2b | 2012-06-06 20:56:43 +0000 | [diff] [blame] | 846 | #endif /* CONFIG_PREEMPT */ |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 847 | |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 848 | .globl fast_exc_return_irq |
| 849 | fast_exc_return_irq: |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 850 | restore: |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 851 | /* |
Benjamin Herrenschmidt | 7c0482e | 2012-05-10 16:12:38 +0000 | [diff] [blame] | 852 | * This is the main kernel exit path. First we check if we |
| 853 | * are about to re-enable interrupts |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 854 | */ |
Michael Ellerman | 01f3880d | 2008-07-16 14:21:34 +1000 | [diff] [blame] | 855 | ld r5,SOFTE(r1) |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 856 | lbz r6,PACASOFTIRQEN(r13) |
Benjamin Herrenschmidt | 7c0482e | 2012-05-10 16:12:38 +0000 | [diff] [blame] | 857 | cmpwi cr0,r5,0 |
| 858 | beq restore_irq_off |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 859 | |
Benjamin Herrenschmidt | 7c0482e | 2012-05-10 16:12:38 +0000 | [diff] [blame] | 860 | /* We are enabling, were we already enabled ? Yes, just return */ |
| 861 | cmpwi cr0,r6,1 |
| 862 | beq cr0,do_restore |
Paul Mackerras | b0a779d | 2006-10-18 10:11:22 +1000 | [diff] [blame] | 863 | |
Benjamin Herrenschmidt | 7c0482e | 2012-05-10 16:12:38 +0000 | [diff] [blame] | 864 | /* |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 865 | * We are about to soft-enable interrupts (we are hard disabled |
| 866 | * at this point). We check if there's anything that needs to |
| 867 | * be replayed first. |
| 868 | */ |
| 869 | lbz r0,PACAIRQHAPPENED(r13) |
| 870 | cmpwi cr0,r0,0 |
| 871 | bne- restore_check_irq_replay |
| 872 | |
| 873 | /* |
| 874 | * Get here when nothing happened while soft-disabled, just |
| 875 | * soft-enable and move-on. We will hard-enable as a side |
| 876 | * effect of rfi |
| 877 | */ |
| 878 | restore_no_replay: |
| 879 | TRACE_ENABLE_INTS |
| 880 | li r0,1 |
| 881 | stb r0,PACASOFTIRQEN(r13); |
| 882 | |
| 883 | /* |
| 884 | * Final return path. BookE is handled in a different file |
| 885 | */ |
Benjamin Herrenschmidt | 7c0482e | 2012-05-10 16:12:38 +0000 | [diff] [blame] | 886 | do_restore: |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 887 | #ifdef CONFIG_PPC_BOOK3E |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 888 | b exception_return_book3e |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 889 | #else |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 890 | /* |
| 891 | * Clear the reservation. If we know the CPU tracks the address of |
| 892 | * the reservation then we can potentially save some cycles and use |
| 893 | * a larx. On POWER6 and POWER7 this is significantly faster. |
| 894 | */ |
| 895 | BEGIN_FTR_SECTION |
| 896 | stdcx. r0,0,r1 /* to clear the reservation */ |
| 897 | FTR_SECTION_ELSE |
| 898 | ldarx r4,0,r1 |
| 899 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS) |
| 900 | |
| 901 | /* |
| 902 | * Some code path such as load_up_fpu or altivec return directly |
| 903 | * here. They run entirely hard disabled and do not alter the |
| 904 | * interrupt state. They also don't use lwarx/stwcx. and thus |
| 905 | * are known not to leave dangling reservations. |
| 906 | */ |
| 907 | .globl fast_exception_return |
| 908 | fast_exception_return: |
| 909 | ld r3,_MSR(r1) |
Paul Mackerras | e56a6e2 | 2007-02-07 13:13:26 +1100 | [diff] [blame] | 910 | ld r4,_CTR(r1) |
| 911 | ld r0,_LINK(r1) |
| 912 | mtctr r4 |
| 913 | mtlr r0 |
| 914 | ld r4,_XER(r1) |
| 915 | mtspr SPRN_XER,r4 |
| 916 | |
| 917 | REST_8GPRS(5, r1) |
| 918 | |
| 919 | andi. r0,r3,MSR_RI |
| 920 | beq- unrecov_restore |
| 921 | |
Benjamin Herrenschmidt | 0c4888e | 2013-11-05 16:33:22 +1100 | [diff] [blame] | 922 | /* Load PPR from thread struct before we clear MSR:RI */ |
| 923 | BEGIN_FTR_SECTION |
| 924 | ld r2,PACACURRENT(r13) |
| 925 | ld r2,TASKTHREADPPR(r2) |
| 926 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) |
| 927 | |
Anton Blanchard | f89451f | 2010-08-11 01:40:27 +0000 | [diff] [blame] | 928 | /* |
Paul Mackerras | e56a6e2 | 2007-02-07 13:13:26 +1100 | [diff] [blame] | 929 | * Clear RI before restoring r13. If we are returning to |
| 930 | * userspace and we take an exception after restoring r13, |
| 931 | * we end up corrupting the userspace r13 value. |
| 932 | */ |
Nicholas Piggin | 49d09bf | 2016-09-15 19:04:46 +1000 | [diff] [blame] | 933 | li r4,0 |
Paul Mackerras | e56a6e2 | 2007-02-07 13:13:26 +1100 | [diff] [blame] | 934 | mtmsrd r4,1 |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 935 | |
Michael Neuling | afc0770 | 2013-02-13 16:21:34 +0000 | [diff] [blame] | 936 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
| 937 | /* TM debug */ |
| 938 | std r3, PACATMSCRATCH(r13) /* Stash returned-to MSR */ |
| 939 | #endif |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 940 | /* |
| 941 | * r13 is our per cpu area, only restore it if we are returning to |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 942 | * userspace the value stored in the stack frame may belong to |
| 943 | * another CPU. |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 944 | */ |
Paul Mackerras | e56a6e2 | 2007-02-07 13:13:26 +1100 | [diff] [blame] | 945 | andi. r0,r3,MSR_PR |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 946 | beq 1f |
Benjamin Herrenschmidt | 0c4888e | 2013-11-05 16:33:22 +1100 | [diff] [blame] | 947 | BEGIN_FTR_SECTION |
| 948 | mtspr SPRN_PPR,r2 /* Restore PPR */ |
| 949 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) |
Christophe Leroy | c223c90 | 2016-05-17 08:33:46 +0200 | [diff] [blame] | 950 | ACCOUNT_CPU_USER_EXIT(r13, r2, r4) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 951 | REST_GPR(13, r1) |
Nicholas Piggin | 9d91432 | 2018-01-10 03:07:15 +1100 | [diff] [blame] | 952 | |
Paul Mackerras | e56a6e2 | 2007-02-07 13:13:26 +1100 | [diff] [blame] | 953 | mtspr SPRN_SRR1,r3 |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 954 | |
| 955 | ld r2,_CCR(r1) |
| 956 | mtcrf 0xFF,r2 |
| 957 | ld r2,_NIP(r1) |
| 958 | mtspr SPRN_SRR0,r2 |
| 959 | |
| 960 | ld r0,GPR0(r1) |
| 961 | ld r2,GPR2(r1) |
| 962 | ld r3,GPR3(r1) |
| 963 | ld r4,GPR4(r1) |
| 964 | ld r1,GPR1(r1) |
Nicholas Piggin | 9d91432 | 2018-01-10 03:07:15 +1100 | [diff] [blame] | 965 | RFI_TO_USER |
| 966 | b . /* prevent speculative execution */ |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 967 | |
Nicholas Piggin | 9d91432 | 2018-01-10 03:07:15 +1100 | [diff] [blame] | 968 | 1: mtspr SPRN_SRR1,r3 |
| 969 | |
| 970 | ld r2,_CCR(r1) |
| 971 | mtcrf 0xFF,r2 |
| 972 | ld r2,_NIP(r1) |
| 973 | mtspr SPRN_SRR0,r2 |
| 974 | |
| 975 | ld r0,GPR0(r1) |
| 976 | ld r2,GPR2(r1) |
| 977 | ld r3,GPR3(r1) |
| 978 | ld r4,GPR4(r1) |
| 979 | ld r1,GPR1(r1) |
| 980 | RFI_TO_KERNEL |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 981 | b . /* prevent speculative execution */ |
| 982 | |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 983 | #endif /* CONFIG_PPC_BOOK3E */ |
| 984 | |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 985 | /* |
Benjamin Herrenschmidt | 7c0482e | 2012-05-10 16:12:38 +0000 | [diff] [blame] | 986 | * We are returning to a context with interrupts soft disabled. |
| 987 | * |
| 988 | * However, we may also about to hard enable, so we need to |
| 989 | * make sure that in this case, we also clear PACA_IRQ_HARD_DIS |
| 990 | * or that bit can get out of sync and bad things will happen |
| 991 | */ |
| 992 | restore_irq_off: |
| 993 | ld r3,_MSR(r1) |
| 994 | lbz r7,PACAIRQHAPPENED(r13) |
| 995 | andi. r0,r3,MSR_EE |
| 996 | beq 1f |
| 997 | rlwinm r7,r7,0,~PACA_IRQ_HARD_DIS |
| 998 | stb r7,PACAIRQHAPPENED(r13) |
| 999 | 1: li r0,0 |
| 1000 | stb r0,PACASOFTIRQEN(r13); |
| 1001 | TRACE_DISABLE_INTS |
| 1002 | b do_restore |
| 1003 | |
| 1004 | /* |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 1005 | * Something did happen, check if a re-emit is needed |
| 1006 | * (this also clears paca->irq_happened) |
| 1007 | */ |
| 1008 | restore_check_irq_replay: |
| 1009 | /* XXX: We could implement a fast path here where we check |
| 1010 | * for irq_happened being just 0x01, in which case we can |
| 1011 | * clear it and return. That means that we would potentially |
| 1012 | * miss a decrementer having wrapped all the way around. |
| 1013 | * |
| 1014 | * Still, this might be useful for things like hash_page |
| 1015 | */ |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1016 | bl __check_irq_replay |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 1017 | cmpwi cr0,r3,0 |
| 1018 | beq restore_no_replay |
| 1019 | |
| 1020 | /* |
| 1021 | * We need to re-emit an interrupt. We do so by re-using our |
| 1022 | * existing exception frame. We first change the trap value, |
| 1023 | * but we need to ensure we preserve the low nibble of it |
| 1024 | */ |
| 1025 | ld r4,_TRAP(r1) |
| 1026 | clrldi r4,r4,60 |
| 1027 | or r4,r4,r3 |
| 1028 | std r4,_TRAP(r1) |
| 1029 | |
| 1030 | /* |
| 1031 | * Then find the right handler and call it. Interrupts are |
| 1032 | * still soft-disabled and we keep them that way. |
| 1033 | */ |
| 1034 | cmpwi cr0,r3,0x500 |
| 1035 | bne 1f |
| 1036 | addi r3,r1,STACK_FRAME_OVERHEAD; |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1037 | bl do_IRQ |
| 1038 | b ret_from_except |
Mahesh Salgaonkar | 0869b6f | 2014-07-29 18:40:01 +0530 | [diff] [blame] | 1039 | 1: cmpwi cr0,r3,0xe60 |
| 1040 | bne 1f |
| 1041 | addi r3,r1,STACK_FRAME_OVERHEAD; |
| 1042 | bl handle_hmi_exception |
| 1043 | b ret_from_except |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 1044 | 1: cmpwi cr0,r3,0x900 |
| 1045 | bne 1f |
| 1046 | addi r3,r1,STACK_FRAME_OVERHEAD; |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1047 | bl timer_interrupt |
| 1048 | b ret_from_except |
Ian Munsie | fe9e1d5 | 2012-11-14 18:49:48 +0000 | [diff] [blame] | 1049 | #ifdef CONFIG_PPC_DOORBELL |
| 1050 | 1: |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 1051 | #ifdef CONFIG_PPC_BOOK3E |
Ian Munsie | fe9e1d5 | 2012-11-14 18:49:48 +0000 | [diff] [blame] | 1052 | cmpwi cr0,r3,0x280 |
| 1053 | #else |
| 1054 | BEGIN_FTR_SECTION |
| 1055 | cmpwi cr0,r3,0xe80 |
| 1056 | FTR_SECTION_ELSE |
| 1057 | cmpwi cr0,r3,0xa00 |
| 1058 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
| 1059 | #endif /* CONFIG_PPC_BOOK3E */ |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 1060 | bne 1f |
| 1061 | addi r3,r1,STACK_FRAME_OVERHEAD; |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1062 | bl doorbell_exception |
| 1063 | b ret_from_except |
Ian Munsie | fe9e1d5 | 2012-11-14 18:49:48 +0000 | [diff] [blame] | 1064 | #endif /* CONFIG_PPC_DOORBELL */ |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1065 | 1: b ret_from_except /* What else to do here ? */ |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 1066 | |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1067 | unrecov_restore: |
| 1068 | addi r3,r1,STACK_FRAME_OVERHEAD |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1069 | bl unrecoverable_exception |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1070 | b unrecov_restore |
| 1071 | |
| 1072 | #ifdef CONFIG_PPC_RTAS |
| 1073 | /* |
| 1074 | * On CHRP, the Run-Time Abstraction Services (RTAS) have to be |
| 1075 | * called with the MMU off. |
| 1076 | * |
| 1077 | * In addition, we need to be in 32b mode, at least for now. |
| 1078 | * |
| 1079 | * Note: r3 is an input parameter to rtas, so don't trash it... |
| 1080 | */ |
| 1081 | _GLOBAL(enter_rtas) |
| 1082 | mflr r0 |
| 1083 | std r0,16(r1) |
| 1084 | stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */ |
| 1085 | |
| 1086 | /* Because RTAS is running in 32b mode, it clobbers the high order half |
| 1087 | * of all registers that it saves. We therefore save those registers |
| 1088 | * RTAS might touch to the stack. (r0, r3-r13 are caller saved) |
| 1089 | */ |
| 1090 | SAVE_GPR(2, r1) /* Save the TOC */ |
| 1091 | SAVE_GPR(13, r1) /* Save paca */ |
| 1092 | SAVE_8GPRS(14, r1) /* Save the non-volatiles */ |
| 1093 | SAVE_10GPRS(22, r1) /* ditto */ |
| 1094 | |
| 1095 | mfcr r4 |
| 1096 | std r4,_CCR(r1) |
| 1097 | mfctr r5 |
| 1098 | std r5,_CTR(r1) |
| 1099 | mfspr r6,SPRN_XER |
| 1100 | std r6,_XER(r1) |
| 1101 | mfdar r7 |
| 1102 | std r7,_DAR(r1) |
| 1103 | mfdsisr r8 |
| 1104 | std r8,_DSISR(r1) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1105 | |
Mike Kravetz | 9fe901d | 2006-03-27 15:20:00 -0800 | [diff] [blame] | 1106 | /* Temporary workaround to clear CR until RTAS can be modified to |
| 1107 | * ignore all bits. |
| 1108 | */ |
| 1109 | li r0,0 |
| 1110 | mtcr r0 |
| 1111 | |
David Woodhouse | 007d88d | 2007-01-01 18:45:34 +0000 | [diff] [blame] | 1112 | #ifdef CONFIG_BUG |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1113 | /* There is no way it is acceptable to get here with interrupts enabled, |
| 1114 | * check it with the asm equivalent of WARN_ON |
| 1115 | */ |
Paul Mackerras | d04c56f | 2006-10-04 16:47:49 +1000 | [diff] [blame] | 1116 | lbz r0,PACASOFTIRQEN(r13) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1117 | 1: tdnei r0,0 |
David Woodhouse | 007d88d | 2007-01-01 18:45:34 +0000 | [diff] [blame] | 1118 | EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING |
| 1119 | #endif |
| 1120 | |
Paul Mackerras | d04c56f | 2006-10-04 16:47:49 +1000 | [diff] [blame] | 1121 | /* Hard-disable interrupts */ |
| 1122 | mfmsr r6 |
| 1123 | rldicl r7,r6,48,1 |
| 1124 | rotldi r7,r7,16 |
| 1125 | mtmsrd r7,1 |
| 1126 | |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1127 | /* Unfortunately, the stack pointer and the MSR are also clobbered, |
| 1128 | * so they are saved in the PACA which allows us to restore |
| 1129 | * our original state after RTAS returns. |
| 1130 | */ |
| 1131 | std r1,PACAR1(r13) |
| 1132 | std r6,PACASAVEDMSR(r13) |
| 1133 | |
| 1134 | /* Setup our real return addr */ |
Anton Blanchard | ad0289e | 2014-02-04 16:04:52 +1100 | [diff] [blame] | 1135 | LOAD_REG_ADDR(r4,rtas_return_loc) |
David Gibson | e58c349 | 2006-01-13 14:56:25 +1100 | [diff] [blame] | 1136 | clrldi r4,r4,2 /* convert to realmode address */ |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1137 | mtlr r4 |
| 1138 | |
| 1139 | li r0,0 |
| 1140 | ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI |
| 1141 | andc r0,r6,r0 |
| 1142 | |
| 1143 | li r9,1 |
| 1144 | rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG) |
Benjamin Herrenschmidt | 5c0484e | 2013-09-23 12:04:45 +1000 | [diff] [blame] | 1145 | ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI|MSR_LE |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1146 | andc r6,r0,r9 |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1147 | sync /* disable interrupts so SRR0/1 */ |
| 1148 | mtmsrd r0 /* don't get trashed */ |
| 1149 | |
David Gibson | e58c349 | 2006-01-13 14:56:25 +1100 | [diff] [blame] | 1150 | LOAD_REG_ADDR(r4, rtas) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1151 | ld r5,RTASENTRY(r4) /* get the rtas->entry value */ |
| 1152 | ld r4,RTASBASE(r4) /* get the rtas->base value */ |
| 1153 | |
| 1154 | mtspr SPRN_SRR0,r5 |
| 1155 | mtspr SPRN_SRR1,r6 |
Nicholas Piggin | efe8bc0 | 2018-02-22 23:35:44 +1100 | [diff] [blame] | 1156 | RFI_TO_KERNEL |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1157 | b . /* prevent speculative execution */ |
| 1158 | |
Anton Blanchard | ad0289e | 2014-02-04 16:04:52 +1100 | [diff] [blame] | 1159 | rtas_return_loc: |
Benjamin Herrenschmidt | 5c0484e | 2013-09-23 12:04:45 +1000 | [diff] [blame] | 1160 | FIXUP_ENDIAN |
| 1161 | |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1162 | /* relocation is off at this point */ |
Benjamin Herrenschmidt | 2dd60d7 | 2011-01-20 17:50:21 +1100 | [diff] [blame] | 1163 | GET_PACA(r4) |
David Gibson | e58c349 | 2006-01-13 14:56:25 +1100 | [diff] [blame] | 1164 | clrldi r4,r4,2 /* convert to realmode address */ |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1165 | |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 1166 | bcl 20,31,$+4 |
| 1167 | 0: mflr r3 |
Anton Blanchard | ad0289e | 2014-02-04 16:04:52 +1100 | [diff] [blame] | 1168 | ld r3,(1f-0b)(r3) /* get &rtas_restore_regs */ |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 1169 | |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1170 | mfmsr r6 |
| 1171 | li r0,MSR_RI |
| 1172 | andc r6,r6,r0 |
| 1173 | sync |
| 1174 | mtmsrd r6 |
| 1175 | |
| 1176 | ld r1,PACAR1(r4) /* Restore our SP */ |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1177 | ld r4,PACASAVEDMSR(r4) /* Restore our MSR */ |
| 1178 | |
| 1179 | mtspr SPRN_SRR0,r3 |
| 1180 | mtspr SPRN_SRR1,r4 |
Nicholas Piggin | efe8bc0 | 2018-02-22 23:35:44 +1100 | [diff] [blame] | 1181 | RFI_TO_KERNEL |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1182 | b . /* prevent speculative execution */ |
| 1183 | |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 1184 | .align 3 |
Anton Blanchard | ad0289e | 2014-02-04 16:04:52 +1100 | [diff] [blame] | 1185 | 1: .llong rtas_restore_regs |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 1186 | |
Anton Blanchard | ad0289e | 2014-02-04 16:04:52 +1100 | [diff] [blame] | 1187 | rtas_restore_regs: |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1188 | /* relocation is on at this point */ |
| 1189 | REST_GPR(2, r1) /* Restore the TOC */ |
| 1190 | REST_GPR(13, r1) /* Restore paca */ |
| 1191 | REST_8GPRS(14, r1) /* Restore the non-volatiles */ |
| 1192 | REST_10GPRS(22, r1) /* ditto */ |
| 1193 | |
Benjamin Herrenschmidt | 2dd60d7 | 2011-01-20 17:50:21 +1100 | [diff] [blame] | 1194 | GET_PACA(r13) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1195 | |
| 1196 | ld r4,_CCR(r1) |
| 1197 | mtcr r4 |
| 1198 | ld r5,_CTR(r1) |
| 1199 | mtctr r5 |
| 1200 | ld r6,_XER(r1) |
| 1201 | mtspr SPRN_XER,r6 |
| 1202 | ld r7,_DAR(r1) |
| 1203 | mtdar r7 |
| 1204 | ld r8,_DSISR(r1) |
| 1205 | mtdsisr r8 |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1206 | |
| 1207 | addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */ |
| 1208 | ld r0,16(r1) /* get return address */ |
| 1209 | |
| 1210 | mtlr r0 |
| 1211 | blr /* return to caller */ |
| 1212 | |
| 1213 | #endif /* CONFIG_PPC_RTAS */ |
| 1214 | |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1215 | _GLOBAL(enter_prom) |
| 1216 | mflr r0 |
| 1217 | std r0,16(r1) |
| 1218 | stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */ |
| 1219 | |
| 1220 | /* Because PROM is running in 32b mode, it clobbers the high order half |
| 1221 | * of all registers that it saves. We therefore save those registers |
| 1222 | * PROM might touch to the stack. (r0, r3-r13 are caller saved) |
| 1223 | */ |
Benjamin Herrenschmidt | 6c17199 | 2009-07-23 23:15:07 +0000 | [diff] [blame] | 1224 | SAVE_GPR(2, r1) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1225 | SAVE_GPR(13, r1) |
| 1226 | SAVE_8GPRS(14, r1) |
| 1227 | SAVE_10GPRS(22, r1) |
Benjamin Herrenschmidt | 6c17199 | 2009-07-23 23:15:07 +0000 | [diff] [blame] | 1228 | mfcr r10 |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1229 | mfmsr r11 |
Benjamin Herrenschmidt | 6c17199 | 2009-07-23 23:15:07 +0000 | [diff] [blame] | 1230 | std r10,_CCR(r1) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1231 | std r11,_MSR(r1) |
| 1232 | |
Benjamin Herrenschmidt | 5c0484e | 2013-09-23 12:04:45 +1000 | [diff] [blame] | 1233 | /* Put PROM address in SRR0 */ |
| 1234 | mtsrr0 r4 |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1235 | |
Benjamin Herrenschmidt | 5c0484e | 2013-09-23 12:04:45 +1000 | [diff] [blame] | 1236 | /* Setup our trampoline return addr in LR */ |
| 1237 | bcl 20,31,$+4 |
| 1238 | 0: mflr r4 |
| 1239 | addi r4,r4,(1f - 0b) |
| 1240 | mtlr r4 |
| 1241 | |
| 1242 | /* Prepare a 32-bit mode big endian MSR |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1243 | */ |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 1244 | #ifdef CONFIG_PPC_BOOK3E |
| 1245 | rlwinm r11,r11,0,1,31 |
Benjamin Herrenschmidt | 5c0484e | 2013-09-23 12:04:45 +1000 | [diff] [blame] | 1246 | mtsrr1 r11 |
| 1247 | rfi |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 1248 | #else /* CONFIG_PPC_BOOK3E */ |
Benjamin Herrenschmidt | 5c0484e | 2013-09-23 12:04:45 +1000 | [diff] [blame] | 1249 | LOAD_REG_IMMEDIATE(r12, MSR_SF | MSR_ISF | MSR_LE) |
| 1250 | andc r11,r11,r12 |
| 1251 | mtsrr1 r11 |
Nicholas Piggin | efe8bc0 | 2018-02-22 23:35:44 +1100 | [diff] [blame] | 1252 | RFI_TO_KERNEL |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 1253 | #endif /* CONFIG_PPC_BOOK3E */ |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1254 | |
Benjamin Herrenschmidt | 5c0484e | 2013-09-23 12:04:45 +1000 | [diff] [blame] | 1255 | 1: /* Return from OF */ |
| 1256 | FIXUP_ENDIAN |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1257 | |
| 1258 | /* Just make sure that r1 top 32 bits didn't get |
| 1259 | * corrupt by OF |
| 1260 | */ |
| 1261 | rldicl r1,r1,0,32 |
| 1262 | |
| 1263 | /* Restore the MSR (back to 64 bits) */ |
| 1264 | ld r0,_MSR(r1) |
Benjamin Herrenschmidt | 6c17199 | 2009-07-23 23:15:07 +0000 | [diff] [blame] | 1265 | MTMSRD(r0) |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1266 | isync |
| 1267 | |
| 1268 | /* Restore other registers */ |
| 1269 | REST_GPR(2, r1) |
| 1270 | REST_GPR(13, r1) |
| 1271 | REST_8GPRS(14, r1) |
| 1272 | REST_10GPRS(22, r1) |
| 1273 | ld r4,_CCR(r1) |
| 1274 | mtcr r4 |
Paul Mackerras | 9994a33 | 2005-10-10 22:36:14 +1000 | [diff] [blame] | 1275 | |
| 1276 | addi r1,r1,PROM_FRAME_SIZE |
| 1277 | ld r0,16(r1) |
| 1278 | mtlr r0 |
| 1279 | blr |
Steven Rostedt | 4e491d1 | 2008-05-14 23:49:44 -0400 | [diff] [blame] | 1280 | |
Steven Rostedt | 606576c | 2008-10-06 19:06:12 -0400 | [diff] [blame] | 1281 | #ifdef CONFIG_FUNCTION_TRACER |
Steven Rostedt | 4e491d1 | 2008-05-14 23:49:44 -0400 | [diff] [blame] | 1282 | #ifdef CONFIG_DYNAMIC_FTRACE |
| 1283 | _GLOBAL(mcount) |
| 1284 | _GLOBAL(_mcount) |
Al Viro | 9445aa1 | 2016-01-13 23:33:46 -0500 | [diff] [blame] | 1285 | EXPORT_SYMBOL(_mcount) |
Torsten Duwe | 1530866 | 2016-03-03 15:26:59 +1100 | [diff] [blame] | 1286 | mflr r12 |
| 1287 | mtctr r12 |
| 1288 | mtlr r0 |
| 1289 | bctr |
Steven Rostedt | 4e491d1 | 2008-05-14 23:49:44 -0400 | [diff] [blame] | 1290 | |
Torsten Duwe | 1530866 | 2016-03-03 15:26:59 +1100 | [diff] [blame] | 1291 | #ifndef CC_USING_MPROFILE_KERNEL |
Anton Blanchard | 5e66684 | 2014-04-04 09:06:33 +1100 | [diff] [blame] | 1292 | _GLOBAL_TOC(ftrace_caller) |
Steven Rostedt | 4e491d1 | 2008-05-14 23:49:44 -0400 | [diff] [blame] | 1293 | /* Taken from output of objdump from lib64/glibc */ |
| 1294 | mflr r3 |
| 1295 | ld r11, 0(r1) |
| 1296 | stdu r1, -112(r1) |
| 1297 | std r3, 128(r1) |
| 1298 | ld r4, 16(r11) |
Abhishek Sagar | 395a59d | 2008-06-21 23:47:27 +0530 | [diff] [blame] | 1299 | subi r3, r3, MCOUNT_INSN_SIZE |
Steven Rostedt | 4e491d1 | 2008-05-14 23:49:44 -0400 | [diff] [blame] | 1300 | .globl ftrace_call |
| 1301 | ftrace_call: |
| 1302 | bl ftrace_stub |
| 1303 | nop |
Steven Rostedt | 4654288 | 2009-02-10 22:19:54 -0800 | [diff] [blame] | 1304 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
| 1305 | .globl ftrace_graph_call |
| 1306 | ftrace_graph_call: |
| 1307 | b ftrace_graph_stub |
| 1308 | _GLOBAL(ftrace_graph_stub) |
| 1309 | #endif |
Steven Rostedt | 4e491d1 | 2008-05-14 23:49:44 -0400 | [diff] [blame] | 1310 | ld r0, 128(r1) |
| 1311 | mtlr r0 |
| 1312 | addi r1, r1, 112 |
Torsten Duwe | 1530866 | 2016-03-03 15:26:59 +1100 | [diff] [blame] | 1313 | |
| 1314 | #else /* CC_USING_MPROFILE_KERNEL */ |
| 1315 | /* |
| 1316 | * |
| 1317 | * ftrace_caller() is the function that replaces _mcount() when ftrace is |
| 1318 | * active. |
| 1319 | * |
| 1320 | * We arrive here after a function A calls function B, and we are the trace |
| 1321 | * function for B. When we enter r1 points to A's stack frame, B has not yet |
| 1322 | * had a chance to allocate one yet. |
| 1323 | * |
| 1324 | * Additionally r2 may point either to the TOC for A, or B, depending on |
| 1325 | * whether B did a TOC setup sequence before calling us. |
| 1326 | * |
| 1327 | * On entry the LR points back to the _mcount() call site, and r0 holds the |
| 1328 | * saved LR as it was on entry to B, ie. the original return address at the |
| 1329 | * call site in A. |
| 1330 | * |
| 1331 | * Our job is to save the register state into a struct pt_regs (on the stack) |
| 1332 | * and then arrange for the ftrace function to be called. |
| 1333 | */ |
| 1334 | _GLOBAL(ftrace_caller) |
| 1335 | /* Save the original return address in A's stack frame */ |
| 1336 | std r0,LRSAVE(r1) |
| 1337 | |
| 1338 | /* Create our stack frame + pt_regs */ |
| 1339 | stdu r1,-SWITCH_FRAME_SIZE(r1) |
| 1340 | |
| 1341 | /* Save all gprs to pt_regs */ |
Naveen N. Rao | c76655f | 2017-06-01 16:18:16 +0530 | [diff] [blame] | 1342 | SAVE_GPR(0, r1) |
| 1343 | SAVE_10GPRS(2, r1) |
| 1344 | SAVE_10GPRS(12, r1) |
| 1345 | SAVE_10GPRS(22, r1) |
| 1346 | |
| 1347 | /* Save previous stack pointer (r1) */ |
| 1348 | addi r8, r1, SWITCH_FRAME_SIZE |
| 1349 | std r8, GPR1(r1) |
Torsten Duwe | 1530866 | 2016-03-03 15:26:59 +1100 | [diff] [blame] | 1350 | |
| 1351 | /* Load special regs for save below */ |
| 1352 | mfmsr r8 |
| 1353 | mfctr r9 |
| 1354 | mfxer r10 |
| 1355 | mfcr r11 |
| 1356 | |
| 1357 | /* Get the _mcount() call site out of LR */ |
| 1358 | mflr r7 |
| 1359 | /* Save it as pt_regs->nip & pt_regs->link */ |
| 1360 | std r7, _NIP(r1) |
| 1361 | std r7, _LINK(r1) |
| 1362 | |
| 1363 | /* Save callee's TOC in the ABI compliant location */ |
| 1364 | std r2, 24(r1) |
| 1365 | ld r2,PACATOC(r13) /* get kernel TOC in r2 */ |
| 1366 | |
| 1367 | addis r3,r2,function_trace_op@toc@ha |
| 1368 | addi r3,r3,function_trace_op@toc@l |
| 1369 | ld r5,0(r3) |
| 1370 | |
Michael Ellerman | 85baa09 | 2016-03-24 22:04:05 +1100 | [diff] [blame] | 1371 | #ifdef CONFIG_LIVEPATCH |
| 1372 | mr r14,r7 /* remember old NIP */ |
| 1373 | #endif |
Torsten Duwe | 1530866 | 2016-03-03 15:26:59 +1100 | [diff] [blame] | 1374 | /* Calculate ip from nip-4 into r3 for call below */ |
| 1375 | subi r3, r7, MCOUNT_INSN_SIZE |
| 1376 | |
| 1377 | /* Put the original return address in r4 as parent_ip */ |
| 1378 | mr r4, r0 |
| 1379 | |
| 1380 | /* Save special regs */ |
| 1381 | std r8, _MSR(r1) |
| 1382 | std r9, _CTR(r1) |
| 1383 | std r10, _XER(r1) |
| 1384 | std r11, _CCR(r1) |
| 1385 | |
| 1386 | /* Load &pt_regs in r6 for call below */ |
| 1387 | addi r6, r1 ,STACK_FRAME_OVERHEAD |
| 1388 | |
| 1389 | /* ftrace_call(r3, r4, r5, r6) */ |
| 1390 | .globl ftrace_call |
| 1391 | ftrace_call: |
| 1392 | bl ftrace_stub |
| 1393 | nop |
| 1394 | |
| 1395 | /* Load ctr with the possibly modified NIP */ |
| 1396 | ld r3, _NIP(r1) |
| 1397 | mtctr r3 |
Michael Ellerman | 85baa09 | 2016-03-24 22:04:05 +1100 | [diff] [blame] | 1398 | #ifdef CONFIG_LIVEPATCH |
| 1399 | cmpd r14,r3 /* has NIP been altered? */ |
| 1400 | #endif |
Torsten Duwe | 1530866 | 2016-03-03 15:26:59 +1100 | [diff] [blame] | 1401 | |
| 1402 | /* Restore gprs */ |
Naveen N. Rao | c76655f | 2017-06-01 16:18:16 +0530 | [diff] [blame] | 1403 | REST_GPR(0,r1) |
| 1404 | REST_10GPRS(2,r1) |
| 1405 | REST_10GPRS(12,r1) |
| 1406 | REST_10GPRS(22,r1) |
Torsten Duwe | 1530866 | 2016-03-03 15:26:59 +1100 | [diff] [blame] | 1407 | |
| 1408 | /* Restore callee's TOC */ |
| 1409 | ld r2, 24(r1) |
| 1410 | |
| 1411 | /* Pop our stack frame */ |
| 1412 | addi r1, r1, SWITCH_FRAME_SIZE |
| 1413 | |
| 1414 | /* Restore original LR for return to B */ |
| 1415 | ld r0, LRSAVE(r1) |
| 1416 | mtlr r0 |
| 1417 | |
Michael Ellerman | 85baa09 | 2016-03-24 22:04:05 +1100 | [diff] [blame] | 1418 | #ifdef CONFIG_LIVEPATCH |
| 1419 | /* Based on the cmpd above, if the NIP was altered handle livepatch */ |
| 1420 | bne- livepatch_handler |
| 1421 | #endif |
| 1422 | |
Torsten Duwe | 1530866 | 2016-03-03 15:26:59 +1100 | [diff] [blame] | 1423 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
| 1424 | stdu r1, -112(r1) |
| 1425 | .globl ftrace_graph_call |
| 1426 | ftrace_graph_call: |
| 1427 | b ftrace_graph_stub |
| 1428 | _GLOBAL(ftrace_graph_stub) |
| 1429 | addi r1, r1, 112 |
| 1430 | #endif |
| 1431 | |
| 1432 | ld r0,LRSAVE(r1) /* restore callee's lr at _mcount site */ |
| 1433 | mtlr r0 |
| 1434 | bctr /* jump after _mcount site */ |
| 1435 | #endif /* CC_USING_MPROFILE_KERNEL */ |
| 1436 | |
Steven Rostedt | 4e491d1 | 2008-05-14 23:49:44 -0400 | [diff] [blame] | 1437 | _GLOBAL(ftrace_stub) |
| 1438 | blr |
Michael Ellerman | 85baa09 | 2016-03-24 22:04:05 +1100 | [diff] [blame] | 1439 | |
| 1440 | #ifdef CONFIG_LIVEPATCH |
| 1441 | /* |
| 1442 | * This function runs in the mcount context, between two functions. As |
| 1443 | * such it can only clobber registers which are volatile and used in |
| 1444 | * function linkage. |
| 1445 | * |
| 1446 | * We get here when a function A, calls another function B, but B has |
| 1447 | * been live patched with a new function C. |
| 1448 | * |
| 1449 | * On entry: |
| 1450 | * - we have no stack frame and can not allocate one |
| 1451 | * - LR points back to the original caller (in A) |
| 1452 | * - CTR holds the new NIP in C |
| 1453 | * - r0 & r12 are free |
| 1454 | * |
| 1455 | * r0 can't be used as the base register for a DS-form load or store, so |
| 1456 | * we temporarily shuffle r1 (stack pointer) into r0 and then put it back. |
| 1457 | */ |
| 1458 | livepatch_handler: |
| 1459 | CURRENT_THREAD_INFO(r12, r1) |
| 1460 | |
| 1461 | /* Save stack pointer into r0 */ |
| 1462 | mr r0, r1 |
| 1463 | |
| 1464 | /* Allocate 3 x 8 bytes */ |
| 1465 | ld r1, TI_livepatch_sp(r12) |
| 1466 | addi r1, r1, 24 |
| 1467 | std r1, TI_livepatch_sp(r12) |
| 1468 | |
| 1469 | /* Save toc & real LR on livepatch stack */ |
| 1470 | std r2, -24(r1) |
| 1471 | mflr r12 |
| 1472 | std r12, -16(r1) |
| 1473 | |
| 1474 | /* Store stack end marker */ |
| 1475 | lis r12, STACK_END_MAGIC@h |
| 1476 | ori r12, r12, STACK_END_MAGIC@l |
| 1477 | std r12, -8(r1) |
| 1478 | |
| 1479 | /* Restore real stack pointer */ |
| 1480 | mr r1, r0 |
| 1481 | |
| 1482 | /* Put ctr in r12 for global entry and branch there */ |
| 1483 | mfctr r12 |
| 1484 | bctrl |
| 1485 | |
| 1486 | /* |
| 1487 | * Now we are returning from the patched function to the original |
| 1488 | * caller A. We are free to use r0 and r12, and we can use r2 until we |
| 1489 | * restore it. |
| 1490 | */ |
| 1491 | |
| 1492 | CURRENT_THREAD_INFO(r12, r1) |
| 1493 | |
| 1494 | /* Save stack pointer into r0 */ |
| 1495 | mr r0, r1 |
| 1496 | |
| 1497 | ld r1, TI_livepatch_sp(r12) |
| 1498 | |
| 1499 | /* Check stack marker hasn't been trashed */ |
| 1500 | lis r2, STACK_END_MAGIC@h |
| 1501 | ori r2, r2, STACK_END_MAGIC@l |
| 1502 | ld r12, -8(r1) |
| 1503 | 1: tdne r12, r2 |
| 1504 | EMIT_BUG_ENTRY 1b, __FILE__, __LINE__ - 1, 0 |
| 1505 | |
| 1506 | /* Restore LR & toc from livepatch stack */ |
| 1507 | ld r12, -16(r1) |
| 1508 | mtlr r12 |
| 1509 | ld r2, -24(r1) |
| 1510 | |
| 1511 | /* Pop livepatch stack frame */ |
| 1512 | CURRENT_THREAD_INFO(r12, r0) |
| 1513 | subi r1, r1, 24 |
| 1514 | std r1, TI_livepatch_sp(r12) |
| 1515 | |
| 1516 | /* Restore real stack pointer */ |
| 1517 | mr r1, r0 |
| 1518 | |
| 1519 | /* Return to original caller of live patched function */ |
| 1520 | blr |
| 1521 | #endif |
| 1522 | |
| 1523 | |
Steven Rostedt | 4e491d1 | 2008-05-14 23:49:44 -0400 | [diff] [blame] | 1524 | #else |
Anton Blanchard | 5e66684 | 2014-04-04 09:06:33 +1100 | [diff] [blame] | 1525 | _GLOBAL_TOC(_mcount) |
Al Viro | 9445aa1 | 2016-01-13 23:33:46 -0500 | [diff] [blame] | 1526 | EXPORT_SYMBOL(_mcount) |
Steven Rostedt | 4e491d1 | 2008-05-14 23:49:44 -0400 | [diff] [blame] | 1527 | /* Taken from output of objdump from lib64/glibc */ |
| 1528 | mflr r3 |
| 1529 | ld r11, 0(r1) |
| 1530 | stdu r1, -112(r1) |
| 1531 | std r3, 128(r1) |
| 1532 | ld r4, 16(r11) |
| 1533 | |
Abhishek Sagar | 395a59d | 2008-06-21 23:47:27 +0530 | [diff] [blame] | 1534 | subi r3, r3, MCOUNT_INSN_SIZE |
Steven Rostedt | 4e491d1 | 2008-05-14 23:49:44 -0400 | [diff] [blame] | 1535 | LOAD_REG_ADDR(r5,ftrace_trace_function) |
| 1536 | ld r5,0(r5) |
| 1537 | ld r5,0(r5) |
| 1538 | mtctr r5 |
| 1539 | bctrl |
Steven Rostedt | 4e491d1 | 2008-05-14 23:49:44 -0400 | [diff] [blame] | 1540 | nop |
Steven Rostedt | 6794c78 | 2009-02-09 21:10:27 -0800 | [diff] [blame] | 1541 | |
| 1542 | |
| 1543 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
| 1544 | b ftrace_graph_caller |
| 1545 | #endif |
Steven Rostedt | 4e491d1 | 2008-05-14 23:49:44 -0400 | [diff] [blame] | 1546 | ld r0, 128(r1) |
| 1547 | mtlr r0 |
| 1548 | addi r1, r1, 112 |
| 1549 | _GLOBAL(ftrace_stub) |
| 1550 | blr |
| 1551 | |
Steven Rostedt | 6794c78 | 2009-02-09 21:10:27 -0800 | [diff] [blame] | 1552 | #endif /* CONFIG_DYNAMIC_FTRACE */ |
| 1553 | |
| 1554 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
Torsten Duwe | 1530866 | 2016-03-03 15:26:59 +1100 | [diff] [blame] | 1555 | #ifndef CC_USING_MPROFILE_KERNEL |
Steven Rostedt | 4654288 | 2009-02-10 22:19:54 -0800 | [diff] [blame] | 1556 | _GLOBAL(ftrace_graph_caller) |
Steven Rostedt | 6794c78 | 2009-02-09 21:10:27 -0800 | [diff] [blame] | 1557 | /* load r4 with local address */ |
| 1558 | ld r4, 128(r1) |
| 1559 | subi r4, r4, MCOUNT_INSN_SIZE |
| 1560 | |
Anton Blanchard | b3c1872 | 2014-09-17 17:07:04 +1000 | [diff] [blame] | 1561 | /* Grab the LR out of the caller stack frame */ |
Steven Rostedt | 6794c78 | 2009-02-09 21:10:27 -0800 | [diff] [blame] | 1562 | ld r11, 112(r1) |
Anton Blanchard | b3c1872 | 2014-09-17 17:07:04 +1000 | [diff] [blame] | 1563 | ld r3, 16(r11) |
Steven Rostedt | 6794c78 | 2009-02-09 21:10:27 -0800 | [diff] [blame] | 1564 | |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1565 | bl prepare_ftrace_return |
Steven Rostedt | 6794c78 | 2009-02-09 21:10:27 -0800 | [diff] [blame] | 1566 | nop |
| 1567 | |
Anton Blanchard | b3c1872 | 2014-09-17 17:07:04 +1000 | [diff] [blame] | 1568 | /* |
| 1569 | * prepare_ftrace_return gives us the address we divert to. |
| 1570 | * Change the LR in the callers stack frame to this. |
| 1571 | */ |
| 1572 | ld r11, 112(r1) |
| 1573 | std r3, 16(r11) |
| 1574 | |
Steven Rostedt | 6794c78 | 2009-02-09 21:10:27 -0800 | [diff] [blame] | 1575 | ld r0, 128(r1) |
| 1576 | mtlr r0 |
| 1577 | addi r1, r1, 112 |
| 1578 | blr |
| 1579 | |
Torsten Duwe | 1530866 | 2016-03-03 15:26:59 +1100 | [diff] [blame] | 1580 | #else /* CC_USING_MPROFILE_KERNEL */ |
| 1581 | _GLOBAL(ftrace_graph_caller) |
| 1582 | /* with -mprofile-kernel, parameter regs are still alive at _mcount */ |
| 1583 | std r10, 104(r1) |
| 1584 | std r9, 96(r1) |
| 1585 | std r8, 88(r1) |
| 1586 | std r7, 80(r1) |
| 1587 | std r6, 72(r1) |
| 1588 | std r5, 64(r1) |
| 1589 | std r4, 56(r1) |
| 1590 | std r3, 48(r1) |
| 1591 | |
| 1592 | /* Save callee's TOC in the ABI compliant location */ |
| 1593 | std r2, 24(r1) |
| 1594 | ld r2, PACATOC(r13) /* get kernel TOC in r2 */ |
| 1595 | |
| 1596 | mfctr r4 /* ftrace_caller has moved local addr here */ |
| 1597 | std r4, 40(r1) |
| 1598 | mflr r3 /* ftrace_caller has restored LR from stack */ |
| 1599 | subi r4, r4, MCOUNT_INSN_SIZE |
| 1600 | |
| 1601 | bl prepare_ftrace_return |
| 1602 | nop |
| 1603 | |
| 1604 | /* |
| 1605 | * prepare_ftrace_return gives us the address we divert to. |
| 1606 | * Change the LR to this. |
| 1607 | */ |
| 1608 | mtlr r3 |
| 1609 | |
| 1610 | ld r0, 40(r1) |
| 1611 | mtctr r0 |
| 1612 | ld r10, 104(r1) |
| 1613 | ld r9, 96(r1) |
| 1614 | ld r8, 88(r1) |
| 1615 | ld r7, 80(r1) |
| 1616 | ld r6, 72(r1) |
| 1617 | ld r5, 64(r1) |
| 1618 | ld r4, 56(r1) |
| 1619 | ld r3, 48(r1) |
| 1620 | |
| 1621 | /* Restore callee's TOC */ |
| 1622 | ld r2, 24(r1) |
| 1623 | |
| 1624 | addi r1, r1, 112 |
| 1625 | mflr r0 |
| 1626 | std r0, LRSAVE(r1) |
| 1627 | bctr |
| 1628 | #endif /* CC_USING_MPROFILE_KERNEL */ |
| 1629 | |
Steven Rostedt | 6794c78 | 2009-02-09 21:10:27 -0800 | [diff] [blame] | 1630 | _GLOBAL(return_to_handler) |
| 1631 | /* need to save return values */ |
| 1632 | std r4, -32(r1) |
| 1633 | std r3, -24(r1) |
| 1634 | /* save TOC */ |
| 1635 | std r2, -16(r1) |
| 1636 | std r31, -8(r1) |
| 1637 | mr r31, r1 |
| 1638 | stdu r1, -112(r1) |
| 1639 | |
Steven Rostedt | bb72534 | 2009-02-11 12:45:49 -0800 | [diff] [blame] | 1640 | /* |
Anton Blanchard | 7d56c65 | 2014-09-17 17:07:03 +1000 | [diff] [blame] | 1641 | * We might be called from a module. |
Steven Rostedt | bb72534 | 2009-02-11 12:45:49 -0800 | [diff] [blame] | 1642 | * Switch to our TOC to run inside the core kernel. |
| 1643 | */ |
Steven Rostedt | be10ab1 | 2009-09-15 08:30:14 -0700 | [diff] [blame] | 1644 | ld r2, PACATOC(r13) |
Steven Rostedt | 6794c78 | 2009-02-09 21:10:27 -0800 | [diff] [blame] | 1645 | |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1646 | bl ftrace_return_to_handler |
Steven Rostedt | 6794c78 | 2009-02-09 21:10:27 -0800 | [diff] [blame] | 1647 | nop |
| 1648 | |
| 1649 | /* return value has real return address */ |
| 1650 | mtlr r3 |
| 1651 | |
| 1652 | ld r1, 0(r1) |
| 1653 | ld r4, -32(r1) |
| 1654 | ld r3, -24(r1) |
| 1655 | ld r2, -16(r1) |
| 1656 | ld r31, -8(r1) |
| 1657 | |
| 1658 | /* Jump back to real return address */ |
| 1659 | blr |
| 1660 | #endif /* CONFIG_FUNCTION_GRAPH_TRACER */ |
| 1661 | #endif /* CONFIG_FUNCTION_TRACER */ |