Blame - arch/s390/kernel/base.S - kernel/msm-4.9

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Heiko Carstens	ab14de6	2007-02-05 21:18:37 +0100	[diff] [blame]	1	/*
				2	* arch/s390/kernel/base.S
				3	*
Heiko Carstens	a53c8fa	2012-07-20 11:15:04 +0200	[diff] [blame]	4	* Copyright IBM Corp. 2006, 2007
Heiko Carstens	ab14de6	2007-02-05 21:18:37 +0100	[diff] [blame]	5	* Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
				6	* Michael Holzheu <holzheu@de.ibm.com>
				7	*/
				8
Jan Glauber	144d634	2011-07-24 10:48:19 +0200	[diff] [blame]	9	#include <linux/linkage.h>
Heiko Carstens	cbb870c	2010-02-26 22:37:43 +0100	[diff] [blame]	10	#include <asm/asm-offsets.h>
Martin Schwidefsky	b35421a	2018-05-23 18:21:49 +0200	[diff] [blame]	11	#include <asm/nospec-insn.h>
Heiko Carstens	ab14de6	2007-02-05 21:18:37 +0100	[diff] [blame]	12	#include <asm/ptrace.h>
Heiko Carstens	eb54619	2012-06-04 15:05:43 +0200	[diff] [blame]	13	#include <asm/sigp.h>
Heiko Carstens	ab14de6	2007-02-05 21:18:37 +0100	[diff] [blame]	14
Martin Schwidefsky	b35421a	2018-05-23 18:21:49 +0200	[diff] [blame]	15	GEN_BR_THUNK %r9
				16	GEN_BR_THUNK %r14
				17
Jan Glauber	144d634	2011-07-24 10:48:19 +0200	[diff] [blame]	18	ENTRY(s390_base_mcck_handler)
Heiko Carstens	ab14de6	2007-02-05 21:18:37 +0100	[diff] [blame]	19	basr %r13,0
				20	0: lg %r15,__LC_PANIC_STACK # load panic stack
				21	aghi %r15,-STACK_FRAME_OVERHEAD
				22	larl %r1,s390_base_mcck_handler_fn
Martin Schwidefsky	b35421a	2018-05-23 18:21:49 +0200	[diff] [blame]	23	lg %r9,0(%r1)
				24	ltgr %r9,%r9
Heiko Carstens	ab14de6	2007-02-05 21:18:37 +0100	[diff] [blame]	25	jz 1f
Martin Schwidefsky	b35421a	2018-05-23 18:21:49 +0200	[diff] [blame]	26	BASR_EX %r14,%r9
Heiko Carstens	ab14de6	2007-02-05 21:18:37 +0100	[diff] [blame]	27	1: la %r1,4095
				28	lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)
				29	lpswe __LC_MCK_OLD_PSW
				30
				31	.section .bss
Jan Glauber	144d634	2011-07-24 10:48:19 +0200	[diff] [blame]	32	.align 8
Heiko Carstens	ab14de6	2007-02-05 21:18:37 +0100	[diff] [blame]	33	.globl s390_base_mcck_handler_fn
				34	s390_base_mcck_handler_fn:
				35	.quad 0
				36	.previous
				37
Jan Glauber	144d634	2011-07-24 10:48:19 +0200	[diff] [blame]	38	ENTRY(s390_base_ext_handler)
Martin Schwidefsky	c532890	2011-12-27 11:27:15 +0100	[diff] [blame]	39	stmg %r0,%r15,__LC_SAVE_AREA_ASYNC
Heiko Carstens	ab14de6	2007-02-05 21:18:37 +0100	[diff] [blame]	40	basr %r13,0
				41	0: aghi %r15,-STACK_FRAME_OVERHEAD
				42	larl %r1,s390_base_ext_handler_fn
Martin Schwidefsky	b35421a	2018-05-23 18:21:49 +0200	[diff] [blame]	43	lg %r9,0(%r1)
				44	ltgr %r9,%r9
Heiko Carstens	ab14de6	2007-02-05 21:18:37 +0100	[diff] [blame]	45	jz 1f
Martin Schwidefsky	b35421a	2018-05-23 18:21:49 +0200	[diff] [blame]	46	BASR_EX %r14,%r9
Martin Schwidefsky	c532890	2011-12-27 11:27:15 +0100	[diff] [blame]	47	1: lmg %r0,%r15,__LC_SAVE_AREA_ASYNC
Heiko Carstens	ab14de6	2007-02-05 21:18:37 +0100	[diff] [blame]	48	ni __LC_EXT_OLD_PSW+1,0xfd # clear wait state bit
				49	lpswe __LC_EXT_OLD_PSW
				50
				51	.section .bss
Jan Glauber	144d634	2011-07-24 10:48:19 +0200	[diff] [blame]	52	.align 8
Heiko Carstens	ab14de6	2007-02-05 21:18:37 +0100	[diff] [blame]	53	.globl s390_base_ext_handler_fn
				54	s390_base_ext_handler_fn:
				55	.quad 0
				56	.previous
				57
Jan Glauber	144d634	2011-07-24 10:48:19 +0200	[diff] [blame]	58	ENTRY(s390_base_pgm_handler)
Martin Schwidefsky	c532890	2011-12-27 11:27:15 +0100	[diff] [blame]	59	stmg %r0,%r15,__LC_SAVE_AREA_SYNC
Heiko Carstens	ab14de6	2007-02-05 21:18:37 +0100	[diff] [blame]	60	basr %r13,0
				61	0: aghi %r15,-STACK_FRAME_OVERHEAD
				62	larl %r1,s390_base_pgm_handler_fn
Martin Schwidefsky	b35421a	2018-05-23 18:21:49 +0200	[diff] [blame]	63	lg %r9,0(%r1)
				64	ltgr %r9,%r9
Heiko Carstens	ab14de6	2007-02-05 21:18:37 +0100	[diff] [blame]	65	jz 1f
Martin Schwidefsky	b35421a	2018-05-23 18:21:49 +0200	[diff] [blame]	66	BASR_EX %r14,%r9
Martin Schwidefsky	c532890	2011-12-27 11:27:15 +0100	[diff] [blame]	67	lmg %r0,%r15,__LC_SAVE_AREA_SYNC
Heiko Carstens	ab14de6	2007-02-05 21:18:37 +0100	[diff] [blame]	68	lpswe __LC_PGM_OLD_PSW
				69	1: lpswe disabled_wait_psw-0b(%r13)
				70
				71	.align 8
				72	disabled_wait_psw:
				73	.quad 0x0002000180000000,0x0000000000000000 + s390_base_pgm_handler
				74
				75	.section .bss
Jan Glauber	144d634	2011-07-24 10:48:19 +0200	[diff] [blame]	76	.align 8
Heiko Carstens	ab14de6	2007-02-05 21:18:37 +0100	[diff] [blame]	77	.globl s390_base_pgm_handler_fn
				78	s390_base_pgm_handler_fn:
				79	.quad 0
				80	.previous
				81
Michael Holzheu	9dc7356	2011-08-03 16:44:22 +0200	[diff] [blame]	82	#
				83	# Calls diag 308 subcode 1 and continues execution
				84	#
Michael Holzheu	9dc7356	2011-08-03 16:44:22 +0200	[diff] [blame]	85	ENTRY(diag308_reset)
				86	larl %r4,.Lctlregs # Save control registers
				87	stctg %c0,%c15,0(%r4)
Michael Holzheu	1592a8e	2015-05-26 19:05:23 +0200	[diff] [blame]	88	lg %r2,0(%r4) # Disable lowcore protection
				89	nilh %r2,0xefff
				90	larl %r4,.Lctlreg0
				91	stg %r2,0(%r4)
				92	lctlg %c0,%c0,0(%r4)
Michael Holzheu	60a0c68	2011-10-30 15:16:40 +0100	[diff] [blame]	93	larl %r4,.Lfpctl # Floating point control register
				94	stfpc 0(%r4)
Michael Holzheu	1592a8e	2015-05-26 19:05:23 +0200	[diff] [blame]	95	larl %r4,.Lprefix # Save prefix register
				96	stpx 0(%r4)
				97	larl %r4,.Lprefix_zero # Set prefix register to 0
				98	spx 0(%r4)
Michael Holzheu	fa7c004	2012-05-21 11:30:30 +0200	[diff] [blame]	99	larl %r4,.Lcontinue_psw # Save PSW flags
				100	epsw %r2,%r3
				101	stm %r2,%r3,0(%r4)
Michael Holzheu	9dc7356	2011-08-03 16:44:22 +0200	[diff] [blame]	102	larl %r4,.Lrestart_psw # Setup restart PSW at absolute 0
				103	lghi %r3,0
				104	lg %r4,0(%r4) # Save PSW
				105	sturg %r4,%r3 # Use sturg, because of large pages
				106	lghi %r1,1
Martin Schwidefsky	10ad34b	2015-01-14 17:52:10 +0100	[diff] [blame]	107	lghi %r0,0
				108	diag %r0,%r1,0x308
Michael Holzheu	9dc7356	2011-08-03 16:44:22 +0200	[diff] [blame]	109	.Lrestart_part2:
				110	lhi %r0,0 # Load r0 with zero
				111	lhi %r1,2 # Use mode 2 = ESAME (dump)
Heiko Carstens	eb54619	2012-06-04 15:05:43 +0200	[diff] [blame]	112	sigp %r1,%r0,SIGP_SET_ARCHITECTURE # Switch to ESAME mode
Michael Holzheu	9dc7356	2011-08-03 16:44:22 +0200	[diff] [blame]	113	sam64 # Switch to 64 bit addressing mode
				114	larl %r4,.Lctlregs # Restore control registers
				115	lctlg %c0,%c15,0(%r4)
Michael Holzheu	60a0c68	2011-10-30 15:16:40 +0100	[diff] [blame]	116	larl %r4,.Lfpctl # Restore floating point ctl register
				117	lfpc 0(%r4)
Michael Holzheu	1592a8e	2015-05-26 19:05:23 +0200	[diff] [blame]	118	larl %r4,.Lprefix # Restore prefix register
				119	spx 0(%r4)
Michael Holzheu	fa7c004	2012-05-21 11:30:30 +0200	[diff] [blame]	120	larl %r4,.Lcontinue_psw # Restore PSW flags
				121	lpswe 0(%r4)
				122	.Lcontinue:
Martin Schwidefsky	b35421a	2018-05-23 18:21:49 +0200	[diff] [blame]	123	BR_EX %r14
Michael Holzheu	9dc7356	2011-08-03 16:44:22 +0200	[diff] [blame]	124	.align 16
				125	.Lrestart_psw:
				126	.long 0x00080000,0x80000000 + .Lrestart_part2
				127
Michael Holzheu	fa7c004	2012-05-21 11:30:30 +0200	[diff] [blame]	128	.section .data..nosave,"aw",@progbits
				129	.align 8
				130	.Lcontinue_psw:
				131	.quad 0,.Lcontinue
				132	.previous
				133
Michael Holzheu	9dc7356	2011-08-03 16:44:22 +0200	[diff] [blame]	134	.section .bss
				135	.align 8
Michael Holzheu	1592a8e	2015-05-26 19:05:23 +0200	[diff] [blame]	136	.Lctlreg0:
				137	.quad 0
Michael Holzheu	9dc7356	2011-08-03 16:44:22 +0200	[diff] [blame]	138	.Lctlregs:
				139	.rept 16
				140	.quad 0
				141	.endr
Michael Holzheu	60a0c68	2011-10-30 15:16:40 +0100	[diff] [blame]	142	.Lfpctl:
				143	.long 0
Michael Holzheu	1592a8e	2015-05-26 19:05:23 +0200	[diff] [blame]	144	.Lprefix:
				145	.long 0
				146	.Lprefix_zero:
				147	.long 0
Michael Holzheu	9dc7356	2011-08-03 16:44:22 +0200	[diff] [blame]	148	.previous