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Paul Mundt959f85f2006-09-27 16:43:28 +09001/*
Nobuhiro Iwamatsu9ca04432011-01-07 03:02:11 +00002 * arch/sh/drivers/pci/fixups-landisk.c
Paul Mundt959f85f2006-09-27 16:43:28 +09003 *
4 * PCI initialization for the I-O DATA Device, Inc. LANDISK board
5 *
6 * Copyright (C) 2006 kogiidena
Nobuhiro Iwamatsu9ca04432011-01-07 03:02:11 +00007 * Copyright (C) 2010 Nobuhiro Iwamatsu
Paul Mundt959f85f2006-09-27 16:43:28 +09008 *
9 * May be copied or modified under the terms of the GNU General Public
10 * License. See linux/COPYING for more information.
11 */
Paul Mundt959f85f2006-09-27 16:43:28 +090012#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pci.h>
Paul Mundt58796ce2012-05-18 17:42:29 +090017#include <linux/sh_intc.h>
Paul Mundt959f85f2006-09-27 16:43:28 +090018#include "pci-sh4.h"
19
Nobuhiro Iwamatsu9ca04432011-01-07 03:02:11 +000020#define PCIMCR_MRSET_OFF 0xBFFFFFFF
21#define PCIMCR_RFSH_OFF 0xFFFFFFFB
22
Ralf Baechled5341942011-06-10 15:30:21 +010023int pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
Paul Mundt959f85f2006-09-27 16:43:28 +090024{
25 /*
26 * slot0: pin1-4 = irq5,6,7,8
27 * slot1: pin1-4 = irq6,7,8,5
28 * slot2: pin1-4 = irq7,8,5,6
29 * slot3: pin1-4 = irq8,5,6,7
30 */
Paul Mundt58796ce2012-05-18 17:42:29 +090031 int irq = ((slot + pin - 1) & 0x3) + evt2irq(0x2a0);
Paul Mundt959f85f2006-09-27 16:43:28 +090032
33 if ((slot | (pin - 1)) > 0x3) {
Nobuhiro Iwamatsu9ca04432011-01-07 03:02:11 +000034 printk(KERN_WARNING "PCI: Bad IRQ mapping request for slot %d pin %c\n",
Paul Mundt959f85f2006-09-27 16:43:28 +090035 slot, pin - 1 + 'A');
36 return -1;
37 }
38 return irq;
39}
Nobuhiro Iwamatsu9ca04432011-01-07 03:02:11 +000040
41int pci_fixup_pcic(struct pci_channel *chan)
42{
43 unsigned long bcr1, mcr;
44
45 bcr1 = __raw_readl(SH7751_BCR1);
46 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
47 pci_write_reg(chan, bcr1, SH4_PCIBCR1);
48
49 mcr = __raw_readl(SH7751_MCR);
50 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
51 pci_write_reg(chan, mcr, SH4_PCIMCR);
52
53 pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5);
54 pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6);
55 pci_write_reg(chan, 0x0c000000, SH4_PCILAR0);
56 pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
57
58 return 0;
59}