| AnilKumar Chimata | e78789a | 2017-04-07 12:18:46 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #ifndef _QCOM_INLINE_CRYPTO_ENGINE_REGS_H_ |
| 14 | #define _QCOM_INLINE_CRYPTO_ENGINE_REGS_H_ |
| 15 | |
| 16 | /* Register bits for ICE version */ |
| 17 | #define ICE_CORE_CURRENT_MAJOR_VERSION 0x03 |
| 18 | |
| 19 | #define ICE_CORE_STEP_REV_MASK 0xFFFF |
| 20 | #define ICE_CORE_STEP_REV 0 /* bit 15-0 */ |
| 21 | #define ICE_CORE_MAJOR_REV_MASK 0xFF000000 |
| 22 | #define ICE_CORE_MAJOR_REV 24 /* bit 31-24 */ |
| 23 | #define ICE_CORE_MINOR_REV_MASK 0xFF0000 |
| 24 | #define ICE_CORE_MINOR_REV 16 /* bit 23-16 */ |
| 25 | |
| 26 | #define ICE_BIST_STATUS_MASK (0xF0000000) /* bits 28-31 */ |
| 27 | |
| 28 | #define ICE_FUSE_SETTING_MASK 0x1 |
| 29 | #define ICE_FORCE_HW_KEY0_SETTING_MASK 0x2 |
| 30 | #define ICE_FORCE_HW_KEY1_SETTING_MASK 0x4 |
| 31 | |
| 32 | /* QCOM ICE Registers from SWI */ |
| 33 | #define QCOM_ICE_REGS_CONTROL 0x0000 |
| 34 | #define QCOM_ICE_REGS_RESET 0x0004 |
| 35 | #define QCOM_ICE_REGS_VERSION 0x0008 |
| 36 | #define QCOM_ICE_REGS_FUSE_SETTING 0x0010 |
| 37 | #define QCOM_ICE_REGS_PARAMETERS_1 0x0014 |
| 38 | #define QCOM_ICE_REGS_PARAMETERS_2 0x0018 |
| 39 | #define QCOM_ICE_REGS_PARAMETERS_3 0x001C |
| 40 | #define QCOM_ICE_REGS_PARAMETERS_4 0x0020 |
| 41 | #define QCOM_ICE_REGS_PARAMETERS_5 0x0024 |
| 42 | |
| 43 | |
| 44 | /* QCOM ICE v3.X only */ |
| 45 | #define QCOM_ICE_GENERAL_ERR_STTS 0x0040 |
| 46 | #define QCOM_ICE_INVALID_CCFG_ERR_STTS 0x0030 |
| 47 | #define QCOM_ICE_GENERAL_ERR_MASK 0x0044 |
| 48 | |
| 49 | |
| 50 | /* QCOM ICE v2.X only */ |
| 51 | #define QCOM_ICE_REGS_NON_SEC_IRQ_STTS 0x0040 |
| 52 | #define QCOM_ICE_REGS_NON_SEC_IRQ_MASK 0x0044 |
| 53 | |
| 54 | |
| 55 | #define QCOM_ICE_REGS_NON_SEC_IRQ_CLR 0x0048 |
| 56 | #define QCOM_ICE_REGS_STREAM1_ERROR_SYNDROME1 0x0050 |
| 57 | #define QCOM_ICE_REGS_STREAM1_ERROR_SYNDROME2 0x0054 |
| 58 | #define QCOM_ICE_REGS_STREAM2_ERROR_SYNDROME1 0x0058 |
| 59 | #define QCOM_ICE_REGS_STREAM2_ERROR_SYNDROME2 0x005C |
| 60 | #define QCOM_ICE_REGS_STREAM1_BIST_ERROR_VEC 0x0060 |
| 61 | #define QCOM_ICE_REGS_STREAM2_BIST_ERROR_VEC 0x0064 |
| 62 | #define QCOM_ICE_REGS_STREAM1_BIST_FINISH_VEC 0x0068 |
| 63 | #define QCOM_ICE_REGS_STREAM2_BIST_FINISH_VEC 0x006C |
| 64 | #define QCOM_ICE_REGS_BIST_STATUS 0x0070 |
| 65 | #define QCOM_ICE_REGS_BYPASS_STATUS 0x0074 |
| 66 | #define QCOM_ICE_REGS_ADVANCED_CONTROL 0x1000 |
| 67 | #define QCOM_ICE_REGS_ENDIAN_SWAP 0x1004 |
| 68 | #define QCOM_ICE_REGS_TEST_BUS_CONTROL 0x1010 |
| 69 | #define QCOM_ICE_REGS_TEST_BUS_REG 0x1014 |
| 70 | #define QCOM_ICE_REGS_STREAM1_COUNTERS1 0x1100 |
| 71 | #define QCOM_ICE_REGS_STREAM1_COUNTERS2 0x1104 |
| 72 | #define QCOM_ICE_REGS_STREAM1_COUNTERS3 0x1108 |
| 73 | #define QCOM_ICE_REGS_STREAM1_COUNTERS4 0x110C |
| 74 | #define QCOM_ICE_REGS_STREAM1_COUNTERS5_MSB 0x1110 |
| 75 | #define QCOM_ICE_REGS_STREAM1_COUNTERS5_LSB 0x1114 |
| 76 | #define QCOM_ICE_REGS_STREAM1_COUNTERS6_MSB 0x1118 |
| 77 | #define QCOM_ICE_REGS_STREAM1_COUNTERS6_LSB 0x111C |
| 78 | #define QCOM_ICE_REGS_STREAM1_COUNTERS7_MSB 0x1120 |
| 79 | #define QCOM_ICE_REGS_STREAM1_COUNTERS7_LSB 0x1124 |
| 80 | #define QCOM_ICE_REGS_STREAM1_COUNTERS8_MSB 0x1128 |
| 81 | #define QCOM_ICE_REGS_STREAM1_COUNTERS8_LSB 0x112C |
| 82 | #define QCOM_ICE_REGS_STREAM1_COUNTERS9_MSB 0x1130 |
| 83 | #define QCOM_ICE_REGS_STREAM1_COUNTERS9_LSB 0x1134 |
| 84 | #define QCOM_ICE_REGS_STREAM2_COUNTERS1 0x1200 |
| 85 | #define QCOM_ICE_REGS_STREAM2_COUNTERS2 0x1204 |
| 86 | #define QCOM_ICE_REGS_STREAM2_COUNTERS3 0x1208 |
| 87 | #define QCOM_ICE_REGS_STREAM2_COUNTERS4 0x120C |
| 88 | #define QCOM_ICE_REGS_STREAM2_COUNTERS5_MSB 0x1210 |
| 89 | #define QCOM_ICE_REGS_STREAM2_COUNTERS5_LSB 0x1214 |
| 90 | #define QCOM_ICE_REGS_STREAM2_COUNTERS6_MSB 0x1218 |
| 91 | #define QCOM_ICE_REGS_STREAM2_COUNTERS6_LSB 0x121C |
| 92 | #define QCOM_ICE_REGS_STREAM2_COUNTERS7_MSB 0x1220 |
| 93 | #define QCOM_ICE_REGS_STREAM2_COUNTERS7_LSB 0x1224 |
| 94 | #define QCOM_ICE_REGS_STREAM2_COUNTERS8_MSB 0x1228 |
| 95 | #define QCOM_ICE_REGS_STREAM2_COUNTERS8_LSB 0x122C |
| 96 | #define QCOM_ICE_REGS_STREAM2_COUNTERS9_MSB 0x1230 |
| 97 | #define QCOM_ICE_REGS_STREAM2_COUNTERS9_LSB 0x1234 |
| 98 | |
| 99 | #define QCOM_ICE_STREAM1_PREMATURE_LBA_CHANGE (1L << 0) |
| 100 | #define QCOM_ICE_STREAM2_PREMATURE_LBA_CHANGE (1L << 1) |
| 101 | #define QCOM_ICE_STREAM1_NOT_EXPECTED_LBO (1L << 2) |
| 102 | #define QCOM_ICE_STREAM2_NOT_EXPECTED_LBO (1L << 3) |
| 103 | #define QCOM_ICE_STREAM1_NOT_EXPECTED_DUN (1L << 4) |
| 104 | #define QCOM_ICE_STREAM2_NOT_EXPECTED_DUN (1L << 5) |
| 105 | #define QCOM_ICE_STREAM1_NOT_EXPECTED_DUS (1L << 6) |
| 106 | #define QCOM_ICE_STREAM2_NOT_EXPECTED_DUS (1L << 7) |
| 107 | #define QCOM_ICE_STREAM1_NOT_EXPECTED_DBO (1L << 8) |
| 108 | #define QCOM_ICE_STREAM2_NOT_EXPECTED_DBO (1L << 9) |
| 109 | #define QCOM_ICE_STREAM1_NOT_EXPECTED_ENC_SEL (1L << 10) |
| 110 | #define QCOM_ICE_STREAM2_NOT_EXPECTED_ENC_SEL (1L << 11) |
| 111 | #define QCOM_ICE_STREAM1_NOT_EXPECTED_CONF_IDX (1L << 12) |
| 112 | #define QCOM_ICE_STREAM2_NOT_EXPECTED_CONF_IDX (1L << 13) |
| 113 | #define QCOM_ICE_STREAM1_NOT_EXPECTED_NEW_TRNS (1L << 14) |
| 114 | #define QCOM_ICE_STREAM2_NOT_EXPECTED_NEW_TRNS (1L << 15) |
| 115 | |
| 116 | #define QCOM_ICE_NON_SEC_IRQ_MASK \ |
| 117 | (QCOM_ICE_STREAM1_PREMATURE_LBA_CHANGE |\ |
| 118 | QCOM_ICE_STREAM2_PREMATURE_LBA_CHANGE |\ |
| 119 | QCOM_ICE_STREAM1_NOT_EXPECTED_LBO |\ |
| 120 | QCOM_ICE_STREAM2_NOT_EXPECTED_LBO |\ |
| 121 | QCOM_ICE_STREAM1_NOT_EXPECTED_DUN |\ |
| 122 | QCOM_ICE_STREAM2_NOT_EXPECTED_DUN |\ |
| 123 | QCOM_ICE_STREAM2_NOT_EXPECTED_DUN |\ |
| 124 | QCOM_ICE_STREAM2_NOT_EXPECTED_DUS |\ |
| 125 | QCOM_ICE_STREAM1_NOT_EXPECTED_DBO |\ |
| 126 | QCOM_ICE_STREAM2_NOT_EXPECTED_DBO |\ |
| 127 | QCOM_ICE_STREAM1_NOT_EXPECTED_ENC_SEL |\ |
| 128 | QCOM_ICE_STREAM2_NOT_EXPECTED_ENC_SEL |\ |
| 129 | QCOM_ICE_STREAM1_NOT_EXPECTED_CONF_IDX |\ |
| 130 | QCOM_ICE_STREAM1_NOT_EXPECTED_NEW_TRNS |\ |
| 131 | QCOM_ICE_STREAM2_NOT_EXPECTED_NEW_TRNS) |
| 132 | |
| 133 | /* QCOM ICE registers from secure side */ |
| 134 | #define QCOM_ICE_TEST_BUS_REG_SECURE_INTR (1L << 28) |
| 135 | #define QCOM_ICE_TEST_BUS_REG_NON_SECURE_INTR (1L << 2) |
| 136 | |
| 137 | #define QCOM_ICE_LUT_KEYS_ICE_SEC_IRQ_STTS 0x2050 |
| 138 | #define QCOM_ICE_LUT_KEYS_ICE_SEC_IRQ_MASK 0x2054 |
| 139 | #define QCOM_ICE_LUT_KEYS_ICE_SEC_IRQ_CLR 0x2058 |
| 140 | |
| 141 | #define QCOM_ICE_STREAM1_PARTIALLY_SET_KEY_USED (1L << 0) |
| 142 | #define QCOM_ICE_STREAM2_PARTIALLY_SET_KEY_USED (1L << 1) |
| 143 | #define QCOM_ICE_QCOMC_DBG_OPEN_EVENT (1L << 30) |
| 144 | #define QCOM_ICE_KEYS_RAM_RESET_COMPLETED (1L << 31) |
| 145 | |
| 146 | #define QCOM_ICE_SEC_IRQ_MASK \ |
| 147 | (QCOM_ICE_STREAM1_PARTIALLY_SET_KEY_USED |\ |
| 148 | QCOM_ICE_STREAM2_PARTIALLY_SET_KEY_USED |\ |
| 149 | QCOM_ICE_QCOMC_DBG_OPEN_EVENT | \ |
| 150 | QCOM_ICE_KEYS_RAM_RESET_COMPLETED) |
| 151 | |
| 152 | |
| 153 | #define qcom_ice_writel(ice, val, reg) \ |
| 154 | writel_relaxed((val), (ice)->mmio + (reg)) |
| 155 | #define qcom_ice_readl(ice, reg) \ |
| 156 | readl_relaxed((ice)->mmio + (reg)) |
| 157 | |
| 158 | |
| 159 | #endif /* _QCOM_INLINE_CRYPTO_ENGINE_REGS_H_ */ |