Sujeev Dias | dd66ce0 | 2016-09-07 11:35:11 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | /* Register offsets from gpi-top */ |
| 14 | #define GPI_GPII_n_CH_k_CNTXT_0_OFFS(n, k) \ |
| 15 | (0x20000 + (0x4000 * (n)) + (0x80 * (k))) |
| 16 | #define GPI_GPII_n_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK (0xFF000000) |
| 17 | #define GPI_GPII_n_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT (24) |
| 18 | #define GPI_GPII_n_CH_k_CNTXT_0_CHSTATE_BMSK (0xF00000) |
| 19 | #define GPI_GPII_n_CH_k_CNTXT_0_CHSTATE_SHFT (20) |
| 20 | #define GPI_GPII_n_CH_k_CNTXT_0_ERINDEX_BMSK (0x7C000) |
| 21 | #define GPI_GPII_n_CH_k_CNTXT_0_ERINDEX_SHFT (14) |
| 22 | #define GPI_GPII_n_CH_k_CNTXT_0_CHID_BMSK (0x1F00) |
| 23 | #define GPI_GPII_n_CH_k_CNTXT_0_CHID_SHFT (8) |
| 24 | #define GPI_GPII_n_CH_k_CNTXT_0_EE_BMSK (0xF0) |
| 25 | #define GPI_GPII_n_CH_k_CNTXT_0_EE_SHFT (4) |
| 26 | #define GPI_GPII_n_CH_k_CNTXT_0_CHTYPE_DIR_BMSK (0x8) |
| 27 | #define GPI_GPII_n_CH_k_CNTXT_0_CHTYPE_DIR_SHFT (3) |
| 28 | #define GPI_GPII_n_CH_k_CNTXT_0_CHTYPE_PROTO_BMSK (0x7) |
| 29 | #define GPI_GPII_n_CH_k_CNTXT_0_CHTYPE_PROTO_SHFT (0) |
| 30 | #define GPI_GPII_n_CH_k_CNTXT_0(el_size, erindex, chtype_dir, chtype_proto) \ |
| 31 | ((el_size << 24) | (erindex << 14) | (chtype_dir << 3) | (chtype_proto)) |
| 32 | #define GPI_CHTYPE_DIR_IN (0) |
| 33 | #define GPI_CHTYPE_DIR_OUT (1) |
| 34 | #define GPI_CHTYPE_PROTO_GPI (0x2) |
| 35 | #define GPI_GPII_n_CH_k_CNTXT_1_R_LENGTH_BMSK (0xFFFF) |
| 36 | #define GPI_GPII_n_CH_k_CNTXT_1_R_LENGTH_SHFT (0) |
| 37 | #define GPI_GPII_n_CH_k_DOORBELL_0_OFFS(n, k) (0x22000 + (0x4000 * (n)) \ |
| 38 | + (0x8 * (k))) |
| 39 | #define GPI_GPII_n_CH_CMD_OFFS(n) (0x23008 + (0x4000 * (n))) |
| 40 | #define GPI_GPII_n_CH_CMD_OPCODE_BMSK (0xFF000000) |
| 41 | #define GPI_GPII_n_CH_CMD_OPCODE_SHFT (24) |
| 42 | #define GPI_GPII_n_CH_CMD_CHID_BMSK (0xFF) |
| 43 | #define GPI_GPII_n_CH_CMD_CHID_SHFT (0) |
| 44 | #define GPI_GPII_n_CH_CMD(opcode, chid) ((opcode << 24) | chid) |
| 45 | #define GPI_GPII_n_CH_CMD_ALLOCATE (0) |
| 46 | #define GPI_GPII_n_CH_CMD_START (1) |
| 47 | #define GPI_GPII_n_CH_CMD_STOP (2) |
| 48 | #define GPI_GPII_n_CH_CMD_RESET (9) |
| 49 | #define GPI_GPII_n_CH_CMD_DE_ALLOC (10) |
| 50 | #define GPI_GPII_n_CH_CMD_UART_SW_STALE (32) |
| 51 | #define GPI_GPII_n_CH_CMD_UART_RFR_READY (33) |
| 52 | #define GPI_GPII_n_CH_CMD_UART_RFR_NOT_READY (34) |
| 53 | |
| 54 | /* EV Context Array */ |
| 55 | #define GPI_GPII_n_EV_CH_k_CNTXT_0_OFFS(n, k) \ |
| 56 | (0x21000 + (0x4000 * (n)) + (0x80 * (k))) |
| 57 | #define GPI_GPII_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK (0xFF000000) |
| 58 | #define GPI_GPII_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT (24) |
| 59 | #define GPI_GPII_n_EV_CH_k_CNTXT_0_CHSTATE_BMSK (0xF00000) |
| 60 | #define GPI_GPII_n_EV_CH_k_CNTXT_0_CHSTATE_SHFT (20) |
| 61 | #define GPI_GPII_n_EV_CH_k_CNTXT_0_INTYPE_BMSK (0x10000) |
| 62 | #define GPI_GPII_n_EV_CH_k_CNTXT_0_INTYPE_SHFT (16) |
| 63 | #define GPI_GPII_n_EV_CH_k_CNTXT_0_EVCHID_BMSK (0xFF00) |
| 64 | #define GPI_GPII_n_EV_CH_k_CNTXT_0_EVCHID_SHFT (8) |
| 65 | #define GPI_GPII_n_EV_CH_k_CNTXT_0_EE_BMSK (0xF0) |
| 66 | #define GPI_GPII_n_EV_CH_k_CNTXT_0_EE_SHFT (4) |
| 67 | #define GPI_GPII_n_EV_CH_k_CNTXT_0_CHTYPE_BMSK (0xF) |
| 68 | #define GPI_GPII_n_EV_CH_k_CNTXT_0_CHTYPE_SHFT (0) |
| 69 | #define GPI_GPII_n_EV_CH_k_CNTXT_0(el_size, intype, chtype) \ |
| 70 | ((el_size << 24) | (intype << 16) | (chtype)) |
| 71 | #define GPI_INTTYPE_IRQ (1) |
| 72 | #define GPI_CHTYPE_GPI_EV (0x2) |
| 73 | #define GPI_GPII_n_EV_CH_k_CNTXT_1_R_LENGTH_BMSK (0xFFFF) |
| 74 | #define GPI_GPII_n_EV_CH_k_CNTXT_1_R_LENGTH_SHFT (0) |
| 75 | |
| 76 | enum CNTXT_OFFS { |
| 77 | CNTXT_0_CONFIG = 0x0, |
| 78 | CNTXT_1_R_LENGTH = 0x4, |
| 79 | CNTXT_2_RING_BASE_LSB = 0x8, |
| 80 | CNTXT_3_RING_BASE_MSB = 0xC, |
| 81 | CNTXT_4_RING_RP_LSB = 0x10, |
| 82 | CNTXT_5_RING_RP_MSB = 0x14, |
| 83 | CNTXT_6_RING_WP_LSB = 0x18, |
| 84 | CNTXT_7_RING_WP_MSB = 0x1C, |
| 85 | CNTXT_8_RING_INT_MOD = 0x20, |
| 86 | CNTXT_9_RING_INTVEC = 0x24, |
| 87 | CNTXT_10_RING_MSI_LSB = 0x28, |
| 88 | CNTXT_11_RING_MSI_MSB = 0x2C, |
| 89 | CNTXT_12_RING_RP_UPDATE_LSB = 0x30, |
| 90 | CNTXT_13_RING_RP_UPDATE_MSB = 0x34, |
| 91 | }; |
| 92 | |
| 93 | #define GPI_GPII_n_EV_CH_k_DOORBELL_0_OFFS(n, k) \ |
| 94 | (0x22100 + (0x4000 * (n)) + (0x8 * (k))) |
| 95 | #define GPI_GPII_n_EV_CH_CMD_OFFS(n) \ |
| 96 | (0x23010 + (0x4000 * (n))) |
| 97 | #define GPI_GPII_n_EV_CH_CMD_OPCODE_BMSK (0xFF000000) |
| 98 | #define GPI_GPII_n_EV_CH_CMD_OPCODE_SHFT (24) |
| 99 | #define GPI_GPII_n_EV_CH_CMD_CHID_BMSK (0xFF) |
| 100 | #define GPI_GPII_n_EV_CH_CMD_CHID_SHFT (0) |
| 101 | #define GPI_GPII_n_EV_CH_CMD(opcode, chid) \ |
| 102 | ((opcode << 24) | chid) |
| 103 | #define GPI_GPII_n_EV_CH_CMD_ALLOCATE (0x00) |
| 104 | #define GPI_GPII_n_EV_CH_CMD_RESET (0x09) |
| 105 | #define GPI_GPII_n_EV_CH_CMD_DE_ALLOC (0x0A) |
| 106 | |
| 107 | #define GPI_GPII_n_CNTXT_TYPE_IRQ_OFFS(n) \ |
| 108 | (0x23080 + (0x4000 * (n))) |
| 109 | |
| 110 | /* mask type register */ |
| 111 | #define GPI_GPII_n_CNTXT_TYPE_IRQ_MSK_OFFS(n) \ |
| 112 | (0x23088 + (0x4000 * (n))) |
| 113 | #define GPI_GPII_n_CNTXT_TYPE_IRQ_MSK_BMSK (0x7F) |
| 114 | #define GPI_GPII_n_CNTXT_TYPE_IRQ_MSK_SHFT (0) |
| 115 | #define GPI_GPII_n_CNTXT_TYPE_IRQ_MSK_GENERAL (0x40) |
| 116 | #define GPI_GPII_n_CNTXT_TYPE_IRQ_MSK_INTER_GPII_EV_CTRL (0x20) |
| 117 | #define GPI_GPII_n_CNTXT_TYPE_IRQ_MSK_INTER_GPII_CH_CTRL (0x10) |
| 118 | #define GPI_GPII_n_CNTXT_TYPE_IRQ_MSK_IEOB (0x08) |
| 119 | #define GPI_GPII_n_CNTXT_TYPE_IRQ_MSK_GLOB (0x04) |
| 120 | #define GPI_GPII_n_CNTXT_TYPE_IRQ_MSK_EV_CTRL (0x02) |
| 121 | #define GPI_GPII_n_CNTXT_TYPE_IRQ_MSK_CH_CTRL (0x01) |
| 122 | |
| 123 | #define GPI_GPII_n_CNTXT_SRC_GPII_CH_IRQ_OFFS(n) \ |
| 124 | (0x23090 + (0x4000 * (n))) |
| 125 | #define GPI_GPII_n_CNTXT_SRC_EV_CH_IRQ_OFFS(n) \ |
| 126 | (0x23094 + (0x4000 * (n))) |
| 127 | |
| 128 | /* Mask channel control interrupt register */ |
| 129 | #define GPI_GPII_n_CNTXT_SRC_CH_IRQ_MSK_OFFS(n) \ |
| 130 | (0x23098 + (0x4000 * (n))) |
| 131 | #define GPI_GPII_n_CNTXT_SRC_CH_IRQ_MSK_BMSK (0x3) |
| 132 | #define GPI_GPII_n_CNTXT_SRC_CH_IRQ_MSK_SHFT (0) |
| 133 | |
| 134 | /* Mask event control interrupt register */ |
| 135 | #define GPI_GPII_n_CNTXT_SRC_EV_CH_IRQ_MSK_OFFS(n) \ |
| 136 | (0x2309C + (0x4000 * (n))) |
| 137 | #define GPI_GPII_n_CNTXT_SRC_EV_CH_IRQ_MSK_BMSK (0x1) |
| 138 | #define GPI_GPII_n_CNTXT_SRC_EV_CH_IRQ_MSK_SHFT (0) |
| 139 | |
| 140 | #define GPI_GPII_n_CNTXT_SRC_CH_IRQ_CLR_OFFS(n) \ |
| 141 | (0x230A0 + (0x4000 * (n))) |
| 142 | #define GPI_GPII_n_CNTXT_SRC_EV_CH_IRQ_CLR_OFFS(n) \ |
| 143 | (0x230A4 + (0x4000 * (n))) |
| 144 | #define GPI_GPII_n_CNTXT_SRC_IEOB_IRQ_OFFS(n) \ |
| 145 | (0x230B0 + (0x4000 * (n))) |
| 146 | |
| 147 | /* Mask event interrupt register */ |
| 148 | #define GPI_GPII_n_CNTXT_SRC_IEOB_IRQ_MSK_OFFS(n) \ |
| 149 | (0x230B8 + (0x4000 * (n))) |
| 150 | #define GPI_GPII_n_CNTXT_SRC_IEOB_IRQ_MSK_BMSK (0x1) |
| 151 | #define GPI_GPII_n_CNTXT_SRC_IEOB_IRQ_MSK_SHFT (0) |
| 152 | |
| 153 | #define GPI_GPII_n_CNTXT_SRC_IEOB_IRQ_CLR_OFFS(n) \ |
| 154 | (0x230C0 + (0x4000 * (n))) |
| 155 | #define GPI_GPII_n_CNTXT_GLOB_IRQ_STTS_OFFS(n) \ |
| 156 | (0x23100 + (0x4000 * (n))) |
| 157 | #define GPI_GLOB_IRQ_ERROR_INT_MSK (0x1) |
| 158 | #define GPI_GLOB_IRQ_GP_INT1_MSK (0x2) |
| 159 | #define GPI_GLOB_IRQ_GP_INT2_MSK (0x4) |
| 160 | #define GPI_GLOB_IRQ_GP_INT3_MSK (0x8) |
| 161 | |
| 162 | /* GPII specific Global - Enable bit register */ |
| 163 | #define GPI_GPII_n_CNTXT_GLOB_IRQ_EN_OFFS(n) \ |
| 164 | (0x23108 + (0x4000 * (n))) |
| 165 | #define GPI_GPII_n_CNTXT_GLOB_IRQ_EN_BMSK (0xF) |
| 166 | #define GPI_GPII_n_CNTXT_GLOB_IRQ_EN_SHFT (0) |
| 167 | #define GPI_GPII_n_CNTXT_GLOB_IRQ_EN_GP_INT3 (0x8) |
| 168 | #define GPI_GPII_n_CNTXT_GLOB_IRQ_EN_GP_INT2 (0x4) |
| 169 | #define GPI_GPII_n_CNTXT_GLOB_IRQ_EN_GP_INT1 (0x2) |
| 170 | #define GPI_GPII_n_CNTXT_GLOB_IRQ_EN_ERROR_INT (0x1) |
| 171 | |
| 172 | #define GPI_GPII_n_CNTXT_GLOB_IRQ_CLR_OFFS(n) \ |
| 173 | (0x23110 + (0x4000 * (n))) |
| 174 | #define GPI_GPII_n_CNTXT_GPII_IRQ_STTS_OFFS(n) \ |
| 175 | (0x23118 + (0x4000 * (n))) |
| 176 | |
| 177 | /* GPII general interrupt - Enable bit register */ |
| 178 | #define GPI_GPII_n_CNTXT_GPII_IRQ_EN_OFFS(n) \ |
| 179 | (0x23120 + (0x4000 * (n))) |
| 180 | #define GPI_GPII_n_CNTXT_GPII_IRQ_EN_BMSK (0xF) |
| 181 | #define GPI_GPII_n_CNTXT_GPII_IRQ_EN_SHFT (0) |
| 182 | #define GPI_GPII_n_CNTXT_GPII_IRQ_EN_STACK_OVRFLOW (0x8) |
| 183 | #define GPI_GPII_n_CNTXT_GLOB_IRQ_EN_CMD_FIFO_OVRFLOW (0x4) |
| 184 | #define GPI_GPII_n_CNTXT_GLOB_IRQ_EN_BUS_ERROR (0x2) |
| 185 | #define GPI_GPII_n_CNTXT_GLOB_IRQ_EN_BREAK_POINT (0x1) |
| 186 | |
| 187 | #define GPI_GPII_n_CNTXT_GPII_IRQ_CLR_OFFS(n) \ |
| 188 | (0x23128 + (0x4000 * (n))) |
| 189 | |
| 190 | /* GPII Interrupt Type register */ |
| 191 | #define GPI_GPII_n_CNTXT_INTSET_OFFS(n) \ |
| 192 | (0x23180 + (0x4000 * (n))) |
| 193 | #define GPI_GPII_n_CNTXT_INTSET_BMSK (0x1) |
| 194 | #define GPI_GPII_n_CNTXT_INTSET_SHFT (0) |
| 195 | |
| 196 | #define GPI_GPII_n_CNTXT_MSI_BASE_LSB_OFFS(n) \ |
| 197 | (0x23188 + (0x4000 * (n))) |
| 198 | #define GPI_GPII_n_CNTXT_MSI_BASE_MSB_OFFS(n) \ |
| 199 | (0x2318C + (0x4000 * (n))) |
| 200 | #define GPI_GPII_n_CNTXT_SCRATCH_0_OFFS(n) \ |
| 201 | (0x23400 + (0x4000 * (n))) |
| 202 | #define GPI_GPII_n_CNTXT_SCRATCH_1_OFFS(n) \ |
| 203 | (0x23404 + (0x4000 * (n))) |
| 204 | |
| 205 | #define GPI_GPII_n_ERROR_LOG_OFFS(n) \ |
| 206 | (0x23200 + (0x4000 * (n))) |
| 207 | #define GPI_GPII_n_ERROR_LOG_CLR_OFFS(n) \ |
| 208 | (0x23210 + (0x4000 * (n))) |
| 209 | |
| 210 | /* QOS Registers */ |
| 211 | #define GPI_GPII_n_CH_k_QOS_OFFS(n, k) \ |
| 212 | (0x2005C + (0x4000 * (n)) + (0x80 * (k))) |
| 213 | |
| 214 | /* Scratch registeres */ |
| 215 | #define GPI_GPII_n_CH_k_SCRATCH_0_OFFS(n, k) \ |
| 216 | (0x20060 + (0x4000 * (n)) + (0x80 * (k))) |
| 217 | #define GPI_GPII_n_CH_K_SCRATCH_0(pair, proto, seid) \ |
| 218 | ((pair << 16) | (proto << 4) | seid) |
| 219 | #define GPI_GPII_n_CH_k_SCRATCH_1_OFFS(n, k) \ |
| 220 | (0x20064 + (0x4000 * (n)) + (0x80 * (k))) |
| 221 | #define GPI_GPII_n_CH_k_SCRATCH_2_OFFS(n, k) \ |
| 222 | (0x20068 + (0x4000 * (n)) + (0x80 * (k))) |
| 223 | #define GPI_GPII_n_CH_k_SCRATCH_3_OFFS(n, k) \ |
| 224 | (0x2006C + (0x4000 * (n)) + (0x80 * (k))) |