blob: 11d23e5b2da74f3ac43698ab7f3f21e814c75468 [file] [log] [blame]
Umang Chheda599b0962020-01-20 17:15:54 +05301/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
Fenglin Wu3840f8e2018-04-27 13:48:43 +08002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
Fenglin Wu22e4cf12018-08-01 15:07:28 +080013#include <linux/debugfs.h>
Fenglin Wu3840f8e2018-04-27 13:48:43 +080014#include <linux/device.h>
15#include <linux/err.h>
Fenglin Wu22e4cf12018-08-01 15:07:28 +080016#include <linux/fs.h>
Fenglin Wu30f10b22018-06-15 07:49:23 +080017#include <linux/hrtimer.h>
Fenglin Wu3840f8e2018-04-27 13:48:43 +080018#include <linux/init.h>
19#include <linux/input.h>
20#include <linux/interrupt.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/of.h>
24#include <linux/of_address.h>
25#include <linux/platform_device.h>
26#include <linux/pwm.h>
Umang Chheda599b0962020-01-20 17:15:54 +053027#include <linux/qpnp/qpnp-misc.h>
Fenglin Wu3840f8e2018-04-27 13:48:43 +080028#include <linux/regmap.h>
29#include <linux/regulator/consumer.h>
Fenglin Wu22e4cf12018-08-01 15:07:28 +080030#include <linux/slab.h>
Fenglin Wu3840f8e2018-04-27 13:48:43 +080031#include <linux/types.h>
Fenglin Wu22e4cf12018-08-01 15:07:28 +080032#include <linux/uaccess.h>
Fenglin Wu3840f8e2018-04-27 13:48:43 +080033
34enum actutor_type {
35 ACT_LRA,
36 ACT_ERM,
37};
38
39enum lra_res_sig_shape {
40 RES_SIG_SINE,
41 RES_SIG_SQUARE,
42};
43
44enum lra_auto_res_mode {
45 AUTO_RES_MODE_ZXD,
46 AUTO_RES_MODE_QWD,
47};
48
49enum wf_src {
50 INT_WF_VMAX,
51 INT_WF_BUFFER,
52 EXT_WF_AUDIO,
53 EXT_WF_PWM,
54};
55
56enum haptics_custom_effect_param {
57 CUSTOM_DATA_EFFECT_IDX,
58 CUSTOM_DATA_TIMEOUT_SEC_IDX,
59 CUSTOM_DATA_TIMEOUT_MSEC_IDX,
60 CUSTOM_DATA_LEN,
61};
62
63/* common definitions */
64#define HAP_BRAKE_PATTERN_MAX 4
65#define HAP_WAVEFORM_BUFFER_MAX 8
66#define HAP_VMAX_MV_DEFAULT 1800
67#define HAP_VMAX_MV_MAX 3596
68#define HAP_ILIM_MA_DEFAULT 400
69#define HAP_ILIM_MA_MAX 800
70#define HAP_PLAY_RATE_US_DEFAULT 5715
71#define HAP_PLAY_RATE_US_MAX 20475
72#define HAP_PLAY_RATE_US_LSB 5
73#define VMAX_MIN_PLAY_TIME_US 20000
74#define HAP_SC_DET_MAX_COUNT 5
75#define HAP_SC_DET_TIME_US 1000000
76#define FF_EFFECT_COUNT_MAX 32
Fenglin Wu802427a2018-08-31 16:07:59 +080077#define HAP_DISABLE_DELAY_USEC 1000
Fenglin Wu3840f8e2018-04-27 13:48:43 +080078
79/* haptics module register definitions */
80#define REG_HAP_STATUS1 0x0A
81#define HAP_SC_DET_BIT BIT(3)
82#define HAP_BUSY_BIT BIT(1)
83
84#define REG_HAP_EN_CTL1 0x46
85#define HAP_EN_BIT BIT(7)
86
87#define REG_HAP_EN_CTL2 0x48
88#define HAP_AUTO_STANDBY_EN_BIT BIT(1)
89#define HAP_BRAKE_EN_BIT BIT(0)
90
91#define REG_HAP_EN_CTL3 0x4A
92#define HAP_HBRIDGE_EN_BIT BIT(7)
93#define HAP_PWM_SIGNAL_EN_BIT BIT(6)
94#define HAP_ILIM_EN_BIT BIT(5)
95#define HAP_ILIM_CC_EN_BIT BIT(4)
96#define HAP_AUTO_RES_RBIAS_EN_BIT BIT(3)
97#define HAP_DAC_EN_BIT BIT(2)
98#define HAP_ZX_HYST_EN_BIT BIT(1)
99#define HAP_PWM_CTL_EN_BIT BIT(0)
100
101#define REG_HAP_AUTO_RES_CTRL 0x4B
102#define HAP_AUTO_RES_EN_BIT BIT(7)
103#define HAP_SEL_AUTO_RES_PERIOD BIT(6)
104#define HAP_AUTO_RES_CNT_ERR_DELTA_MASK GENMASK(5, 4)
105#define HAP_AUTO_RES_CNT_ERR_DELTA_SHIFT 4
106#define HAP_AUTO_RES_ERR_RECOVERY_BIT BIT(3)
107#define HAP_AUTO_RES_EN_DLY_MASK GENMASK(2, 0)
108#define AUTO_RES_CNT_ERR_DELTA(x) (x << HAP_AUTO_RES_CNT_ERR_DELTA_SHIFT)
109#define AUTO_RES_EN_DLY(x) x
110
111#define REG_HAP_CFG1 0x4C
112#define REG_HAP_CFG2 0x4D
113#define HAP_LRA_RES_TYPE_BIT BIT(0)
114
115#define REG_HAP_SEL 0x4E
116#define HAP_WF_SOURCE_MASK GENMASK(5, 4)
117#define HAP_WF_SOURCE_SHIFT 4
118#define HAP_WF_TRIGGER_BIT BIT(0)
119#define HAP_WF_SOURCE_VMAX (0 << HAP_WF_SOURCE_SHIFT)
120#define HAP_WF_SOURCE_BUFFER (1 << HAP_WF_SOURCE_SHIFT)
121#define HAP_WF_SOURCE_AUDIO (2 << HAP_WF_SOURCE_SHIFT)
122#define HAP_WF_SOURCE_PWM (3 << HAP_WF_SOURCE_SHIFT)
123
124#define REG_HAP_AUTO_RES_CFG 0x4F
125#define HAP_AUTO_RES_MODE_BIT BIT(7)
126#define HAP_AUTO_RES_MODE_SHIFT 7
127#define HAP_AUTO_RES_CAL_DURATON_MASK GENMASK(6, 5)
128#define HAP_CAL_EOP_EN_BIT BIT(3)
129#define HAP_CAL_PERIOD_MASK GENMASK(2, 0)
130#define HAP_CAL_OPT3_EVERY_8_PERIOD 2
131
132#define REG_HAP_SLEW_CFG 0x50
133#define REG_HAP_VMAX_CFG 0x51
134#define HAP_VMAX_SIGN_BIT BIT(7)
135#define HAP_VMAX_OVD_BIT BIT(6)
136#define HAP_VMAX_MV_MASK GENMASK(5, 1)
137#define HAP_VMAX_MV_SHIFT 1
138#define HAP_VMAX_MV_LSB 116
139
140#define REG_HAP_ILIM_CFG 0x52
141#define REG_HAP_SC_DEB_CFG 0x53
142#define REG_HAP_RATE_CFG1 0x54
143#define REG_HAP_RATE_CFG2 0x55
144#define REG_HAP_INTERNAL_PWM 0x56
145#define REG_HAP_EXTERNAL_PWM 0x57
146#define REG_HAP_PWM 0x58
147
148#define REG_HAP_SC_CLR 0x59
149#define HAP_SC_CLR_BIT BIT(0)
150
151#define REG_HAP_ZX_CFG 0x5A
152#define HAP_ZX_DET_DEB_MASK GENMASK(2, 0)
153#define ZX_DET_DEB_10US 0
154#define ZX_DET_DEB_20US 1
155#define ZX_DET_DEB_40US 2
156#define ZX_DET_DEB_80US 3
157
158#define REG_HAP_BRAKE 0x5C
159#define HAP_BRAKE_PATTERN_MASK 0x3
160#define HAP_BRAKE_PATTERN_SHIFT 2
161
162#define REG_HAP_WF_REPEAT 0x5E
163#define HAP_WF_REPEAT_MASK GENMASK(6, 4)
164#define HAP_WF_REPEAT_SHIFT 4
165#define HAP_WF_S_REPEAT_MASK GENMASK(1, 0)
166
167#define REG_HAP_WF_S1 0x60
168#define HAP_WF_SIGN_BIT BIT(7)
169#define HAP_WF_OVD_BIT BIT(6)
170#define HAP_WF_AMP_BIT GENMASK(5, 1)
171#define HAP_WF_AMP_SHIFT 1
172
173#define REG_HAP_PLAY 0x70
174#define HAP_PLAY_BIT BIT(7)
175
176#define REG_HAP_SEC_ACCESS 0xD0
Umang Chheda599b0962020-01-20 17:15:54 +0530177#define REG_HAP_PERPH_RESET_CTL3 0xDA
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800178
179struct qti_hap_effect {
180 int id;
181 u8 *pattern;
182 int pattern_length;
183 u16 play_rate_us;
Fenglin Wu659c0042018-07-18 11:02:43 +0800184 u16 vmax_mv;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800185 u8 wf_repeat_n;
186 u8 wf_s_repeat_n;
Fenglin Wucf1a1b92018-06-11 07:39:44 +0800187 u8 brake[HAP_BRAKE_PATTERN_MAX];
188 int brake_pattern_length;
189 bool brake_en;
190 bool lra_auto_res_disable;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800191};
192
193struct qti_hap_play_info {
194 struct qti_hap_effect *effect;
195 u16 vmax_mv;
196 int length_us;
197 int playing_pos;
198 bool playing_pattern;
199};
200
201struct qti_hap_config {
202 enum actutor_type act_type;
203 enum lra_res_sig_shape lra_shape;
204 enum lra_auto_res_mode lra_auto_res_mode;
205 enum wf_src ext_src;
206 u16 vmax_mv;
207 u16 ilim_ma;
208 u16 play_rate_us;
Fenglin Wucf1a1b92018-06-11 07:39:44 +0800209 bool lra_allow_variable_play_rate;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800210 bool use_ext_wf_src;
211};
212
213struct qti_hap_chip {
214 struct platform_device *pdev;
215 struct device *dev;
216 struct regmap *regmap;
217 struct input_dev *input_dev;
218 struct pwm_device *pwm_dev;
219 struct qti_hap_config config;
220 struct qti_hap_play_info play;
221 struct qti_hap_effect *predefined;
222 struct qti_hap_effect constant;
223 struct regulator *vdd_supply;
Fenglin Wu30f10b22018-06-15 07:49:23 +0800224 struct hrtimer stop_timer;
Fenglin Wu802427a2018-08-31 16:07:59 +0800225 struct hrtimer hap_disable_timer;
Fenglin Wu22e4cf12018-08-01 15:07:28 +0800226 struct dentry *hap_debugfs;
Umang Chheda599b0962020-01-20 17:15:54 +0530227 struct notifier_block twm_nb;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800228 spinlock_t bus_lock;
229 ktime_t last_sc_time;
230 int play_irq;
231 int sc_irq;
232 int effects_count;
233 int sc_det_count;
234 u16 reg_base;
235 bool perm_disable;
236 bool play_irq_en;
237 bool vdd_enabled;
Umang Chheda599b0962020-01-20 17:15:54 +0530238 bool twm_state;
239 bool haptics_ext_pin_twm;
240};
241
242struct hap_addr_val {
243 u16 addr;
244 u8 value;
245};
246
247static struct hap_addr_val twm_ext_cfg[] = {
248 {REG_HAP_PLAY, 0x00}, /* Stop playing haptics waveform */
249 {REG_HAP_PERPH_RESET_CTL3, 0x0D}, /* Disable SHUTDOWN1_RB reset */
250 {REG_HAP_SEL, 0x01}, /* Configure for external-pin mode */
251 {REG_HAP_EN_CTL1, 0x80}, /* Enable haptics driver */
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800252};
253
Anirudh Ghayalb195a982020-05-07 15:10:20 +0530254static struct hap_addr_val twm_cfg[] = {
255 {REG_HAP_PLAY, 0x00}, /* Stop playing haptics waveform */
256 {REG_HAP_SEL, 0x00}, /* Configure for cmd mode */
257 {REG_HAP_EN_CTL1, 0x00}, /* Enable haptics driver */
258 {REG_HAP_PERPH_RESET_CTL3, 0x0D}, /* Disable SHUTDOWN1_RB reset */
259};
260
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800261static int wf_repeat[8] = {1, 2, 4, 8, 16, 32, 64, 128};
262static int wf_s_repeat[4] = {1, 2, 4, 8};
263
Anirudh Ghayal760e91d2020-04-13 15:33:39 +0530264static int twm_sys_enable;
265module_param_named(
266 haptics_twm, twm_sys_enable, int, 0600
267);
268
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800269static inline bool is_secure(u8 addr)
270{
271 return ((addr & 0xFF) > 0xD0);
272}
273
274static int qti_haptics_read(struct qti_hap_chip *chip,
275 u8 addr, u8 *val, int len)
276{
277 int rc = 0;
278 unsigned long flags;
279
280 spin_lock_irqsave(&chip->bus_lock, flags);
281
282 rc = regmap_bulk_read(chip->regmap, chip->reg_base + addr, val, len);
283 if (rc < 0)
284 dev_err(chip->dev, "Reading addr 0x%x failed, rc=%d\n",
285 addr, rc);
286 spin_unlock_irqrestore(&chip->bus_lock, flags);
287
288 return rc;
289}
290
291static int qti_haptics_write(struct qti_hap_chip *chip,
292 u8 addr, u8 *val, int len)
293{
294 int rc = 0, i;
295 unsigned long flags;
296
297 spin_lock_irqsave(&chip->bus_lock, flags);
298 if (is_secure(addr)) {
299 for (i = 0; i < len; i++) {
300 rc = regmap_write(chip->regmap,
301 chip->reg_base + REG_HAP_SEC_ACCESS,
302 0xA5);
303 if (rc < 0) {
304 dev_err(chip->dev, "write SEC_ACCESS failed, rc=%d\n",
305 rc);
306 goto unlock;
307 }
308
309 rc = regmap_write(chip->regmap,
310 chip->reg_base + addr + i, val[i]);
311 if (rc < 0) {
312 dev_err(chip->dev, "write val 0x%x to addr 0x%x failed, rc=%d\n",
313 val[i], addr + i, rc);
314 goto unlock;
315 }
316 }
317 } else {
318 if (len > 1)
319 rc = regmap_bulk_write(chip->regmap,
320 chip->reg_base + addr, val, len);
321 else
322 rc = regmap_write(chip->regmap,
323 chip->reg_base + addr, *val);
324
325 if (rc < 0)
326 dev_err(chip->dev, "write addr 0x%x failed, rc=%d\n",
327 addr, rc);
328 }
329
330 for (i = 0; i < len; i++)
331 dev_dbg(chip->dev, "Update addr 0x%x to val 0x%x\n",
332 addr + i, val[i]);
333
334unlock:
335 spin_unlock_irqrestore(&chip->bus_lock, flags);
336 return rc;
337}
338
339static int qti_haptics_masked_write(struct qti_hap_chip *chip, u8 addr,
340 u8 mask, u8 val)
341{
342 int rc;
343 unsigned long flags;
344
345 spin_lock_irqsave(&chip->bus_lock, flags);
346 if (is_secure(addr)) {
347 rc = regmap_write(chip->regmap,
348 chip->reg_base + REG_HAP_SEC_ACCESS,
349 0xA5);
350 if (rc < 0) {
351 dev_err(chip->dev, "write SEC_ACCESS failed, rc=%d\n",
352 rc);
353 goto unlock;
354 }
355 }
356
357 rc = regmap_update_bits(chip->regmap, chip->reg_base + addr, mask, val);
358 if (rc < 0)
359 dev_err(chip->dev, "Update addr 0x%x to val 0x%x with mask 0x%x failed, rc=%d\n",
360 addr, val, mask, rc);
361
362 dev_dbg(chip->dev, "Update addr 0x%x to val 0x%x with mask 0x%x\n",
363 addr, val, mask);
364unlock:
365 spin_unlock_irqrestore(&chip->bus_lock, flags);
366
367 return rc;
368}
369
370static void construct_constant_waveform_in_pattern(
371 struct qti_hap_play_info *play)
372{
373 struct qti_hap_chip *chip = container_of(play,
374 struct qti_hap_chip, play);
375 struct qti_hap_config *config = &chip->config;
376 struct qti_hap_effect *effect = play->effect;
377 int total_samples, samples, left, magnitude, i, j, k;
378 int delta = INT_MAX, delta_min = INT_MAX;
379
380 /* Using play_rate_us in config for constant waveform */
381 effect->play_rate_us = config->play_rate_us;
382 total_samples = play->length_us / effect->play_rate_us;
383 left = play->length_us % effect->play_rate_us;
384
385 if (total_samples <= HAP_WAVEFORM_BUFFER_MAX) {
386 effect->pattern_length = total_samples;
387 effect->wf_s_repeat_n = 0;
388 effect->wf_repeat_n = 0;
389 } else {
390 /*
391 * Find a closest setting to achieve the constant waveform
392 * with the required length by using buffer waveform source:
393 * play_length_us = pattern_length * wf_s_repeat_n
394 * * wf_repeat_n * play_rate_us
395 */
396 for (i = 0; i < ARRAY_SIZE(wf_repeat); i++) {
397 for (j = 0; j < ARRAY_SIZE(wf_s_repeat); j++) {
398 for (k = 1; k <= HAP_WAVEFORM_BUFFER_MAX; k++) {
399 samples = k * wf_s_repeat[j] *
400 wf_repeat[i];
401 delta = abs(total_samples - samples);
402 if (delta < delta_min) {
403 delta_min = delta;
404 effect->pattern_length = k;
405 effect->wf_s_repeat_n = j;
406 effect->wf_repeat_n = i;
407 }
408 if (samples > total_samples)
409 break;
410 }
411 }
412 }
413 }
414
415 if (left > 0 && effect->pattern_length < HAP_WAVEFORM_BUFFER_MAX)
416 effect->pattern_length++;
417
418 play->length_us = effect->pattern_length * effect->play_rate_us;
419 dev_dbg(chip->dev, "total_samples = %d, pattern_length = %d, wf_s_repeat = %d, wf_repeat = %d\n",
420 total_samples, effect->pattern_length,
421 wf_s_repeat[effect->wf_s_repeat_n],
422 wf_repeat[effect->wf_repeat_n]);
423
424 for (i = 0; i < effect->pattern_length; i++) {
425 magnitude = play->vmax_mv / HAP_VMAX_MV_LSB;
426 effect->pattern[i] = (u8)magnitude << HAP_WF_AMP_SHIFT;
427 }
428}
429
430static int qti_haptics_config_wf_buffer(struct qti_hap_chip *chip)
431{
432 struct qti_hap_play_info *play = &chip->play;
433 struct qti_hap_effect *effect = play->effect;
434 u8 addr, pattern[HAP_WAVEFORM_BUFFER_MAX] = {0};
435 int rc = 0;
436 size_t len;
437
438 if (play->playing_pos == effect->pattern_length) {
439 dev_dbg(chip->dev, "pattern playing done\n");
440 return 0;
441 }
442
443 if (effect->pattern_length - play->playing_pos
444 >= HAP_WAVEFORM_BUFFER_MAX)
445 len = HAP_WAVEFORM_BUFFER_MAX;
446 else
447 len = effect->pattern_length - play->playing_pos;
448
449 dev_dbg(chip->dev, "copy %d bytes start from %d\n",
450 (int)len, play->playing_pos);
451 memcpy(pattern, &effect->pattern[play->playing_pos], len);
452
453 play->playing_pos += len;
454
455 addr = REG_HAP_WF_S1;
456 rc = qti_haptics_write(chip, REG_HAP_WF_S1, pattern,
457 HAP_WAVEFORM_BUFFER_MAX);
458 if (rc < 0)
459 dev_err(chip->dev, "Program WF_SAMPLE failed, rc=%d\n", rc);
460
461 return rc;
462}
463
464static int qti_haptics_config_wf_repeat(struct qti_hap_chip *chip)
465{
466 struct qti_hap_effect *effect = chip->play.effect;
467 u8 addr, mask, val;
468 int rc = 0;
469
470 addr = REG_HAP_WF_REPEAT;
471 mask = HAP_WF_REPEAT_MASK | HAP_WF_S_REPEAT_MASK;
472 val = effect->wf_repeat_n << HAP_WF_REPEAT_SHIFT;
473 val |= effect->wf_s_repeat_n;
474 rc = qti_haptics_masked_write(chip, addr, mask, val);
475 if (rc < 0)
476 dev_err(chip->dev, "Program WF_REPEAT failed, rc=%d\n", rc);
477
478 return rc;
479}
480
481static int qti_haptics_play(struct qti_hap_chip *chip, bool play)
482{
483 int rc = 0;
484 u8 val = play ? HAP_PLAY_BIT : 0;
485
486 rc = qti_haptics_write(chip,
487 REG_HAP_PLAY, &val, 1);
488 if (rc < 0)
489 dev_err(chip->dev, "%s playing haptics failed, rc=%d\n",
490 play ? "start" : "stop", rc);
491
492 return rc;
493}
494
495static int qti_haptics_module_en(struct qti_hap_chip *chip, bool en)
496{
497 int rc = 0;
498 u8 val = en ? HAP_EN_BIT : 0;
499
500 rc = qti_haptics_write(chip,
501 REG_HAP_EN_CTL1, &val, 1);
502 if (rc < 0)
503 dev_err(chip->dev, "%s haptics failed, rc=%d\n",
504 en ? "enable" : "disable", rc);
505
506
507 return rc;
508}
509
510static int qti_haptics_config_vmax(struct qti_hap_chip *chip, int vmax_mv)
511{
512 u8 addr, mask, val;
513 int rc;
514
515 addr = REG_HAP_VMAX_CFG;
516 mask = HAP_VMAX_MV_MASK;
517 val = (vmax_mv / HAP_VMAX_MV_LSB) << HAP_VMAX_MV_SHIFT;
518 rc = qti_haptics_masked_write(chip, addr, mask, val);
519 if (rc < 0)
520 dev_err(chip->dev, "write VMAX_CFG failed, rc=%d\n",
521 rc);
522
523 return rc;
524}
525
526static int qti_haptics_config_wf_src(struct qti_hap_chip *chip,
527 enum wf_src src)
528{
529 u8 addr, mask, val = 0;
530 int rc;
531
532 addr = REG_HAP_SEL;
533 mask = HAP_WF_SOURCE_MASK | HAP_WF_TRIGGER_BIT;
534 val = src << HAP_WF_SOURCE_SHIFT;
535 if (src == EXT_WF_AUDIO || src == EXT_WF_PWM)
536 val |= HAP_WF_TRIGGER_BIT;
537
538 rc = qti_haptics_masked_write(chip, addr, mask, val);
539 if (rc < 0)
540 dev_err(chip->dev, "set HAP_SEL failed, rc=%d\n", rc);
541
542 return rc;
543}
544
545static int qti_haptics_config_play_rate_us(struct qti_hap_chip *chip,
546 int play_rate_us)
547{
548 u8 addr, val[2];
549 int tmp, rc;
550
551 addr = REG_HAP_RATE_CFG1;
552 tmp = play_rate_us / HAP_PLAY_RATE_US_LSB;
553 val[0] = tmp & 0xff;
554 val[1] = (tmp >> 8) & 0xf;
555 rc = qti_haptics_write(chip, addr, val, 2);
556 if (rc < 0)
557 dev_err(chip->dev, "write play_rate failed, rc=%d\n", rc);
558
559 return rc;
560}
561
Fenglin Wu802427a2018-08-31 16:07:59 +0800562static int qti_haptics_brake_enable(struct qti_hap_chip *chip, bool en)
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800563{
564 u8 addr, mask, val;
Fenglin Wu802427a2018-08-31 16:07:59 +0800565 int rc;
566
567 addr = REG_HAP_EN_CTL2;
568 mask = HAP_BRAKE_EN_BIT;
569 val = en ? HAP_BRAKE_EN_BIT : 0;
570 rc = qti_haptics_masked_write(chip, addr, mask, val);
571 if (rc < 0)
572 dev_err(chip->dev, "write BRAKE_EN failed, rc=%d\n", rc);
573
574 return rc;
575}
576
577static int qti_haptics_config_brake(struct qti_hap_chip *chip, u8 *brake)
578{
579 u8 addr, val;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800580 int i, rc;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800581
582 addr = REG_HAP_BRAKE;
583 for (val = 0, i = 0; i < HAP_BRAKE_PATTERN_MAX; i++)
584 val |= (brake[i] & HAP_BRAKE_PATTERN_MASK) <<
585 i * HAP_BRAKE_PATTERN_SHIFT;
586
587 rc = qti_haptics_write(chip, addr, &val, 1);
588 if (rc < 0) {
589 dev_err(chip->dev, "write brake pattern failed, rc=%d\n", rc);
590 return rc;
591 }
Fenglin Wuf3907c82018-07-27 09:06:32 +0800592 /*
593 * Set BRAKE_EN regardless of the brake pattern, this helps to stop
594 * playing immediately once the valid values in WF_Sx are played.
595 */
Fenglin Wu802427a2018-08-31 16:07:59 +0800596 rc = qti_haptics_brake_enable(chip, true);
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800597
598 return rc;
599}
600
Fenglin Wucf1a1b92018-06-11 07:39:44 +0800601static int qti_haptics_lra_auto_res_enable(struct qti_hap_chip *chip, bool en)
602{
603 int rc;
604 u8 addr, val, mask;
605
606 addr = REG_HAP_AUTO_RES_CTRL;
607 mask = HAP_AUTO_RES_EN_BIT;
608 val = en ? HAP_AUTO_RES_EN_BIT : 0;
609 rc = qti_haptics_masked_write(chip, addr, mask, val);
610 if (rc < 0)
611 dev_err(chip->dev, "set AUTO_RES_CTRL failed, rc=%d\n", rc);
612
613 return rc;
614}
615
Fenglin Wu802427a2018-08-31 16:07:59 +0800616#define HAP_CLEAR_PLAYING_RATE_US 15
617static int qti_haptics_clear_settings(struct qti_hap_chip *chip)
618{
619 int rc;
620 u8 pattern[HAP_WAVEFORM_BUFFER_MAX] = {1, 0, 0, 0, 0, 0, 0, 0};
621
622 rc = qti_haptics_brake_enable(chip, false);
623 if (rc < 0)
624 return rc;
625
626 rc = qti_haptics_lra_auto_res_enable(chip, false);
627 if (rc < 0)
628 return rc;
629
630 rc = qti_haptics_config_play_rate_us(chip, HAP_CLEAR_PLAYING_RATE_US);
631 if (rc < 0)
632 return rc;
633
634 rc = qti_haptics_write(chip, REG_HAP_WF_S1, pattern,
635 HAP_WAVEFORM_BUFFER_MAX);
636 if (rc < 0)
637 return rc;
638
639 rc = qti_haptics_play(chip, true);
640 if (rc < 0)
641 return rc;
642
643 rc = qti_haptics_play(chip, false);
644 if (rc < 0)
645 return rc;
646
647 return 0;
648}
649
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800650static int qti_haptics_load_constant_waveform(struct qti_hap_chip *chip)
651{
652 struct qti_hap_play_info *play = &chip->play;
653 struct qti_hap_config *config = &chip->config;
654 int rc = 0;
655
Fenglin Wuf3907c82018-07-27 09:06:32 +0800656 rc = qti_haptics_config_play_rate_us(chip, config->play_rate_us);
657 if (rc < 0)
658 return rc;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800659 /*
660 * Using VMAX waveform source if playing length is >= 20ms,
661 * otherwise using buffer waveform source and calculate the
662 * pattern length and repeating times to achieve accurate
663 * playing time accuracy.
664 */
665 if (play->length_us >= VMAX_MIN_PLAY_TIME_US) {
666 rc = qti_haptics_config_vmax(chip, play->vmax_mv);
667 if (rc < 0)
668 return rc;
669
Fenglin Wucf1a1b92018-06-11 07:39:44 +0800670 /* Enable Auto-Resonance when VMAX wf-src is selected */
671 if (config->act_type == ACT_LRA) {
672 rc = qti_haptics_lra_auto_res_enable(chip, true);
673 if (rc < 0)
674 return rc;
675 }
676
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800677 /* Set WF_SOURCE to VMAX */
678 rc = qti_haptics_config_wf_src(chip, INT_WF_VMAX);
679 if (rc < 0)
680 return rc;
681
682 play->playing_pattern = false;
Fenglin Wu802427a2018-08-31 16:07:59 +0800683 play->effect = NULL;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800684 } else {
685 rc = qti_haptics_config_vmax(chip, config->vmax_mv);
686 if (rc < 0)
687 return rc;
688
689 play->effect = &chip->constant;
690 play->playing_pos = 0;
691 /* Format and config waveform in patterns */
692 construct_constant_waveform_in_pattern(play);
693 rc = qti_haptics_config_wf_buffer(chip);
694 if (rc < 0)
695 return rc;
696
697 rc = qti_haptics_config_wf_repeat(chip);
698 if (rc < 0)
699 return rc;
700
701 /* Set WF_SOURCE to buffer */
702 rc = qti_haptics_config_wf_src(chip, INT_WF_BUFFER);
703 if (rc < 0)
704 return rc;
705
706 play->playing_pattern = true;
707 }
708
709 return 0;
710}
711
712static int qti_haptics_load_predefined_effect(struct qti_hap_chip *chip,
713 int effect_idx)
714{
715 struct qti_hap_play_info *play = &chip->play;
716 struct qti_hap_config *config = &chip->config;
717 int rc = 0;
718
719 if (effect_idx >= chip->effects_count)
720 return -EINVAL;
721
722 play->effect = &chip->predefined[effect_idx];
723 play->playing_pos = 0;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800724 rc = qti_haptics_config_vmax(chip, play->vmax_mv);
725 if (rc < 0)
726 return rc;
727
Fenglin Wucf1a1b92018-06-11 07:39:44 +0800728 rc = qti_haptics_config_play_rate_us(chip, play->effect->play_rate_us);
729 if (rc < 0)
730 return rc;
731
732 if (config->act_type == ACT_LRA) {
733 rc = qti_haptics_lra_auto_res_enable(chip,
734 !play->effect->lra_auto_res_disable);
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800735 if (rc < 0)
736 return rc;
737 }
738
Fenglin Wucf1a1b92018-06-11 07:39:44 +0800739 /* Set brake pattern in the effect */
740 rc = qti_haptics_config_brake(chip, play->effect->brake);
741 if (rc < 0)
742 return rc;
743
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800744 rc = qti_haptics_config_wf_buffer(chip);
745 if (rc < 0)
746 return rc;
747
748 rc = qti_haptics_config_wf_repeat(chip);
749 if (rc < 0)
750 return rc;
751
752 /* Set WF_SOURCE to buffer */
753 rc = qti_haptics_config_wf_src(chip, INT_WF_BUFFER);
754 if (rc < 0)
755 return rc;
756
757 play->playing_pattern = true;
758
759 return 0;
760}
761
762static irqreturn_t qti_haptics_play_irq_handler(int irq, void *data)
763{
764 struct qti_hap_chip *chip = (struct qti_hap_chip *)data;
765 struct qti_hap_play_info *play = &chip->play;
766 struct qti_hap_effect *effect = play->effect;
767 int rc;
768
769 dev_dbg(chip->dev, "play_irq triggered\n");
770 if (play->playing_pos == effect->pattern_length) {
771 dev_dbg(chip->dev, "waveform playing done\n");
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800772 if (chip->play_irq_en) {
773 disable_irq_nosync(chip->play_irq);
774 chip->play_irq_en = false;
775 }
776
777 goto handled;
778 }
779
780 /* Config to play remaining patterns */
781 rc = qti_haptics_config_wf_repeat(chip);
782 if (rc < 0)
783 goto handled;
784
785 rc = qti_haptics_config_wf_buffer(chip);
786 if (rc < 0)
787 goto handled;
788
789handled:
790 return IRQ_HANDLED;
791}
792
793static irqreturn_t qti_haptics_sc_irq_handler(int irq, void *data)
794{
795 struct qti_hap_chip *chip = (struct qti_hap_chip *)data;
796 u8 addr, val;
797 ktime_t temp;
798 s64 sc_delta_time_us;
799 int rc;
800
801 dev_dbg(chip->dev, "sc_irq triggered\n");
802 addr = REG_HAP_STATUS1;
803 rc = qti_haptics_read(chip, addr, &val, 1);
804 if (rc < 0) {
805 dev_err(chip->dev, "read HAP_STATUS1 failed, rc=%d\n", rc);
806 goto handled;
807 }
808
809 if (!(val & HAP_SC_DET_BIT))
810 goto handled;
811
812 temp = ktime_get();
813 sc_delta_time_us = ktime_us_delta(temp, chip->last_sc_time);
814 chip->last_sc_time = temp;
815
816 if (sc_delta_time_us > HAP_SC_DET_TIME_US)
817 chip->sc_det_count = 0;
818 else
819 chip->sc_det_count++;
820
821 addr = REG_HAP_SC_CLR;
822 val = HAP_SC_CLR_BIT;
823 rc = qti_haptics_write(chip, addr, &val, 1);
824 if (rc < 0) {
825 dev_err(chip->dev, "write SC_CLR failed, rc=%d\n", rc);
826 goto handled;
827 }
828
829 if (chip->sc_det_count > HAP_SC_DET_MAX_COUNT) {
830 rc = qti_haptics_module_en(chip, false);
831 if (rc < 0)
832 goto handled;
833
834 dev_crit(chip->dev, "Short circuit persists, disable haptics\n");
835 chip->perm_disable = true;
836 }
837
838handled:
839 return IRQ_HANDLED;
840}
841
842static inline void get_play_length(struct qti_hap_play_info *play,
843 int *length_us)
844{
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800845 struct qti_hap_effect *effect = play->effect;
846 int tmp;
847
848 tmp = effect->pattern_length * effect->play_rate_us;
849 tmp *= wf_s_repeat[effect->wf_s_repeat_n];
850 tmp *= wf_repeat[effect->wf_repeat_n];
Fenglin Wucf1a1b92018-06-11 07:39:44 +0800851 if (effect->brake_en)
852 tmp += effect->play_rate_us * effect->brake_pattern_length;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800853
854 *length_us = tmp;
855}
856
857static int qti_haptics_upload_effect(struct input_dev *dev,
858 struct ff_effect *effect, struct ff_effect *old)
859{
860 struct qti_hap_chip *chip = input_get_drvdata(dev);
861 struct qti_hap_config *config = &chip->config;
862 struct qti_hap_play_info *play = &chip->play;
863 int rc = 0, tmp, i;
864 s16 level, data[CUSTOM_DATA_LEN];
Fenglin Wu802427a2018-08-31 16:07:59 +0800865 ktime_t rem;
866 s64 time_us;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800867
Fenglin Wu802427a2018-08-31 16:07:59 +0800868 if (hrtimer_active(&chip->hap_disable_timer)) {
869 rem = hrtimer_get_remaining(&chip->hap_disable_timer);
870 time_us = ktime_to_us(rem);
871 dev_dbg(chip->dev, "waiting for playing clear sequence: %lld us\n",
872 time_us);
873 usleep_range(time_us, time_us + 100);
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800874 }
875
876 switch (effect->type) {
877 case FF_CONSTANT:
878 play->length_us = effect->replay.length * USEC_PER_MSEC;
879 level = effect->u.constant.level;
880 tmp = level * config->vmax_mv;
881 play->vmax_mv = tmp / 0x7fff;
882 dev_dbg(chip->dev, "upload constant effect, length = %dus, vmax_mv=%d\n",
883 play->length_us, play->vmax_mv);
884
885 rc = qti_haptics_load_constant_waveform(chip);
886 if (rc < 0) {
887 dev_err(chip->dev, "Play constant waveform failed, rc=%d\n",
888 rc);
Fenglin Wu802427a2018-08-31 16:07:59 +0800889 return rc;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800890 }
891 break;
892
893 case FF_PERIODIC:
Fenglin Wu802427a2018-08-31 16:07:59 +0800894 if (chip->effects_count == 0)
895 return -EINVAL;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800896
897 if (effect->u.periodic.waveform != FF_CUSTOM) {
898 dev_err(chip->dev, "Only accept custom waveforms\n");
Fenglin Wu802427a2018-08-31 16:07:59 +0800899 return -EINVAL;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800900 }
901
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800902 if (copy_from_user(data, effect->u.periodic.custom_data,
Fenglin Wu802427a2018-08-31 16:07:59 +0800903 sizeof(s16) * CUSTOM_DATA_LEN))
904 return -EFAULT;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800905
906 for (i = 0; i < chip->effects_count; i++)
907 if (chip->predefined[i].id ==
908 data[CUSTOM_DATA_EFFECT_IDX])
909 break;
910
911 if (i == chip->effects_count) {
912 dev_err(chip->dev, "predefined effect %d is NOT supported\n",
913 data[0]);
Fenglin Wu802427a2018-08-31 16:07:59 +0800914 return -EINVAL;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800915 }
916
Fenglin Wu659c0042018-07-18 11:02:43 +0800917 level = effect->u.periodic.magnitude;
918 tmp = level * chip->predefined[i].vmax_mv;
919 play->vmax_mv = tmp / 0x7fff;
920
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800921 dev_dbg(chip->dev, "upload effect %d, vmax_mv=%d\n",
922 chip->predefined[i].id, play->vmax_mv);
923 rc = qti_haptics_load_predefined_effect(chip, i);
924 if (rc < 0) {
925 dev_err(chip->dev, "Play predefined effect %d failed, rc=%d\n",
926 chip->predefined[i].id, rc);
Fenglin Wu802427a2018-08-31 16:07:59 +0800927 return rc;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800928 }
929
930 get_play_length(play, &play->length_us);
931 data[CUSTOM_DATA_TIMEOUT_SEC_IDX] =
932 play->length_us / USEC_PER_SEC;
933 data[CUSTOM_DATA_TIMEOUT_MSEC_IDX] =
934 (play->length_us % USEC_PER_SEC) / USEC_PER_MSEC;
935
936 /*
937 * Copy the custom data contains the play length back to
938 * userspace so that the userspace client can wait and
939 * send stop playing command after it's done.
940 */
941 if (copy_to_user(effect->u.periodic.custom_data, data,
Fenglin Wu802427a2018-08-31 16:07:59 +0800942 sizeof(s16) * CUSTOM_DATA_LEN))
943 return -EFAULT;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800944 break;
945
946 default:
947 dev_err(chip->dev, "Unsupported effect type: %d\n",
948 effect->type);
Fenglin Wu802427a2018-08-31 16:07:59 +0800949 return -EINVAL;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800950 }
951
Fenglin Wu802427a2018-08-31 16:07:59 +0800952 if (chip->vdd_supply && !chip->vdd_enabled) {
953 rc = regulator_enable(chip->vdd_supply);
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800954 if (rc < 0) {
Fenglin Wu802427a2018-08-31 16:07:59 +0800955 dev_err(chip->dev, "Enable VDD supply failed, rc=%d\n",
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800956 rc);
957 return rc;
958 }
Fenglin Wu802427a2018-08-31 16:07:59 +0800959 chip->vdd_enabled = true;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800960 }
Fenglin Wu802427a2018-08-31 16:07:59 +0800961
962 return 0;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800963}
964
965static int qti_haptics_playback(struct input_dev *dev, int effect_id, int val)
966{
967 struct qti_hap_chip *chip = input_get_drvdata(dev);
968 struct qti_hap_play_info *play = &chip->play;
Fenglin Wu30f10b22018-06-15 07:49:23 +0800969 s64 secs;
970 unsigned long nsecs;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800971 int rc = 0;
972
973 dev_dbg(chip->dev, "playback, val = %d\n", val);
974 if (!!val) {
Fenglin Wu802427a2018-08-31 16:07:59 +0800975 rc = qti_haptics_module_en(chip, true);
976 if (rc < 0)
977 return rc;
978
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800979 rc = qti_haptics_play(chip, true);
980 if (rc < 0)
981 return rc;
982
983 if (play->playing_pattern) {
984 if (!chip->play_irq_en) {
985 enable_irq(chip->play_irq);
986 chip->play_irq_en = true;
987 }
Fenglin Wuf3907c82018-07-27 09:06:32 +0800988 /* Toggle PLAY when playing pattern */
989 rc = qti_haptics_play(chip, false);
990 if (rc < 0)
991 return rc;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800992 } else {
993 if (chip->play_irq_en) {
994 disable_irq_nosync(chip->play_irq);
995 chip->play_irq_en = false;
996 }
Fenglin Wu30f10b22018-06-15 07:49:23 +0800997 secs = play->length_us / USEC_PER_SEC;
998 nsecs = (play->length_us % USEC_PER_SEC) *
999 NSEC_PER_USEC;
1000 hrtimer_start(&chip->stop_timer, ktime_set(secs, nsecs),
1001 HRTIMER_MODE_REL);
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001002 }
1003 } else {
1004 play->length_us = 0;
1005 rc = qti_haptics_play(chip, false);
1006 if (rc < 0)
1007 return rc;
1008
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001009 if (chip->play_irq_en) {
1010 disable_irq_nosync(chip->play_irq);
1011 chip->play_irq_en = false;
1012 }
1013 }
1014
1015 return rc;
1016}
1017
1018static int qti_haptics_erase(struct input_dev *dev, int effect_id)
1019{
1020 struct qti_hap_chip *chip = input_get_drvdata(dev);
Fenglin Wu802427a2018-08-31 16:07:59 +08001021 int delay_us, rc = 0;
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001022
1023 if (chip->vdd_supply && chip->vdd_enabled) {
1024 rc = regulator_disable(chip->vdd_supply);
1025 if (rc < 0) {
1026 dev_err(chip->dev, "Disable VDD supply failed, rc=%d\n",
1027 rc);
1028 return rc;
1029 }
1030 chip->vdd_enabled = false;
1031 }
1032
Fenglin Wu802427a2018-08-31 16:07:59 +08001033 rc = qti_haptics_clear_settings(chip);
1034 if (rc < 0) {
1035 dev_err(chip->dev, "clear setting failed, rc=%d\n", rc);
1036 return rc;
1037 }
1038
1039 if (chip->play.effect)
1040 delay_us = chip->play.effect->play_rate_us;
1041 else
1042 delay_us = chip->config.play_rate_us;
1043
1044 delay_us += HAP_DISABLE_DELAY_USEC;
1045 hrtimer_start(&chip->hap_disable_timer,
1046 ktime_set(0, delay_us * NSEC_PER_USEC),
1047 HRTIMER_MODE_REL);
1048
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001049 return rc;
1050}
1051
Fenglin Wud92ef742018-07-16 15:50:08 +08001052static void qti_haptics_set_gain(struct input_dev *dev, u16 gain)
1053{
1054 struct qti_hap_chip *chip = input_get_drvdata(dev);
1055 struct qti_hap_config *config = &chip->config;
1056 struct qti_hap_play_info *play = &chip->play;
1057
1058 if (gain == 0)
1059 return;
1060
1061 if (gain > 0x7fff)
1062 gain = 0x7fff;
1063
1064 play->vmax_mv = ((u32)(gain * config->vmax_mv)) / 0x7fff;
1065 qti_haptics_config_vmax(chip, play->vmax_mv);
1066}
1067
Anirudh Ghayalb195a982020-05-07 15:10:20 +05301068static int qti_haptics_twm_config(struct qti_hap_chip *chip, bool ext_pin)
Umang Chheda599b0962020-01-20 17:15:54 +05301069{
Anirudh Ghayalb195a982020-05-07 15:10:20 +05301070 int rc = 0, i;
Umang Chheda599b0962020-01-20 17:15:54 +05301071
Anirudh Ghayalb195a982020-05-07 15:10:20 +05301072 if (ext_pin) {
1073 for (i = 0; i < ARRAY_SIZE(twm_ext_cfg); i++) {
1074 rc = qti_haptics_write(chip, twm_ext_cfg[i].addr,
1075 &twm_ext_cfg[i].value, 1);
1076 if (rc < 0)
1077 break;
1078 }
1079 } else {
1080 for (i = 0; i < ARRAY_SIZE(twm_cfg); i++) {
1081 rc = qti_haptics_write(chip, twm_cfg[i].addr,
1082 &twm_cfg[i].value, 1);
1083 if (rc < 0)
1084 break;
Umang Chheda599b0962020-01-20 17:15:54 +05301085 }
1086 }
Anirudh Ghayalb195a982020-05-07 15:10:20 +05301087
1088 if (rc < 0)
1089 pr_err("Failed to write twm_config rc=%d\n", rc);
1090 else
1091 pr_debug("Enabled haptics for TWM mode\n");
Umang Chheda599b0962020-01-20 17:15:54 +05301092
1093 return 0;
1094}
1095
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001096static int qti_haptics_hw_init(struct qti_hap_chip *chip)
1097{
1098 struct qti_hap_config *config = &chip->config;
1099 u8 addr, val, mask;
1100 int rc = 0;
1101
1102 /* Config actuator type */
1103 addr = REG_HAP_CFG1;
1104 val = config->act_type;
1105 rc = qti_haptics_write(chip, addr, &val, 1);
1106 if (rc < 0) {
1107 dev_err(chip->dev, "write actuator type failed, rc=%d\n", rc);
1108 return rc;
1109 }
1110
1111 /* Config ilim_ma */
1112 addr = REG_HAP_ILIM_CFG;
1113 val = config->ilim_ma == 400 ? 0 : 1;
1114 rc = qti_haptics_write(chip, addr, &val, 1);
1115 if (rc < 0) {
1116 dev_err(chip->dev, "write ilim_ma failed, rc=%d\n", rc);
1117 return rc;
1118 }
1119
1120 /* Set HAP_EN_CTL3 */
1121 addr = REG_HAP_EN_CTL3;
1122 val = HAP_HBRIDGE_EN_BIT | HAP_PWM_SIGNAL_EN_BIT | HAP_ILIM_EN_BIT |
Fenglin Wucf1a1b92018-06-11 07:39:44 +08001123 HAP_ILIM_CC_EN_BIT | HAP_AUTO_RES_RBIAS_EN_BIT |
1124 HAP_DAC_EN_BIT | HAP_PWM_CTL_EN_BIT;
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001125 rc = qti_haptics_write(chip, addr, &val, 1);
1126 if (rc < 0) {
1127 dev_err(chip->dev, "set EN_CTL3 failed, rc=%d\n", rc);
1128 return rc;
1129 }
1130
1131 /* Set ZX_CFG */
1132 addr = REG_HAP_ZX_CFG;
1133 mask = HAP_ZX_DET_DEB_MASK;
1134 val = ZX_DET_DEB_80US;
1135 rc = qti_haptics_masked_write(chip, addr, mask, val);
1136 if (rc < 0) {
1137 dev_err(chip->dev, "write ZX_CFG failed, rc=%d\n", rc);
1138 return rc;
1139 }
1140
1141 /*
1142 * Config play rate: this is the resonance period for LRA,
1143 * or the play duration of each waveform sample for ERM.
1144 */
1145 rc = qti_haptics_config_play_rate_us(chip, config->play_rate_us);
1146 if (rc < 0)
1147 return rc;
1148
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001149 /* Set external waveform source if it's used */
1150 if (config->use_ext_wf_src) {
1151 rc = qti_haptics_config_wf_src(chip, config->ext_src);
1152 if (rc < 0)
1153 return rc;
1154 }
1155
1156 /*
1157 * Skip configurations below for ERM actuator
1158 * as they're only for LRA actuators
1159 */
1160 if (config->act_type == ACT_ERM)
1161 return 0;
1162
1163 addr = REG_HAP_CFG2;
1164 val = config->lra_shape;
1165 rc = qti_haptics_write(chip, addr, &val, 1);
1166 if (rc < 0) {
1167 dev_err(chip->dev, "write lra_sig_shape failed, rc=%d\n", rc);
1168 return rc;
1169 }
1170
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001171 addr = REG_HAP_AUTO_RES_CFG;
1172 mask = HAP_AUTO_RES_MODE_BIT | HAP_CAL_EOP_EN_BIT | HAP_CAL_PERIOD_MASK;
1173 val = config->lra_auto_res_mode << HAP_AUTO_RES_MODE_SHIFT;
1174 val |= HAP_CAL_EOP_EN_BIT | HAP_CAL_OPT3_EVERY_8_PERIOD;
1175 rc = qti_haptics_masked_write(chip, addr, mask, val);
1176 if (rc < 0) {
1177 dev_err(chip->dev, "set AUTO_RES_CFG failed, rc=%d\n", rc);
1178 return rc;
1179 }
1180
1181 addr = REG_HAP_AUTO_RES_CTRL;
Fenglin Wucf1a1b92018-06-11 07:39:44 +08001182 val = HAP_AUTO_RES_EN_BIT | HAP_SEL_AUTO_RES_PERIOD |
1183 AUTO_RES_CNT_ERR_DELTA(2) | HAP_AUTO_RES_ERR_RECOVERY_BIT |
1184 AUTO_RES_EN_DLY(4);
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001185 rc = qti_haptics_write(chip, addr, &val, 1);
1186 if (rc < 0) {
1187 dev_err(chip->dev, "set AUTO_RES_CTRL failed, rc=%d\n",
1188 rc);
1189 return rc;
1190 }
1191
1192 return 0;
1193}
1194
Fenglin Wu30f10b22018-06-15 07:49:23 +08001195static enum hrtimer_restart qti_hap_stop_timer(struct hrtimer *timer)
1196{
1197 struct qti_hap_chip *chip = container_of(timer, struct qti_hap_chip,
1198 stop_timer);
1199 int rc;
1200
1201 chip->play.length_us = 0;
1202 rc = qti_haptics_play(chip, false);
Fenglin Wu802427a2018-08-31 16:07:59 +08001203 if (rc < 0)
Fenglin Wu30f10b22018-06-15 07:49:23 +08001204 dev_err(chip->dev, "Stop playing failed, rc=%d\n", rc);
Fenglin Wu802427a2018-08-31 16:07:59 +08001205
1206 return HRTIMER_NORESTART;
1207}
1208
1209static enum hrtimer_restart qti_hap_disable_timer(struct hrtimer *timer)
1210{
1211 struct qti_hap_chip *chip = container_of(timer, struct qti_hap_chip,
1212 hap_disable_timer);
1213 int rc;
Fenglin Wu30f10b22018-06-15 07:49:23 +08001214
1215 rc = qti_haptics_module_en(chip, false);
1216 if (rc < 0)
Fenglin Wu802427a2018-08-31 16:07:59 +08001217 dev_err(chip->dev, "Disable haptics module failed, rc=%d\n",
1218 rc);
1219
Fenglin Wu30f10b22018-06-15 07:49:23 +08001220 return HRTIMER_NORESTART;
1221}
1222
Fenglin Wu22e4cf12018-08-01 15:07:28 +08001223static void verify_brake_setting(struct qti_hap_effect *effect)
1224{
1225 int i = effect->brake_pattern_length - 1;
1226 u8 val = 0;
1227
1228 for (; i >= 0; i--) {
1229 if (effect->brake[i] != 0)
1230 break;
1231
1232 effect->brake_pattern_length--;
1233 }
1234
1235 for (i = 0; i < effect->brake_pattern_length; i++) {
1236 effect->brake[i] &= HAP_BRAKE_PATTERN_MASK;
1237 val |= effect->brake[i] << (i * HAP_BRAKE_PATTERN_SHIFT);
1238 }
1239
1240 effect->brake_en = (val != 0);
1241}
1242
Umang Chheda599b0962020-01-20 17:15:54 +05301243static int twm_notifier_cb(struct notifier_block *nb,
1244 unsigned long action, void *data)
1245{
1246 struct qti_hap_chip *chip = container_of(nb,
1247 struct qti_hap_chip, twm_nb);
1248
1249 if (action != PMIC_TWM_CLEAR &&
1250 action != PMIC_TWM_ENABLE)
1251 pr_debug("Unsupported option %lu\n", action);
1252 else
1253 chip->twm_state = (u8)action;
1254
1255 return NOTIFY_OK;
1256}
1257
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001258static int qti_haptics_parse_dt(struct qti_hap_chip *chip)
1259{
1260 struct qti_hap_config *config = &chip->config;
1261 const struct device_node *node = chip->dev->of_node;
1262 struct device_node *child_node;
1263 struct qti_hap_effect *effect;
1264 const char *str;
Fenglin Wuf3907c82018-07-27 09:06:32 +08001265 int rc = 0, tmp, i = 0, j, m;
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001266
1267 rc = of_property_read_u32(node, "reg", &tmp);
1268 if (rc < 0) {
1269 dev_err(chip->dev, "Failed to reg base, rc=%d\n", rc);
1270 return rc;
1271 }
1272 chip->reg_base = (u16)tmp;
1273
1274 chip->sc_irq = platform_get_irq_byname(chip->pdev, "hap-sc-irq");
1275 if (chip->sc_irq < 0) {
1276 dev_err(chip->dev, "Failed to get hap-sc-irq\n");
1277 return chip->sc_irq;
1278 }
1279
1280 chip->play_irq = platform_get_irq_byname(chip->pdev, "hap-play-irq");
1281 if (chip->play_irq < 0) {
1282 dev_err(chip->dev, "Failed to get hap-play-irq\n");
1283 return chip->play_irq;
1284 }
1285
1286 config->act_type = ACT_LRA;
1287 rc = of_property_read_string(node, "qcom,actuator-type", &str);
1288 if (!rc) {
1289 if (strcmp(str, "erm") == 0) {
1290 config->act_type = ACT_ERM;
1291 } else if (strcmp(str, "lra") == 0) {
1292 config->act_type = ACT_LRA;
1293 } else {
1294 dev_err(chip->dev, "Invalid actuator type: %s\n",
1295 str);
1296 return -EINVAL;
1297 }
1298 }
1299
1300 config->vmax_mv = HAP_VMAX_MV_DEFAULT;
1301 rc = of_property_read_u32(node, "qcom,vmax-mv", &tmp);
1302 if (!rc)
1303 config->vmax_mv = (tmp > HAP_VMAX_MV_MAX) ?
1304 HAP_VMAX_MV_MAX : tmp;
1305
1306 config->ilim_ma = HAP_ILIM_MA_DEFAULT;
1307 rc = of_property_read_u32(node, "qcom,ilim-ma", &tmp);
1308 if (!rc)
1309 config->ilim_ma = (tmp >= HAP_ILIM_MA_MAX) ?
1310 HAP_ILIM_MA_MAX : HAP_ILIM_MA_DEFAULT;
1311
1312 config->play_rate_us = HAP_PLAY_RATE_US_DEFAULT;
1313 rc = of_property_read_u32(node, "qcom,play-rate-us", &tmp);
1314 if (!rc)
1315 config->play_rate_us = (tmp >= HAP_PLAY_RATE_US_MAX) ?
1316 HAP_PLAY_RATE_US_MAX : tmp;
1317
Umang Chheda599b0962020-01-20 17:15:54 +05301318 chip->haptics_ext_pin_twm = of_property_read_bool(node,
1319 "qcom,haptics-ext-pin-twm");
1320
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001321 if (of_find_property(node, "qcom,external-waveform-source", NULL)) {
1322 if (!of_property_read_string(node,
1323 "qcom,external-waveform-source", &str)) {
1324 if (strcmp(str, "audio") == 0) {
1325 config->ext_src = EXT_WF_AUDIO;
1326 } else if (strcmp(str, "pwm") == 0) {
1327 config->ext_src = EXT_WF_PWM;
1328 } else {
1329 dev_err(chip->dev, "Invalid external waveform source: %s\n",
1330 str);
1331 return -EINVAL;
1332 }
1333 }
1334 config->use_ext_wf_src = true;
1335 }
1336
1337 if (of_find_property(node, "vdd-supply", NULL)) {
1338 chip->vdd_supply = devm_regulator_get(chip->dev, "vdd");
1339 if (IS_ERR(chip->vdd_supply)) {
1340 rc = PTR_ERR(chip->vdd_supply);
1341 if (rc != -EPROBE_DEFER)
1342 dev_err(chip->dev, "Failed to get vdd regulator");
1343 return rc;
1344 }
1345 }
1346
1347 if (config->act_type == ACT_LRA) {
1348 config->lra_shape = RES_SIG_SINE;
1349 rc = of_property_read_string(node,
1350 "qcom,lra-resonance-sig-shape", &str);
1351 if (!rc) {
1352 if (strcmp(str, "sine") == 0) {
1353 config->lra_shape = RES_SIG_SINE;
1354 } else if (strcmp(str, "square") == 0) {
1355 config->lra_shape = RES_SIG_SQUARE;
1356 } else {
1357 dev_err(chip->dev, "Invalid resonance signal shape: %s\n",
1358 str);
1359 return -EINVAL;
1360 }
1361 }
1362
Fenglin Wucf1a1b92018-06-11 07:39:44 +08001363 config->lra_allow_variable_play_rate = of_property_read_bool(
1364 node, "qcom,lra-allow-variable-play-rate");
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001365
1366 config->lra_auto_res_mode = AUTO_RES_MODE_ZXD;
1367 rc = of_property_read_string(node,
1368 "qcom,lra-auto-resonance-mode", &str);
1369 if (!rc) {
1370 if (strcmp(str, "zxd") == 0) {
1371 config->lra_auto_res_mode = AUTO_RES_MODE_ZXD;
1372 } else if (strcmp(str, "qwd") == 0) {
1373 config->lra_auto_res_mode = AUTO_RES_MODE_QWD;
1374 } else {
1375 dev_err(chip->dev, "Invalid auto resonance mode: %s\n",
1376 str);
1377 return -EINVAL;
1378 }
1379 }
1380 }
1381
1382 chip->constant.pattern = devm_kcalloc(chip->dev,
1383 HAP_WAVEFORM_BUFFER_MAX,
1384 sizeof(u8), GFP_KERNEL);
1385 if (!chip->constant.pattern)
1386 return -ENOMEM;
1387
1388 tmp = of_get_available_child_count(node);
1389 if (tmp == 0)
1390 return 0;
1391
1392 chip->predefined = devm_kcalloc(chip->dev, tmp,
1393 sizeof(*chip->predefined), GFP_KERNEL);
1394 if (!chip->predefined)
1395 return -ENOMEM;
1396
1397 chip->effects_count = tmp;
1398
1399 for_each_available_child_of_node(node, child_node) {
1400 effect = &chip->predefined[i++];
1401 rc = of_property_read_u32(child_node, "qcom,effect-id",
1402 &effect->id);
1403 if (rc < 0) {
1404 dev_err(chip->dev, "Read qcom,effect-id failed, rc=%d\n",
1405 rc);
1406 return rc;
1407 }
1408
Fenglin Wu659c0042018-07-18 11:02:43 +08001409 effect->vmax_mv = config->vmax_mv;
1410 rc = of_property_read_u32(child_node, "qcom,wf-vmax-mv", &tmp);
1411 if (rc < 0)
1412 dev_dbg(chip->dev, "Read qcom,wf-vmax-mv failed, rc=%d\n",
1413 rc);
1414 else
1415 effect->vmax_mv = (tmp > HAP_VMAX_MV_MAX) ?
1416 HAP_VMAX_MV_MAX : tmp;
1417
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001418 rc = of_property_count_elems_of_size(child_node,
1419 "qcom,wf-pattern", sizeof(u8));
1420 if (rc < 0) {
1421 dev_err(chip->dev, "Count qcom,wf-pattern property failed, rc=%d\n",
1422 rc);
1423 return rc;
1424 } else if (rc == 0) {
1425 dev_dbg(chip->dev, "qcom,wf-pattern has no data\n");
1426 return -EINVAL;
1427 }
1428
1429 effect->pattern_length = rc;
1430 effect->pattern = devm_kcalloc(chip->dev,
1431 effect->pattern_length, sizeof(u8), GFP_KERNEL);
1432 if (!effect->pattern)
1433 return -ENOMEM;
1434
1435 rc = of_property_read_u8_array(child_node, "qcom,wf-pattern",
1436 effect->pattern, effect->pattern_length);
1437 if (rc < 0) {
1438 dev_err(chip->dev, "Read qcom,wf-pattern property failed, rc=%d\n",
1439 rc);
1440 return rc;
1441 }
1442
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001443 effect->play_rate_us = config->play_rate_us;
1444 rc = of_property_read_u32(child_node, "qcom,wf-play-rate-us",
1445 &tmp);
1446 if (rc < 0)
1447 dev_dbg(chip->dev, "Read qcom,wf-play-rate-us failed, rc=%d\n",
1448 rc);
1449 else
1450 effect->play_rate_us = tmp;
1451
1452 if (config->act_type == ACT_LRA &&
Fenglin Wucf1a1b92018-06-11 07:39:44 +08001453 !config->lra_allow_variable_play_rate &&
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001454 config->play_rate_us != effect->play_rate_us) {
1455 dev_warn(chip->dev, "play rate should match with LRA resonance frequency\n");
1456 effect->play_rate_us = config->play_rate_us;
1457 }
1458
1459 rc = of_property_read_u32(child_node, "qcom,wf-repeat-count",
1460 &tmp);
1461 if (rc < 0) {
1462 dev_dbg(chip->dev, "Read qcom,wf-repeat-count failed, rc=%d\n",
1463 rc);
1464 } else {
1465 for (j = 0; j < ARRAY_SIZE(wf_repeat); j++)
1466 if (tmp <= wf_repeat[j])
1467 break;
1468
1469 effect->wf_repeat_n = j;
1470 }
1471
1472 rc = of_property_read_u32(child_node, "qcom,wf-s-repeat-count",
1473 &tmp);
1474 if (rc < 0) {
1475 dev_dbg(chip->dev, "Read qcom,wf-s-repeat-count failed, rc=%d\n",
1476 rc);
1477 } else {
1478 for (j = 0; j < ARRAY_SIZE(wf_s_repeat); j++)
1479 if (tmp <= wf_s_repeat[j])
1480 break;
1481
1482 effect->wf_s_repeat_n = j;
1483 }
Fenglin Wucf1a1b92018-06-11 07:39:44 +08001484
Fenglin Wuf3907c82018-07-27 09:06:32 +08001485 effect->lra_auto_res_disable = of_property_read_bool(child_node,
Fenglin Wucf1a1b92018-06-11 07:39:44 +08001486 "qcom,lra-auto-resonance-disable");
1487
1488 tmp = of_property_count_elems_of_size(child_node,
1489 "qcom,wf-brake-pattern", sizeof(u8));
1490 if (tmp <= 0)
1491 continue;
1492
1493 if (tmp > HAP_BRAKE_PATTERN_MAX) {
1494 dev_err(chip->dev, "wf-brake-pattern shouldn't be more than %d bytes\n",
1495 HAP_BRAKE_PATTERN_MAX);
1496 return -EINVAL;
1497 }
1498
1499 rc = of_property_read_u8_array(child_node,
1500 "qcom,wf-brake-pattern", effect->brake, tmp);
1501 if (rc < 0) {
1502 dev_err(chip->dev, "Failed to get wf-brake-pattern, rc=%d\n",
1503 rc);
1504 return rc;
1505 }
1506
1507 effect->brake_pattern_length = tmp;
Fenglin Wu22e4cf12018-08-01 15:07:28 +08001508 verify_brake_setting(effect);
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001509 }
1510
Fenglin Wuf3907c82018-07-27 09:06:32 +08001511 for (j = 0; j < i; j++) {
1512 dev_dbg(chip->dev, "effect: %d\n", chip->predefined[j].id);
1513 dev_dbg(chip->dev, " vmax: %d mv\n",
1514 chip->predefined[j].vmax_mv);
1515 dev_dbg(chip->dev, " play_rate: %d us\n",
1516 chip->predefined[j].play_rate_us);
1517 for (m = 0; m < chip->predefined[j].pattern_length; m++)
1518 dev_dbg(chip->dev, " pattern[%d]: 0x%x\n",
1519 m, chip->predefined[j].pattern[m]);
1520 for (m = 0; m < chip->predefined[j].brake_pattern_length; m++)
1521 dev_dbg(chip->dev, " brake_pattern[%d]: 0x%x\n",
1522 m, chip->predefined[j].brake[m]);
1523 dev_dbg(chip->dev, " brake_en: %d\n",
1524 chip->predefined[j].brake_en);
1525 dev_dbg(chip->dev, " wf_repeat_n: %d\n",
1526 chip->predefined[j].wf_repeat_n);
1527 dev_dbg(chip->dev, " wf_s_repeat_n: %d\n",
1528 chip->predefined[j].wf_s_repeat_n);
1529 dev_dbg(chip->dev, " lra_auto_res_disable: %d\n",
1530 chip->predefined[j].lra_auto_res_disable);
1531 }
1532
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001533 return 0;
1534}
1535
Fenglin Wu22e4cf12018-08-01 15:07:28 +08001536#ifdef CONFIG_DEBUG_FS
1537static int play_rate_dbgfs_read(void *data, u64 *val)
1538{
1539 struct qti_hap_effect *effect = (struct qti_hap_effect *)data;
1540
1541 *val = effect->play_rate_us;
1542
1543 return 0;
1544}
1545
1546static int play_rate_dbgfs_write(void *data, u64 val)
1547{
1548 struct qti_hap_effect *effect = (struct qti_hap_effect *)data;
1549
1550 if (val > HAP_PLAY_RATE_US_MAX)
1551 val = HAP_PLAY_RATE_US_MAX;
1552
1553 effect->play_rate_us = val;
1554
1555 return 0;
1556}
1557
1558static int vmax_dbgfs_read(void *data, u64 *val)
1559{
1560 struct qti_hap_effect *effect = (struct qti_hap_effect *)data;
1561
1562 *val = effect->vmax_mv;
1563
1564 return 0;
1565}
1566
1567static int vmax_dbgfs_write(void *data, u64 val)
1568{
1569 struct qti_hap_effect *effect = (struct qti_hap_effect *)data;
1570
1571 if (val > HAP_VMAX_MV_MAX)
1572 val = HAP_VMAX_MV_MAX;
1573
1574 effect->vmax_mv = val;
1575
1576 return 0;
1577}
1578
1579static int wf_repeat_n_dbgfs_read(void *data, u64 *val)
1580{
1581 struct qti_hap_effect *effect = (struct qti_hap_effect *)data;
1582
1583 *val = wf_repeat[effect->wf_repeat_n];
1584
1585 return 0;
1586}
1587
1588static int wf_repeat_n_dbgfs_write(void *data, u64 val)
1589{
1590 struct qti_hap_effect *effect = (struct qti_hap_effect *)data;
1591 int i;
1592
1593 for (i = 0; i < ARRAY_SIZE(wf_repeat); i++)
1594 if (val == wf_repeat[i])
1595 break;
1596
1597 if (i == ARRAY_SIZE(wf_repeat))
1598 pr_err("wf_repeat value %llu is invalid\n", val);
1599 else
1600 effect->wf_repeat_n = i;
1601
1602 return 0;
1603}
1604
1605static int wf_s_repeat_n_dbgfs_read(void *data, u64 *val)
1606{
1607 struct qti_hap_effect *effect = (struct qti_hap_effect *)data;
1608
1609 *val = wf_s_repeat[effect->wf_s_repeat_n];
1610
1611 return 0;
1612}
1613
1614static int wf_s_repeat_n_dbgfs_write(void *data, u64 val)
1615{
1616 struct qti_hap_effect *effect = (struct qti_hap_effect *)data;
1617 int i;
1618
1619 for (i = 0; i < ARRAY_SIZE(wf_s_repeat); i++)
1620 if (val == wf_s_repeat[i])
1621 break;
1622
1623 if (i == ARRAY_SIZE(wf_s_repeat))
1624 pr_err("wf_s_repeat value %llu is invalid\n", val);
1625 else
1626 effect->wf_s_repeat_n = i;
1627
1628 return 0;
1629}
1630
1631
1632static int auto_res_dbgfs_read(void *data, u64 *val)
1633{
1634 struct qti_hap_effect *effect = (struct qti_hap_effect *)data;
1635
1636 *val = !effect->lra_auto_res_disable;
1637
1638 return 0;
1639}
1640
1641static int auto_res_dbgfs_write(void *data, u64 val)
1642{
1643 struct qti_hap_effect *effect = (struct qti_hap_effect *)data;
1644
1645 effect->lra_auto_res_disable = !val;
1646
1647 return 0;
1648}
1649
1650DEFINE_SIMPLE_ATTRIBUTE(play_rate_debugfs_ops, play_rate_dbgfs_read,
1651 play_rate_dbgfs_write, "%llu\n");
1652DEFINE_SIMPLE_ATTRIBUTE(vmax_debugfs_ops, vmax_dbgfs_read,
1653 vmax_dbgfs_write, "%llu\n");
1654DEFINE_SIMPLE_ATTRIBUTE(wf_repeat_n_debugfs_ops, wf_repeat_n_dbgfs_read,
1655 wf_repeat_n_dbgfs_write, "%llu\n");
1656DEFINE_SIMPLE_ATTRIBUTE(wf_s_repeat_n_debugfs_ops, wf_s_repeat_n_dbgfs_read,
1657 wf_s_repeat_n_dbgfs_write, "%llu\n");
1658DEFINE_SIMPLE_ATTRIBUTE(auto_res_debugfs_ops, auto_res_dbgfs_read,
1659 auto_res_dbgfs_write, "%llu\n");
1660
1661#define CHAR_PER_PATTERN 8
1662static ssize_t brake_pattern_dbgfs_read(struct file *filep,
1663 char __user *buf, size_t count, loff_t *ppos)
1664{
1665 struct qti_hap_effect *effect =
1666 (struct qti_hap_effect *)filep->private_data;
1667 char *kbuf, *tmp;
1668 int rc, length, i, len;
1669
1670 kbuf = kcalloc(CHAR_PER_PATTERN, HAP_BRAKE_PATTERN_MAX, GFP_KERNEL);
1671 if (!kbuf)
1672 return -ENOMEM;
1673
1674 tmp = kbuf;
1675 for (length = 0, i = 0; i < HAP_BRAKE_PATTERN_MAX; i++) {
1676 len = snprintf(tmp, CHAR_PER_PATTERN, "0x%x ",
1677 effect->brake[i]);
1678 tmp += len;
1679 length += len;
1680 }
1681
1682 kbuf[length++] = '\n';
1683 kbuf[length++] = '\0';
1684
1685 rc = simple_read_from_buffer(buf, count, ppos, kbuf, length);
1686
1687 kfree(kbuf);
1688 return rc;
1689}
1690
1691static ssize_t brake_pattern_dbgfs_write(struct file *filep,
1692 const char __user *buf, size_t count, loff_t *ppos)
1693{
1694 struct qti_hap_effect *effect =
1695 (struct qti_hap_effect *)filep->private_data;
1696 char *kbuf, *token;
1697 int rc = 0, i = 0, j;
1698 u32 val;
1699
1700 kbuf = kmalloc(count + 1, GFP_KERNEL);
1701 if (!kbuf)
1702 return -ENOMEM;
1703
1704 rc = copy_from_user(kbuf, buf, count);
1705 if (rc > 0) {
1706 rc = -EFAULT;
1707 goto err;
1708 }
1709
1710 kbuf[count] = '\0';
1711 *ppos += count;
1712
1713 while ((token = strsep(&kbuf, " ")) != NULL) {
1714 rc = kstrtouint(token, 0, &val);
1715 if (rc < 0) {
1716 rc = -EINVAL;
1717 goto err;
1718 }
1719
1720 effect->brake[i++] = val & HAP_BRAKE_PATTERN_MASK;
1721
1722 if (i >= HAP_BRAKE_PATTERN_MAX)
1723 break;
1724 }
1725
1726 for (j = i; j < HAP_BRAKE_PATTERN_MAX; j++)
1727 effect->brake[j] = 0;
1728
1729 effect->brake_pattern_length = i;
1730 verify_brake_setting(effect);
1731
1732 rc = count;
1733err:
1734 kfree(kbuf);
1735 return rc;
1736}
1737
1738static const struct file_operations brake_pattern_dbgfs_ops = {
1739 .read = brake_pattern_dbgfs_read,
1740 .write = brake_pattern_dbgfs_write,
1741 .owner = THIS_MODULE,
1742 .open = simple_open,
1743};
1744
1745static ssize_t pattern_dbgfs_read(struct file *filep,
1746 char __user *buf, size_t count, loff_t *ppos)
1747{
1748 struct qti_hap_effect *effect =
1749 (struct qti_hap_effect *)filep->private_data;
1750 char *kbuf, *tmp;
1751 int rc, length, i, len;
1752
1753 kbuf = kcalloc(CHAR_PER_PATTERN, effect->pattern_length, GFP_KERNEL);
1754 if (!kbuf)
1755 return -ENOMEM;
1756
1757 tmp = kbuf;
1758 for (length = 0, i = 0; i < effect->pattern_length; i++) {
1759 len = snprintf(tmp, CHAR_PER_PATTERN, "0x%x ",
1760 effect->pattern[i]);
1761 tmp += len;
1762 length += len;
1763 }
1764
1765 kbuf[length++] = '\n';
1766 kbuf[length++] = '\0';
1767
1768 rc = simple_read_from_buffer(buf, count, ppos, kbuf, length);
1769
1770 kfree(kbuf);
1771 return rc;
1772}
1773
1774static ssize_t pattern_dbgfs_write(struct file *filep,
1775 const char __user *buf, size_t count, loff_t *ppos)
1776{
1777 struct qti_hap_effect *effect =
1778 (struct qti_hap_effect *)filep->private_data;
1779 char *kbuf, *token;
1780 int rc = 0, i = 0, j;
1781 u32 val;
1782
1783 kbuf = kmalloc(count + 1, GFP_KERNEL);
1784 if (!kbuf)
1785 return -ENOMEM;
1786
1787 rc = copy_from_user(kbuf, buf, count);
1788 if (rc > 0) {
1789 rc = -EFAULT;
1790 goto err;
1791 }
1792
1793 kbuf[count] = '\0';
1794 *ppos += count;
1795
1796 while ((token = strsep(&kbuf, " ")) != NULL) {
1797 rc = kstrtouint(token, 0, &val);
1798 if (rc < 0) {
1799 rc = -EINVAL;
1800 goto err;
1801 }
1802
1803 effect->pattern[i++] = val & 0xff;
1804
1805 if (i >= effect->pattern_length)
1806 break;
1807 }
1808
1809 for (j = i; j < effect->pattern_length; j++)
1810 effect->pattern[j] = 0;
1811
1812 rc = count;
1813err:
1814 kfree(kbuf);
1815 return rc;
1816}
1817
1818static const struct file_operations pattern_dbgfs_ops = {
1819 .read = pattern_dbgfs_read,
1820 .write = pattern_dbgfs_write,
1821 .owner = THIS_MODULE,
1822 .open = simple_open,
1823};
1824
1825static int create_effect_debug_files(struct qti_hap_effect *effect,
1826 struct dentry *dir)
1827{
1828 struct dentry *file;
1829
1830 file = debugfs_create_file("play_rate_us", 0644, dir,
1831 effect, &play_rate_debugfs_ops);
1832 if (!file) {
1833 pr_err("create play-rate debugfs node failed\n");
1834 return -ENOMEM;
1835 }
1836
1837 file = debugfs_create_file("vmax_mv", 0644, dir,
1838 effect, &vmax_debugfs_ops);
1839 if (!file) {
1840 pr_err("create vmax debugfs node failed\n");
1841 return -ENOMEM;
1842 }
1843
1844 file = debugfs_create_file("wf_repeat_n", 0644, dir,
1845 effect, &wf_repeat_n_debugfs_ops);
1846 if (!file) {
1847 pr_err("create wf-repeat debugfs node failed\n");
1848 return -ENOMEM;
1849 }
1850
1851 file = debugfs_create_file("wf_s_repeat_n", 0644, dir,
1852 effect, &wf_s_repeat_n_debugfs_ops);
1853 if (!file) {
1854 pr_err("create wf-s-repeat debugfs node failed\n");
1855 return -ENOMEM;
1856 }
1857
1858 file = debugfs_create_file("lra_auto_res_en", 0644, dir,
1859 effect, &auto_res_debugfs_ops);
1860 if (!file) {
1861 pr_err("create lra-auto-res-en debugfs node failed\n");
1862 return -ENOMEM;
1863 }
1864
1865 file = debugfs_create_file("brake", 0644, dir,
1866 effect, &brake_pattern_dbgfs_ops);
1867 if (!file) {
1868 pr_err("create brake debugfs node failed\n");
1869 return -ENOMEM;
1870 }
1871
1872 file = debugfs_create_file("pattern", 0644, dir,
1873 effect, &pattern_dbgfs_ops);
1874 if (!file) {
1875 pr_err("create pattern debugfs node failed\n");
1876 return -ENOMEM;
1877 }
1878
1879 return 0;
1880}
1881
1882static int qti_haptics_add_debugfs(struct qti_hap_chip *chip)
1883{
1884 struct dentry *hap_dir, *effect_dir;
1885 char str[12] = {0};
1886 int i, rc = 0;
1887
1888 hap_dir = debugfs_create_dir("haptics", NULL);
1889 if (!hap_dir) {
1890 pr_err("create haptics debugfs directory failed\n");
1891 return -ENOMEM;
1892 }
1893
1894 for (i = 0; i < chip->effects_count; i++) {
1895 snprintf(str, ARRAY_SIZE(str), "effect%d", i);
1896 effect_dir = debugfs_create_dir(str, hap_dir);
1897 if (!effect_dir) {
1898 pr_err("create %s debugfs directory failed\n", str);
1899 rc = -ENOMEM;
1900 goto cleanup;
1901 }
1902
1903 rc = create_effect_debug_files(&chip->predefined[i],
1904 effect_dir);
1905 if (rc < 0) {
1906 rc = -ENOMEM;
1907 goto cleanup;
1908 }
1909 }
1910
1911 chip->hap_debugfs = hap_dir;
1912 return 0;
1913
1914cleanup:
1915 debugfs_remove_recursive(hap_dir);
1916 return rc;
1917}
1918#endif
1919
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001920static int qti_haptics_probe(struct platform_device *pdev)
1921{
1922 struct qti_hap_chip *chip;
1923 struct input_dev *input_dev;
1924 struct ff_device *ff;
1925 int rc = 0, effect_count_max;
1926
1927 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1928 if (!chip)
1929 return -ENOMEM;
1930
1931 input_dev = devm_input_allocate_device(&pdev->dev);
1932 if (!input_dev)
1933 return -ENOMEM;
1934
1935 chip->pdev = pdev;
1936 chip->dev = &pdev->dev;
1937 chip->regmap = dev_get_regmap(chip->dev->parent, NULL);
1938 if (!chip->regmap) {
1939 dev_err(chip->dev, "Failed to get regmap handle\n");
1940 return -ENXIO;
1941 }
1942
1943 rc = qti_haptics_parse_dt(chip);
1944 if (rc < 0) {
1945 dev_err(chip->dev, "parse device-tree failed, rc=%d\n", rc);
1946 return rc;
1947 }
1948
1949 spin_lock_init(&chip->bus_lock);
1950
1951 rc = qti_haptics_hw_init(chip);
1952 if (rc < 0) {
1953 dev_err(chip->dev, "parse device-tree failed, rc=%d\n", rc);
1954 return rc;
1955 }
1956
1957 rc = devm_request_threaded_irq(chip->dev, chip->play_irq, NULL,
1958 qti_haptics_play_irq_handler,
1959 IRQF_ONESHOT, "hap_play_irq", chip);
1960 if (rc < 0) {
1961 dev_err(chip->dev, "request play-irq failed, rc=%d\n", rc);
1962 return rc;
1963 }
1964
1965 disable_irq(chip->play_irq);
1966 chip->play_irq_en = false;
1967
1968 rc = devm_request_threaded_irq(chip->dev, chip->sc_irq, NULL,
1969 qti_haptics_sc_irq_handler,
1970 IRQF_ONESHOT, "hap_sc_irq", chip);
1971 if (rc < 0) {
1972 dev_err(chip->dev, "request sc-irq failed, rc=%d\n", rc);
1973 return rc;
1974 }
1975
Umang Chheda599b0962020-01-20 17:15:54 +05301976 chip->twm_nb.notifier_call = twm_notifier_cb;
1977 rc = qpnp_misc_twm_notifier_register(&chip->twm_nb);
1978 if (rc < 0)
1979 pr_err("Failed to register twm_notifier_cb rc=%d\n", rc);
1980
Fenglin Wu30f10b22018-06-15 07:49:23 +08001981 hrtimer_init(&chip->stop_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1982 chip->stop_timer.function = qti_hap_stop_timer;
Fenglin Wu802427a2018-08-31 16:07:59 +08001983 hrtimer_init(&chip->hap_disable_timer, CLOCK_MONOTONIC,
1984 HRTIMER_MODE_REL);
1985 chip->hap_disable_timer.function = qti_hap_disable_timer;
Fenglin Wu37aa3492018-07-10 10:58:49 +08001986 input_dev->name = "qti-haptics";
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001987 input_set_drvdata(input_dev, chip);
1988 chip->input_dev = input_dev;
1989
1990 input_set_capability(input_dev, EV_FF, FF_CONSTANT);
Fenglin Wud92ef742018-07-16 15:50:08 +08001991 input_set_capability(input_dev, EV_FF, FF_GAIN);
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001992 if (chip->effects_count != 0) {
1993 input_set_capability(input_dev, EV_FF, FF_PERIODIC);
1994 input_set_capability(input_dev, EV_FF, FF_CUSTOM);
1995 }
1996
1997 if (chip->effects_count + 1 > FF_EFFECT_COUNT_MAX)
1998 effect_count_max = chip->effects_count + 1;
1999 else
2000 effect_count_max = FF_EFFECT_COUNT_MAX;
2001 rc = input_ff_create(input_dev, effect_count_max);
2002 if (rc < 0) {
2003 dev_err(chip->dev, "create FF input device failed, rc=%d\n",
2004 rc);
2005 return rc;
2006 }
2007
2008 ff = input_dev->ff;
2009 ff->upload = qti_haptics_upload_effect;
2010 ff->playback = qti_haptics_playback;
2011 ff->erase = qti_haptics_erase;
Fenglin Wud92ef742018-07-16 15:50:08 +08002012 ff->set_gain = qti_haptics_set_gain;
Fenglin Wu3840f8e2018-04-27 13:48:43 +08002013
2014 rc = input_register_device(input_dev);
2015 if (rc < 0) {
2016 dev_err(chip->dev, "register input device failed, rc=%d\n",
2017 rc);
2018 goto destroy_ff;
2019 }
2020
2021 dev_set_drvdata(chip->dev, chip);
Fenglin Wu22e4cf12018-08-01 15:07:28 +08002022#ifdef CONFIG_DEBUG_FS
2023 rc = qti_haptics_add_debugfs(chip);
2024 if (rc < 0)
2025 dev_dbg(chip->dev, "create debugfs failed, rc=%d\n", rc);
2026#endif
Fenglin Wu3840f8e2018-04-27 13:48:43 +08002027 return 0;
2028
2029destroy_ff:
2030 input_ff_destroy(chip->input_dev);
Umang Chheda599b0962020-01-20 17:15:54 +05302031 qpnp_misc_twm_notifier_unregister(&chip->twm_nb);
Fenglin Wu3840f8e2018-04-27 13:48:43 +08002032 return rc;
2033}
2034
2035static int qti_haptics_remove(struct platform_device *pdev)
2036{
2037 struct qti_hap_chip *chip = dev_get_drvdata(&pdev->dev);
2038
Fenglin Wu22e4cf12018-08-01 15:07:28 +08002039#ifdef CONFIG_DEBUG_FS
2040 debugfs_remove_recursive(chip->hap_debugfs);
2041#endif
Fenglin Wu3840f8e2018-04-27 13:48:43 +08002042 input_ff_destroy(chip->input_dev);
Umang Chheda599b0962020-01-20 17:15:54 +05302043 qpnp_misc_twm_notifier_unregister(&chip->twm_nb);
Fenglin Wu3840f8e2018-04-27 13:48:43 +08002044 dev_set_drvdata(chip->dev, NULL);
2045
2046 return 0;
2047}
2048
Fenglin Wu802427a2018-08-31 16:07:59 +08002049static void qti_haptics_shutdown(struct platform_device *pdev)
2050{
2051 struct qti_hap_chip *chip = dev_get_drvdata(&pdev->dev);
2052 int rc;
2053
2054 dev_dbg(chip->dev, "Shutdown!\n");
2055
2056 qti_haptics_module_en(chip, false);
2057
2058 if (chip->vdd_supply && chip->vdd_enabled) {
2059 rc = regulator_disable(chip->vdd_supply);
2060 if (rc < 0) {
2061 dev_err(chip->dev, "Disable VDD supply failed, rc=%d\n",
2062 rc);
2063 return;
2064 }
2065 chip->vdd_enabled = false;
2066 }
Umang Chheda599b0962020-01-20 17:15:54 +05302067
Anirudh Ghayalb195a982020-05-07 15:10:20 +05302068 if (chip->twm_state == PMIC_TWM_ENABLE && twm_sys_enable) {
2069 rc = qti_haptics_twm_config(chip, chip->haptics_ext_pin_twm);
Umang Chheda599b0962020-01-20 17:15:54 +05302070 if (rc < 0)
2071 pr_err("Haptics TWM config failed rc=%d\n", rc);
2072 }
Fenglin Wu802427a2018-08-31 16:07:59 +08002073}
2074
Fenglin Wu3840f8e2018-04-27 13:48:43 +08002075static const struct of_device_id haptics_match_table[] = {
2076 { .compatible = "qcom,haptics" },
2077 { .compatible = "qcom,pm660-haptics" },
2078 { .compatible = "qcom,pm8150b-haptics" },
2079 {},
2080};
2081
2082static struct platform_driver qti_haptics_driver = {
2083 .driver = {
2084 .name = "qcom,haptics",
Fenglin Wu802427a2018-08-31 16:07:59 +08002085 .owner = THIS_MODULE,
Fenglin Wu3840f8e2018-04-27 13:48:43 +08002086 .of_match_table = haptics_match_table,
2087 },
2088 .probe = qti_haptics_probe,
2089 .remove = qti_haptics_remove,
Fenglin Wu802427a2018-08-31 16:07:59 +08002090 .shutdown = qti_haptics_shutdown,
Fenglin Wu3840f8e2018-04-27 13:48:43 +08002091};
2092module_platform_driver(qti_haptics_driver);
2093
2094MODULE_DESCRIPTION("QTI haptics driver");
2095MODULE_LICENSE("GPL v2");