Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 1 | /* |
Subhash Jadavani | cce6fbc | 2016-08-11 11:35:26 -0700 | [diff] [blame] | 2 | * Copyright (c) 2013-2016, Linux Foundation. All rights reserved. |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | */ |
| 14 | |
| 15 | #include "phy-qcom-ufs-i.h" |
| 16 | |
| 17 | #define MAX_PROP_NAME 32 |
Subhash Jadavani | 9c80770 | 2017-04-01 00:35:51 -0700 | [diff] [blame] | 18 | #define VDDA_PHY_MIN_UV 800000 |
| 19 | #define VDDA_PHY_MAX_UV 925000 |
Subhash Jadavani | cce6fbc | 2016-08-11 11:35:26 -0700 | [diff] [blame] | 20 | #define VDDA_PLL_MIN_UV 1200000 |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 21 | #define VDDA_PLL_MAX_UV 1800000 |
| 22 | #define VDDP_REF_CLK_MIN_UV 1200000 |
| 23 | #define VDDP_REF_CLK_MAX_UV 1200000 |
| 24 | |
Subhash Jadavani | 8bfeb63 | 2017-04-03 17:14:30 -0700 | [diff] [blame] | 25 | #define UFS_PHY_DEFAULT_LANES_PER_DIRECTION 1 |
| 26 | |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 27 | static int __ufs_qcom_phy_init_vreg(struct phy *, struct ufs_qcom_phy_vreg *, |
| 28 | const char *, bool); |
| 29 | static int ufs_qcom_phy_init_vreg(struct phy *, struct ufs_qcom_phy_vreg *, |
| 30 | const char *); |
| 31 | static int ufs_qcom_phy_base_init(struct platform_device *pdev, |
| 32 | struct ufs_qcom_phy *phy_common); |
| 33 | |
Subhash Jadavani | cce6fbc | 2016-08-11 11:35:26 -0700 | [diff] [blame] | 34 | void ufs_qcom_phy_write_tbl(struct ufs_qcom_phy *ufs_qcom_phy, |
| 35 | struct ufs_qcom_phy_calibration *tbl, |
| 36 | int tbl_size) |
| 37 | { |
| 38 | int i; |
| 39 | |
| 40 | for (i = 0; i < tbl_size; i++) |
| 41 | writel_relaxed(tbl[i].cfg_value, |
| 42 | ufs_qcom_phy->mmio + tbl[i].reg_offset); |
| 43 | } |
| 44 | EXPORT_SYMBOL(ufs_qcom_phy_write_tbl); |
| 45 | |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 46 | int ufs_qcom_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy, |
| 47 | struct ufs_qcom_phy_calibration *tbl_A, |
| 48 | int tbl_size_A, |
| 49 | struct ufs_qcom_phy_calibration *tbl_B, |
| 50 | int tbl_size_B, bool is_rate_B) |
| 51 | { |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 52 | int ret = 0; |
| 53 | |
| 54 | if (!tbl_A) { |
| 55 | dev_err(ufs_qcom_phy->dev, "%s: tbl_A is NULL", __func__); |
| 56 | ret = EINVAL; |
| 57 | goto out; |
| 58 | } |
| 59 | |
Subhash Jadavani | cce6fbc | 2016-08-11 11:35:26 -0700 | [diff] [blame] | 60 | ufs_qcom_phy_write_tbl(ufs_qcom_phy, tbl_A, tbl_size_A); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 61 | |
| 62 | /* |
| 63 | * In case we would like to work in rate B, we need |
| 64 | * to override a registers that were configured in rate A table |
| 65 | * with registers of rate B table. |
| 66 | * table. |
| 67 | */ |
| 68 | if (is_rate_B) { |
| 69 | if (!tbl_B) { |
| 70 | dev_err(ufs_qcom_phy->dev, "%s: tbl_B is NULL", |
| 71 | __func__); |
| 72 | ret = EINVAL; |
| 73 | goto out; |
| 74 | } |
| 75 | |
Subhash Jadavani | cce6fbc | 2016-08-11 11:35:26 -0700 | [diff] [blame] | 76 | ufs_qcom_phy_write_tbl(ufs_qcom_phy, tbl_B, tbl_size_B); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 77 | } |
| 78 | |
| 79 | /* flush buffered writes */ |
| 80 | mb(); |
| 81 | |
| 82 | out: |
| 83 | return ret; |
| 84 | } |
Axel Lin | 358d6c8 | 2015-03-23 11:54:50 +0800 | [diff] [blame] | 85 | EXPORT_SYMBOL_GPL(ufs_qcom_phy_calibrate); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 86 | |
| 87 | struct phy *ufs_qcom_phy_generic_probe(struct platform_device *pdev, |
| 88 | struct ufs_qcom_phy *common_cfg, |
Axel Lin | 4a9e5ca | 2015-07-15 15:33:51 +0800 | [diff] [blame] | 89 | const struct phy_ops *ufs_qcom_phy_gen_ops, |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 90 | struct ufs_qcom_phy_specific_ops *phy_spec_ops) |
| 91 | { |
| 92 | int err; |
| 93 | struct device *dev = &pdev->dev; |
| 94 | struct phy *generic_phy = NULL; |
| 95 | struct phy_provider *phy_provider; |
| 96 | |
| 97 | err = ufs_qcom_phy_base_init(pdev, common_cfg); |
| 98 | if (err) { |
| 99 | dev_err(dev, "%s: phy base init failed %d\n", __func__, err); |
| 100 | goto out; |
| 101 | } |
| 102 | |
| 103 | phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
| 104 | if (IS_ERR(phy_provider)) { |
| 105 | err = PTR_ERR(phy_provider); |
| 106 | dev_err(dev, "%s: failed to register phy %d\n", __func__, err); |
| 107 | goto out; |
| 108 | } |
| 109 | |
| 110 | generic_phy = devm_phy_create(dev, NULL, ufs_qcom_phy_gen_ops); |
| 111 | if (IS_ERR(generic_phy)) { |
| 112 | err = PTR_ERR(generic_phy); |
| 113 | dev_err(dev, "%s: failed to create phy %d\n", __func__, err); |
Axel Lin | d89a7f6 | 2015-03-03 09:05:55 +0800 | [diff] [blame] | 114 | generic_phy = NULL; |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 115 | goto out; |
| 116 | } |
| 117 | |
Subhash Jadavani | 8bfeb63 | 2017-04-03 17:14:30 -0700 | [diff] [blame] | 118 | if (of_property_read_u32(dev->of_node, "lanes-per-direction", |
| 119 | &common_cfg->lanes_per_direction)) |
| 120 | common_cfg->lanes_per_direction = |
| 121 | UFS_PHY_DEFAULT_LANES_PER_DIRECTION; |
| 122 | |
Subhash Jadavani | 9c80770 | 2017-04-01 00:35:51 -0700 | [diff] [blame] | 123 | /* |
| 124 | * UFS PHY power management is managed by its parent (UFS host |
| 125 | * controller) hence set the no the no runtime PM callbacks flag |
| 126 | * on UFS PHY device to avoid any accidental attempt to call the |
| 127 | * PM callbacks for PHY device. |
| 128 | */ |
| 129 | pm_runtime_no_callbacks(&generic_phy->dev); |
| 130 | |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 131 | common_cfg->phy_spec_ops = phy_spec_ops; |
| 132 | common_cfg->dev = dev; |
| 133 | |
| 134 | out: |
| 135 | return generic_phy; |
| 136 | } |
Axel Lin | 358d6c8 | 2015-03-23 11:54:50 +0800 | [diff] [blame] | 137 | EXPORT_SYMBOL_GPL(ufs_qcom_phy_generic_probe); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 138 | |
| 139 | /* |
| 140 | * This assumes the embedded phy structure inside generic_phy is of type |
| 141 | * struct ufs_qcom_phy. In order to function properly it's crucial |
| 142 | * to keep the embedded struct "struct ufs_qcom_phy common_cfg" |
| 143 | * as the first inside generic_phy. |
| 144 | */ |
| 145 | struct ufs_qcom_phy *get_ufs_qcom_phy(struct phy *generic_phy) |
| 146 | { |
| 147 | return (struct ufs_qcom_phy *)phy_get_drvdata(generic_phy); |
| 148 | } |
Axel Lin | 358d6c8 | 2015-03-23 11:54:50 +0800 | [diff] [blame] | 149 | EXPORT_SYMBOL_GPL(get_ufs_qcom_phy); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 150 | |
| 151 | static |
| 152 | int ufs_qcom_phy_base_init(struct platform_device *pdev, |
| 153 | struct ufs_qcom_phy *phy_common) |
| 154 | { |
| 155 | struct device *dev = &pdev->dev; |
| 156 | struct resource *res; |
| 157 | int err = 0; |
| 158 | |
| 159 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_mem"); |
Subhash Jadavani | cce6fbc | 2016-08-11 11:35:26 -0700 | [diff] [blame] | 160 | if (!res) { |
| 161 | dev_err(dev, "%s: phy_mem resource not found\n", __func__); |
| 162 | err = -ENOMEM; |
| 163 | goto out; |
| 164 | } |
| 165 | |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 166 | phy_common->mmio = devm_ioremap_resource(dev, res); |
| 167 | if (IS_ERR((void const *)phy_common->mmio)) { |
| 168 | err = PTR_ERR((void const *)phy_common->mmio); |
| 169 | phy_common->mmio = NULL; |
| 170 | dev_err(dev, "%s: ioremap for phy_mem resource failed %d\n", |
| 171 | __func__, err); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 172 | } |
Subhash Jadavani | cce6fbc | 2016-08-11 11:35:26 -0700 | [diff] [blame] | 173 | out: |
| 174 | return err; |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 175 | } |
| 176 | |
| 177 | static int __ufs_qcom_phy_clk_get(struct phy *phy, |
| 178 | const char *name, struct clk **clk_out, bool err_print) |
| 179 | { |
| 180 | struct clk *clk; |
| 181 | int err = 0; |
| 182 | struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy); |
| 183 | struct device *dev = ufs_qcom_phy->dev; |
| 184 | |
| 185 | clk = devm_clk_get(dev, name); |
| 186 | if (IS_ERR(clk)) { |
| 187 | err = PTR_ERR(clk); |
| 188 | if (err_print) |
| 189 | dev_err(dev, "failed to get %s err %d", name, err); |
| 190 | } else { |
| 191 | *clk_out = clk; |
| 192 | } |
| 193 | |
| 194 | return err; |
| 195 | } |
| 196 | |
| 197 | static |
| 198 | int ufs_qcom_phy_clk_get(struct phy *phy, |
| 199 | const char *name, struct clk **clk_out) |
| 200 | { |
| 201 | return __ufs_qcom_phy_clk_get(phy, name, clk_out, true); |
| 202 | } |
| 203 | |
| 204 | int |
| 205 | ufs_qcom_phy_init_clks(struct phy *generic_phy, |
| 206 | struct ufs_qcom_phy *phy_common) |
| 207 | { |
| 208 | int err; |
| 209 | |
Subhash Jadavani | cce6fbc | 2016-08-11 11:35:26 -0700 | [diff] [blame] | 210 | /* |
| 211 | * tx_iface_clk does not exist in newer version of ufs-phy HW, |
| 212 | * so don't return error if it is not found |
| 213 | */ |
Subhash Jadavani | 9c80770 | 2017-04-01 00:35:51 -0700 | [diff] [blame] | 214 | __ufs_qcom_phy_clk_get(generic_phy, "tx_iface_clk", |
| 215 | &phy_common->tx_iface_clk, false); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 216 | |
Subhash Jadavani | cce6fbc | 2016-08-11 11:35:26 -0700 | [diff] [blame] | 217 | /* |
| 218 | * rx_iface_clk does not exist in newer version of ufs-phy HW, |
| 219 | * so don't return error if it is not found |
| 220 | */ |
Subhash Jadavani | 9c80770 | 2017-04-01 00:35:51 -0700 | [diff] [blame] | 221 | __ufs_qcom_phy_clk_get(generic_phy, "rx_iface_clk", |
| 222 | &phy_common->rx_iface_clk, false); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 223 | |
| 224 | err = ufs_qcom_phy_clk_get(generic_phy, "ref_clk_src", |
| 225 | &phy_common->ref_clk_src); |
| 226 | if (err) |
| 227 | goto out; |
| 228 | |
| 229 | /* |
| 230 | * "ref_clk_parent" is optional hence don't abort init if it's not |
| 231 | * found. |
| 232 | */ |
| 233 | __ufs_qcom_phy_clk_get(generic_phy, "ref_clk_parent", |
| 234 | &phy_common->ref_clk_parent, false); |
| 235 | |
| 236 | err = ufs_qcom_phy_clk_get(generic_phy, "ref_clk", |
| 237 | &phy_common->ref_clk); |
Subhash Jadavani | cce6fbc | 2016-08-11 11:35:26 -0700 | [diff] [blame] | 238 | if (err) |
| 239 | goto out; |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 240 | |
Subhash Jadavani | cce6fbc | 2016-08-11 11:35:26 -0700 | [diff] [blame] | 241 | /* |
| 242 | * "ref_aux_clk" is optional and only supported by certain |
| 243 | * phy versions, don't abort init if it's not found. |
| 244 | */ |
| 245 | __ufs_qcom_phy_clk_get(generic_phy, "ref_aux_clk", |
| 246 | &phy_common->ref_aux_clk, false); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 247 | out: |
| 248 | return err; |
| 249 | } |
Axel Lin | 358d6c8 | 2015-03-23 11:54:50 +0800 | [diff] [blame] | 250 | EXPORT_SYMBOL_GPL(ufs_qcom_phy_init_clks); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 251 | |
| 252 | int |
| 253 | ufs_qcom_phy_init_vregulators(struct phy *generic_phy, |
| 254 | struct ufs_qcom_phy *phy_common) |
| 255 | { |
| 256 | int err; |
| 257 | |
| 258 | err = ufs_qcom_phy_init_vreg(generic_phy, &phy_common->vdda_pll, |
| 259 | "vdda-pll"); |
| 260 | if (err) |
| 261 | goto out; |
| 262 | |
| 263 | err = ufs_qcom_phy_init_vreg(generic_phy, &phy_common->vdda_phy, |
| 264 | "vdda-phy"); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 265 | if (err) |
| 266 | goto out; |
| 267 | |
| 268 | /* vddp-ref-clk-* properties are optional */ |
| 269 | __ufs_qcom_phy_init_vreg(generic_phy, &phy_common->vddp_ref_clk, |
| 270 | "vddp-ref-clk", true); |
| 271 | out: |
| 272 | return err; |
| 273 | } |
Axel Lin | 358d6c8 | 2015-03-23 11:54:50 +0800 | [diff] [blame] | 274 | EXPORT_SYMBOL_GPL(ufs_qcom_phy_init_vregulators); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 275 | |
| 276 | static int __ufs_qcom_phy_init_vreg(struct phy *phy, |
| 277 | struct ufs_qcom_phy_vreg *vreg, const char *name, bool optional) |
| 278 | { |
| 279 | int err = 0; |
| 280 | struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy); |
| 281 | struct device *dev = ufs_qcom_phy->dev; |
| 282 | |
| 283 | char prop_name[MAX_PROP_NAME]; |
| 284 | |
Subhash Jadavani | 9c80770 | 2017-04-01 00:35:51 -0700 | [diff] [blame] | 285 | if (dev->of_node) { |
| 286 | snprintf(prop_name, MAX_PROP_NAME, "%s-supply", name); |
| 287 | if (!of_parse_phandle(dev->of_node, prop_name, 0)) { |
| 288 | dev_dbg(dev, "No vreg data found for %s\n", prop_name); |
| 289 | return optional ? err : -ENODATA; |
| 290 | } |
| 291 | } |
| 292 | |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 293 | vreg->name = kstrdup(name, GFP_KERNEL); |
| 294 | if (!vreg->name) { |
| 295 | err = -ENOMEM; |
| 296 | goto out; |
| 297 | } |
| 298 | |
| 299 | vreg->reg = devm_regulator_get(dev, name); |
| 300 | if (IS_ERR(vreg->reg)) { |
| 301 | err = PTR_ERR(vreg->reg); |
| 302 | vreg->reg = NULL; |
| 303 | if (!optional) |
| 304 | dev_err(dev, "failed to get %s, %d\n", name, err); |
| 305 | goto out; |
| 306 | } |
| 307 | |
| 308 | if (dev->of_node) { |
| 309 | snprintf(prop_name, MAX_PROP_NAME, "%s-max-microamp", name); |
| 310 | err = of_property_read_u32(dev->of_node, |
| 311 | prop_name, &vreg->max_uA); |
| 312 | if (err && err != -EINVAL) { |
| 313 | dev_err(dev, "%s: failed to read %s\n", |
| 314 | __func__, prop_name); |
| 315 | goto out; |
| 316 | } else if (err == -EINVAL || !vreg->max_uA) { |
| 317 | if (regulator_count_voltages(vreg->reg) > 0) { |
| 318 | dev_err(dev, "%s: %s is mandatory\n", |
| 319 | __func__, prop_name); |
| 320 | goto out; |
| 321 | } |
| 322 | err = 0; |
| 323 | } |
| 324 | snprintf(prop_name, MAX_PROP_NAME, "%s-always-on", name); |
Julia Lawall | 3ea981e | 2016-08-05 13:25:13 +0200 | [diff] [blame] | 325 | vreg->is_always_on = of_property_read_bool(dev->of_node, |
| 326 | prop_name); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 327 | } |
| 328 | |
| 329 | if (!strcmp(name, "vdda-pll")) { |
| 330 | vreg->max_uV = VDDA_PLL_MAX_UV; |
| 331 | vreg->min_uV = VDDA_PLL_MIN_UV; |
| 332 | } else if (!strcmp(name, "vdda-phy")) { |
| 333 | vreg->max_uV = VDDA_PHY_MAX_UV; |
| 334 | vreg->min_uV = VDDA_PHY_MIN_UV; |
| 335 | } else if (!strcmp(name, "vddp-ref-clk")) { |
| 336 | vreg->max_uV = VDDP_REF_CLK_MAX_UV; |
| 337 | vreg->min_uV = VDDP_REF_CLK_MIN_UV; |
| 338 | } |
| 339 | |
| 340 | out: |
| 341 | if (err) |
| 342 | kfree(vreg->name); |
| 343 | return err; |
| 344 | } |
| 345 | |
| 346 | static int ufs_qcom_phy_init_vreg(struct phy *phy, |
| 347 | struct ufs_qcom_phy_vreg *vreg, const char *name) |
| 348 | { |
| 349 | return __ufs_qcom_phy_init_vreg(phy, vreg, name, false); |
| 350 | } |
| 351 | |
| 352 | static |
| 353 | int ufs_qcom_phy_cfg_vreg(struct phy *phy, |
| 354 | struct ufs_qcom_phy_vreg *vreg, bool on) |
| 355 | { |
| 356 | int ret = 0; |
| 357 | struct regulator *reg = vreg->reg; |
| 358 | const char *name = vreg->name; |
| 359 | int min_uV; |
| 360 | int uA_load; |
| 361 | struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy); |
| 362 | struct device *dev = ufs_qcom_phy->dev; |
| 363 | |
| 364 | BUG_ON(!vreg); |
| 365 | |
| 366 | if (regulator_count_voltages(reg) > 0) { |
| 367 | min_uV = on ? vreg->min_uV : 0; |
| 368 | ret = regulator_set_voltage(reg, min_uV, vreg->max_uV); |
| 369 | if (ret) { |
| 370 | dev_err(dev, "%s: %s set voltage failed, err=%d\n", |
| 371 | __func__, name, ret); |
| 372 | goto out; |
| 373 | } |
| 374 | uA_load = on ? vreg->max_uA : 0; |
Stephen Rothwell | 7e476c7 | 2015-03-10 13:44:41 +1100 | [diff] [blame] | 375 | ret = regulator_set_load(reg, uA_load); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 376 | if (ret >= 0) { |
| 377 | /* |
Stephen Rothwell | 7e476c7 | 2015-03-10 13:44:41 +1100 | [diff] [blame] | 378 | * regulator_set_load() returns new regulator |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 379 | * mode upon success. |
| 380 | */ |
| 381 | ret = 0; |
| 382 | } else { |
| 383 | dev_err(dev, "%s: %s set optimum mode(uA_load=%d) failed, err=%d\n", |
| 384 | __func__, name, uA_load, ret); |
| 385 | goto out; |
| 386 | } |
| 387 | } |
| 388 | out: |
| 389 | return ret; |
| 390 | } |
| 391 | |
| 392 | static |
| 393 | int ufs_qcom_phy_enable_vreg(struct phy *phy, |
| 394 | struct ufs_qcom_phy_vreg *vreg) |
| 395 | { |
| 396 | struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy); |
| 397 | struct device *dev = ufs_qcom_phy->dev; |
| 398 | int ret = 0; |
| 399 | |
| 400 | if (!vreg || vreg->enabled) |
| 401 | goto out; |
| 402 | |
| 403 | ret = ufs_qcom_phy_cfg_vreg(phy, vreg, true); |
| 404 | if (ret) { |
| 405 | dev_err(dev, "%s: ufs_qcom_phy_cfg_vreg() failed, err=%d\n", |
| 406 | __func__, ret); |
| 407 | goto out; |
| 408 | } |
| 409 | |
| 410 | ret = regulator_enable(vreg->reg); |
| 411 | if (ret) { |
| 412 | dev_err(dev, "%s: enable failed, err=%d\n", |
| 413 | __func__, ret); |
| 414 | goto out; |
| 415 | } |
| 416 | |
| 417 | vreg->enabled = true; |
| 418 | out: |
| 419 | return ret; |
| 420 | } |
| 421 | |
| 422 | int ufs_qcom_phy_enable_ref_clk(struct phy *generic_phy) |
| 423 | { |
| 424 | int ret = 0; |
| 425 | struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy); |
| 426 | |
| 427 | if (phy->is_ref_clk_enabled) |
| 428 | goto out; |
| 429 | |
| 430 | /* |
| 431 | * reference clock is propagated in a daisy-chained manner from |
| 432 | * source to phy, so ungate them at each stage. |
| 433 | */ |
| 434 | ret = clk_prepare_enable(phy->ref_clk_src); |
| 435 | if (ret) { |
| 436 | dev_err(phy->dev, "%s: ref_clk_src enable failed %d\n", |
| 437 | __func__, ret); |
| 438 | goto out; |
| 439 | } |
| 440 | |
| 441 | /* |
| 442 | * "ref_clk_parent" is optional clock hence make sure that clk reference |
| 443 | * is available before trying to enable the clock. |
| 444 | */ |
| 445 | if (phy->ref_clk_parent) { |
| 446 | ret = clk_prepare_enable(phy->ref_clk_parent); |
| 447 | if (ret) { |
| 448 | dev_err(phy->dev, "%s: ref_clk_parent enable failed %d\n", |
| 449 | __func__, ret); |
| 450 | goto out_disable_src; |
| 451 | } |
| 452 | } |
| 453 | |
| 454 | ret = clk_prepare_enable(phy->ref_clk); |
| 455 | if (ret) { |
| 456 | dev_err(phy->dev, "%s: ref_clk enable failed %d\n", |
| 457 | __func__, ret); |
| 458 | goto out_disable_parent; |
| 459 | } |
| 460 | |
Subhash Jadavani | cce6fbc | 2016-08-11 11:35:26 -0700 | [diff] [blame] | 461 | /* |
| 462 | * "ref_aux_clk" is optional clock and only supported by certain |
| 463 | * phy versions, hence make sure that clk reference is available |
| 464 | * before trying to enable the clock. |
| 465 | */ |
| 466 | if (phy->ref_aux_clk) { |
| 467 | ret = clk_prepare_enable(phy->ref_aux_clk); |
| 468 | if (ret) { |
| 469 | dev_err(phy->dev, "%s: ref_aux_clk enable failed %d\n", |
| 470 | __func__, ret); |
| 471 | goto out_disable_ref; |
| 472 | } |
| 473 | } |
| 474 | |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 475 | phy->is_ref_clk_enabled = true; |
| 476 | goto out; |
| 477 | |
Subhash Jadavani | cce6fbc | 2016-08-11 11:35:26 -0700 | [diff] [blame] | 478 | out_disable_ref: |
| 479 | if (phy->ref_clk) |
| 480 | clk_disable_unprepare(phy->ref_clk); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 481 | out_disable_parent: |
| 482 | if (phy->ref_clk_parent) |
| 483 | clk_disable_unprepare(phy->ref_clk_parent); |
| 484 | out_disable_src: |
| 485 | clk_disable_unprepare(phy->ref_clk_src); |
| 486 | out: |
| 487 | return ret; |
| 488 | } |
Yaniv Gardi | 65d49b3 | 2015-09-02 11:32:17 +0300 | [diff] [blame] | 489 | EXPORT_SYMBOL_GPL(ufs_qcom_phy_enable_ref_clk); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 490 | |
| 491 | static |
| 492 | int ufs_qcom_phy_disable_vreg(struct phy *phy, |
| 493 | struct ufs_qcom_phy_vreg *vreg) |
| 494 | { |
| 495 | struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy); |
| 496 | struct device *dev = ufs_qcom_phy->dev; |
| 497 | int ret = 0; |
| 498 | |
Nitin Rawat | 5645285 | 2019-10-21 20:55:22 +0530 | [diff] [blame] | 499 | if (!vreg || !vreg->enabled) |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 500 | goto out; |
| 501 | |
Nitin Rawat | 5645285 | 2019-10-21 20:55:22 +0530 | [diff] [blame] | 502 | if (vreg->is_always_on) { |
| 503 | /* voting 0 uA load will keep regulator in LPM mode */ |
| 504 | ret = regulator_set_load(vreg->reg, 0); |
| 505 | if (ret >= 0) { |
| 506 | /* |
| 507 | * regulator_set_load() returns new regulator |
| 508 | * mode upon success |
| 509 | */ |
| 510 | ret = 0; |
| 511 | } else { |
| 512 | dev_err(dev, "%s: %s set optimum mode(uA_load=0) failed, err=%d\n", |
| 513 | __func__, vreg->name, ret); |
| 514 | } |
| 515 | goto out; |
| 516 | } |
| 517 | |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 518 | ret = regulator_disable(vreg->reg); |
| 519 | |
| 520 | if (!ret) { |
| 521 | /* ignore errors on applying disable config */ |
| 522 | ufs_qcom_phy_cfg_vreg(phy, vreg, false); |
| 523 | vreg->enabled = false; |
| 524 | } else { |
| 525 | dev_err(dev, "%s: %s disable failed, err=%d\n", |
| 526 | __func__, vreg->name, ret); |
| 527 | } |
| 528 | out: |
| 529 | return ret; |
| 530 | } |
| 531 | |
| 532 | void ufs_qcom_phy_disable_ref_clk(struct phy *generic_phy) |
| 533 | { |
| 534 | struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy); |
| 535 | |
| 536 | if (phy->is_ref_clk_enabled) { |
Subhash Jadavani | cce6fbc | 2016-08-11 11:35:26 -0700 | [diff] [blame] | 537 | /* |
| 538 | * "ref_aux_clk" is optional clock and only supported by |
| 539 | * certain phy versions, hence make sure that clk reference |
| 540 | * is available before trying to disable the clock. |
| 541 | */ |
| 542 | if (phy->ref_aux_clk) |
| 543 | clk_disable_unprepare(phy->ref_aux_clk); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 544 | clk_disable_unprepare(phy->ref_clk); |
| 545 | /* |
| 546 | * "ref_clk_parent" is optional clock hence make sure that clk |
| 547 | * reference is available before trying to disable the clock. |
| 548 | */ |
| 549 | if (phy->ref_clk_parent) |
| 550 | clk_disable_unprepare(phy->ref_clk_parent); |
| 551 | clk_disable_unprepare(phy->ref_clk_src); |
| 552 | phy->is_ref_clk_enabled = false; |
| 553 | } |
| 554 | } |
Yaniv Gardi | 65d49b3 | 2015-09-02 11:32:17 +0300 | [diff] [blame] | 555 | EXPORT_SYMBOL_GPL(ufs_qcom_phy_disable_ref_clk); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 556 | |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 557 | /* Turn ON M-PHY RMMI interface clocks */ |
| 558 | int ufs_qcom_phy_enable_iface_clk(struct phy *generic_phy) |
| 559 | { |
| 560 | struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy); |
| 561 | int ret = 0; |
| 562 | |
| 563 | if (phy->is_iface_clk_enabled) |
| 564 | goto out; |
| 565 | |
Subhash Jadavani | cce6fbc | 2016-08-11 11:35:26 -0700 | [diff] [blame] | 566 | if (!phy->tx_iface_clk) |
| 567 | goto out; |
| 568 | |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 569 | ret = clk_prepare_enable(phy->tx_iface_clk); |
| 570 | if (ret) { |
| 571 | dev_err(phy->dev, "%s: tx_iface_clk enable failed %d\n", |
| 572 | __func__, ret); |
| 573 | goto out; |
| 574 | } |
| 575 | ret = clk_prepare_enable(phy->rx_iface_clk); |
| 576 | if (ret) { |
| 577 | clk_disable_unprepare(phy->tx_iface_clk); |
| 578 | dev_err(phy->dev, "%s: rx_iface_clk enable failed %d. disabling also tx_iface_clk\n", |
| 579 | __func__, ret); |
| 580 | goto out; |
| 581 | } |
| 582 | phy->is_iface_clk_enabled = true; |
| 583 | |
| 584 | out: |
| 585 | return ret; |
| 586 | } |
Yaniv Gardi | 65d49b3 | 2015-09-02 11:32:17 +0300 | [diff] [blame] | 587 | EXPORT_SYMBOL_GPL(ufs_qcom_phy_enable_iface_clk); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 588 | |
| 589 | /* Turn OFF M-PHY RMMI interface clocks */ |
| 590 | void ufs_qcom_phy_disable_iface_clk(struct phy *generic_phy) |
| 591 | { |
| 592 | struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy); |
| 593 | |
Subhash Jadavani | cce6fbc | 2016-08-11 11:35:26 -0700 | [diff] [blame] | 594 | if (!phy->tx_iface_clk) |
| 595 | return; |
| 596 | |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 597 | if (phy->is_iface_clk_enabled) { |
| 598 | clk_disable_unprepare(phy->tx_iface_clk); |
| 599 | clk_disable_unprepare(phy->rx_iface_clk); |
| 600 | phy->is_iface_clk_enabled = false; |
| 601 | } |
| 602 | } |
Yaniv Gardi | 65d49b3 | 2015-09-02 11:32:17 +0300 | [diff] [blame] | 603 | EXPORT_SYMBOL_GPL(ufs_qcom_phy_disable_iface_clk); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 604 | |
| 605 | int ufs_qcom_phy_start_serdes(struct phy *generic_phy) |
| 606 | { |
| 607 | struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy); |
| 608 | int ret = 0; |
| 609 | |
| 610 | if (!ufs_qcom_phy->phy_spec_ops->start_serdes) { |
| 611 | dev_err(ufs_qcom_phy->dev, "%s: start_serdes() callback is not supported\n", |
| 612 | __func__); |
| 613 | ret = -ENOTSUPP; |
| 614 | } else { |
| 615 | ufs_qcom_phy->phy_spec_ops->start_serdes(ufs_qcom_phy); |
| 616 | } |
| 617 | |
| 618 | return ret; |
| 619 | } |
Yaniv Gardi | 65d49b3 | 2015-09-02 11:32:17 +0300 | [diff] [blame] | 620 | EXPORT_SYMBOL_GPL(ufs_qcom_phy_start_serdes); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 621 | |
| 622 | int ufs_qcom_phy_set_tx_lane_enable(struct phy *generic_phy, u32 tx_lanes) |
| 623 | { |
| 624 | struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy); |
| 625 | int ret = 0; |
| 626 | |
Subhash Jadavani | cce6fbc | 2016-08-11 11:35:26 -0700 | [diff] [blame] | 627 | if (ufs_qcom_phy->phy_spec_ops->set_tx_lane_enable) |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 628 | ufs_qcom_phy->phy_spec_ops->set_tx_lane_enable(ufs_qcom_phy, |
| 629 | tx_lanes); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 630 | |
| 631 | return ret; |
| 632 | } |
Yaniv Gardi | 65d49b3 | 2015-09-02 11:32:17 +0300 | [diff] [blame] | 633 | EXPORT_SYMBOL_GPL(ufs_qcom_phy_set_tx_lane_enable); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 634 | |
Subhash Jadavani | cce6fbc | 2016-08-11 11:35:26 -0700 | [diff] [blame] | 635 | int ufs_qcom_phy_ctrl_rx_linecfg(struct phy *generic_phy, bool ctrl) |
| 636 | { |
| 637 | struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy); |
| 638 | int ret = 0; |
| 639 | |
| 640 | if (ufs_qcom_phy->phy_spec_ops->ctrl_rx_linecfg) |
| 641 | ufs_qcom_phy->phy_spec_ops->ctrl_rx_linecfg(ufs_qcom_phy, ctrl); |
| 642 | |
| 643 | return ret; |
| 644 | } |
| 645 | EXPORT_SYMBOL_GPL(ufs_qcom_phy_ctrl_rx_linecfg); |
| 646 | |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 647 | void ufs_qcom_phy_save_controller_version(struct phy *generic_phy, |
| 648 | u8 major, u16 minor, u16 step) |
| 649 | { |
| 650 | struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy); |
| 651 | |
| 652 | ufs_qcom_phy->host_ctrl_rev_major = major; |
| 653 | ufs_qcom_phy->host_ctrl_rev_minor = minor; |
| 654 | ufs_qcom_phy->host_ctrl_rev_step = step; |
| 655 | } |
Yaniv Gardi | 65d49b3 | 2015-09-02 11:32:17 +0300 | [diff] [blame] | 656 | EXPORT_SYMBOL_GPL(ufs_qcom_phy_save_controller_version); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 657 | |
| 658 | int ufs_qcom_phy_calibrate_phy(struct phy *generic_phy, bool is_rate_B) |
| 659 | { |
| 660 | struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy); |
| 661 | int ret = 0; |
| 662 | |
| 663 | if (!ufs_qcom_phy->phy_spec_ops->calibrate_phy) { |
| 664 | dev_err(ufs_qcom_phy->dev, "%s: calibrate_phy() callback is not supported\n", |
| 665 | __func__); |
| 666 | ret = -ENOTSUPP; |
| 667 | } else { |
| 668 | ret = ufs_qcom_phy->phy_spec_ops-> |
| 669 | calibrate_phy(ufs_qcom_phy, is_rate_B); |
| 670 | if (ret) |
| 671 | dev_err(ufs_qcom_phy->dev, "%s: calibrate_phy() failed %d\n", |
| 672 | __func__, ret); |
| 673 | } |
| 674 | |
| 675 | return ret; |
| 676 | } |
Yaniv Gardi | 65d49b3 | 2015-09-02 11:32:17 +0300 | [diff] [blame] | 677 | EXPORT_SYMBOL_GPL(ufs_qcom_phy_calibrate_phy); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 678 | |
Subhash Jadavani | cce6fbc | 2016-08-11 11:35:26 -0700 | [diff] [blame] | 679 | const char *ufs_qcom_phy_name(struct phy *phy) |
| 680 | { |
| 681 | struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy); |
| 682 | |
| 683 | return ufs_qcom_phy->name; |
| 684 | } |
| 685 | EXPORT_SYMBOL(ufs_qcom_phy_name); |
| 686 | |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 687 | int ufs_qcom_phy_remove(struct phy *generic_phy, |
| 688 | struct ufs_qcom_phy *ufs_qcom_phy) |
| 689 | { |
| 690 | phy_power_off(generic_phy); |
| 691 | |
| 692 | kfree(ufs_qcom_phy->vdda_pll.name); |
| 693 | kfree(ufs_qcom_phy->vdda_phy.name); |
| 694 | |
| 695 | return 0; |
| 696 | } |
Axel Lin | 358d6c8 | 2015-03-23 11:54:50 +0800 | [diff] [blame] | 697 | EXPORT_SYMBOL_GPL(ufs_qcom_phy_remove); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 698 | |
| 699 | int ufs_qcom_phy_exit(struct phy *generic_phy) |
| 700 | { |
| 701 | struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy); |
| 702 | |
| 703 | if (ufs_qcom_phy->is_powered_on) |
| 704 | phy_power_off(generic_phy); |
| 705 | |
| 706 | return 0; |
| 707 | } |
Axel Lin | 358d6c8 | 2015-03-23 11:54:50 +0800 | [diff] [blame] | 708 | EXPORT_SYMBOL_GPL(ufs_qcom_phy_exit); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 709 | |
| 710 | int ufs_qcom_phy_is_pcs_ready(struct phy *generic_phy) |
| 711 | { |
| 712 | struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy); |
| 713 | |
| 714 | if (!ufs_qcom_phy->phy_spec_ops->is_physical_coding_sublayer_ready) { |
| 715 | dev_err(ufs_qcom_phy->dev, "%s: is_physical_coding_sublayer_ready() callback is not supported\n", |
| 716 | __func__); |
| 717 | return -ENOTSUPP; |
| 718 | } |
| 719 | |
| 720 | return ufs_qcom_phy->phy_spec_ops-> |
| 721 | is_physical_coding_sublayer_ready(ufs_qcom_phy); |
| 722 | } |
Yaniv Gardi | 65d49b3 | 2015-09-02 11:32:17 +0300 | [diff] [blame] | 723 | EXPORT_SYMBOL_GPL(ufs_qcom_phy_is_pcs_ready); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 724 | |
| 725 | int ufs_qcom_phy_power_on(struct phy *generic_phy) |
| 726 | { |
| 727 | struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy); |
| 728 | struct device *dev = phy_common->dev; |
| 729 | int err; |
| 730 | |
| 731 | err = ufs_qcom_phy_enable_vreg(generic_phy, &phy_common->vdda_phy); |
| 732 | if (err) { |
| 733 | dev_err(dev, "%s enable vdda_phy failed, err=%d\n", |
| 734 | __func__, err); |
| 735 | goto out; |
| 736 | } |
| 737 | |
| 738 | phy_common->phy_spec_ops->power_control(phy_common, true); |
| 739 | |
| 740 | /* vdda_pll also enables ref clock LDOs so enable it first */ |
| 741 | err = ufs_qcom_phy_enable_vreg(generic_phy, &phy_common->vdda_pll); |
| 742 | if (err) { |
| 743 | dev_err(dev, "%s enable vdda_pll failed, err=%d\n", |
| 744 | __func__, err); |
| 745 | goto out_disable_phy; |
| 746 | } |
| 747 | |
| 748 | err = ufs_qcom_phy_enable_ref_clk(generic_phy); |
| 749 | if (err) { |
| 750 | dev_err(dev, "%s enable phy ref clock failed, err=%d\n", |
| 751 | __func__, err); |
| 752 | goto out_disable_pll; |
| 753 | } |
| 754 | |
| 755 | /* enable device PHY ref_clk pad rail */ |
| 756 | if (phy_common->vddp_ref_clk.reg) { |
| 757 | err = ufs_qcom_phy_enable_vreg(generic_phy, |
| 758 | &phy_common->vddp_ref_clk); |
| 759 | if (err) { |
| 760 | dev_err(dev, "%s enable vddp_ref_clk failed, err=%d\n", |
| 761 | __func__, err); |
| 762 | goto out_disable_ref_clk; |
| 763 | } |
| 764 | } |
| 765 | |
| 766 | phy_common->is_powered_on = true; |
| 767 | goto out; |
| 768 | |
| 769 | out_disable_ref_clk: |
| 770 | ufs_qcom_phy_disable_ref_clk(generic_phy); |
| 771 | out_disable_pll: |
| 772 | ufs_qcom_phy_disable_vreg(generic_phy, &phy_common->vdda_pll); |
| 773 | out_disable_phy: |
| 774 | ufs_qcom_phy_disable_vreg(generic_phy, &phy_common->vdda_phy); |
| 775 | out: |
| 776 | return err; |
| 777 | } |
Axel Lin | 358d6c8 | 2015-03-23 11:54:50 +0800 | [diff] [blame] | 778 | EXPORT_SYMBOL_GPL(ufs_qcom_phy_power_on); |
Yaniv Gardi | adaafaa | 2015-01-15 16:32:35 +0200 | [diff] [blame] | 779 | |
| 780 | int ufs_qcom_phy_power_off(struct phy *generic_phy) |
| 781 | { |
| 782 | struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy); |
| 783 | |
| 784 | phy_common->phy_spec_ops->power_control(phy_common, false); |
| 785 | |
| 786 | if (phy_common->vddp_ref_clk.reg) |
| 787 | ufs_qcom_phy_disable_vreg(generic_phy, |
| 788 | &phy_common->vddp_ref_clk); |
| 789 | ufs_qcom_phy_disable_ref_clk(generic_phy); |
| 790 | |
| 791 | ufs_qcom_phy_disable_vreg(generic_phy, &phy_common->vdda_pll); |
| 792 | ufs_qcom_phy_disable_vreg(generic_phy, &phy_common->vdda_phy); |
| 793 | phy_common->is_powered_on = false; |
| 794 | |
| 795 | return 0; |
| 796 | } |
Axel Lin | 358d6c8 | 2015-03-23 11:54:50 +0800 | [diff] [blame] | 797 | EXPORT_SYMBOL_GPL(ufs_qcom_phy_power_off); |
Subhash Jadavani | cce6fbc | 2016-08-11 11:35:26 -0700 | [diff] [blame] | 798 | |
| 799 | int ufs_qcom_phy_configure_lpm(struct phy *generic_phy, bool enable) |
| 800 | { |
| 801 | struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy); |
| 802 | int ret = 0; |
| 803 | |
| 804 | if (ufs_qcom_phy->phy_spec_ops->configure_lpm) { |
| 805 | ret = ufs_qcom_phy->phy_spec_ops-> |
| 806 | configure_lpm(ufs_qcom_phy, enable); |
| 807 | if (ret) |
| 808 | dev_err(ufs_qcom_phy->dev, |
| 809 | "%s: configure_lpm(%s) failed %d\n", |
| 810 | __func__, enable ? "enable" : "disable", ret); |
| 811 | } |
| 812 | |
| 813 | return ret; |
| 814 | } |
| 815 | EXPORT_SYMBOL(ufs_qcom_phy_configure_lpm); |
Subhash Jadavani | 9c80770 | 2017-04-01 00:35:51 -0700 | [diff] [blame] | 816 | |
| 817 | void ufs_qcom_phy_dump_regs(struct ufs_qcom_phy *phy, int offset, |
| 818 | int len, char *prefix) |
| 819 | { |
| 820 | print_hex_dump(KERN_ERR, prefix, |
| 821 | len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE, |
| 822 | 16, 4, phy->mmio + offset, len, false); |
| 823 | } |
| 824 | EXPORT_SYMBOL(ufs_qcom_phy_dump_regs); |
| 825 | |
| 826 | void ufs_qcom_phy_dbg_register_dump(struct phy *generic_phy) |
| 827 | { |
| 828 | struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy); |
| 829 | |
| 830 | if (ufs_qcom_phy->phy_spec_ops->dbg_register_dump) |
| 831 | ufs_qcom_phy->phy_spec_ops->dbg_register_dump(ufs_qcom_phy); |
| 832 | } |
| 833 | EXPORT_SYMBOL(ufs_qcom_phy_dbg_register_dump); |