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gerrit-public.fairphone.software / kernel / msm-4.9 / refs/tags/FP3-REL-Q-3.A.0107 / . / drivers / spi / spi_qsd.h
blob: b18b55e2a143b87ce33fd27da50e7a1e66ea3b4c [file] [log] [blame]
Alok Chauhanf04d9262017-08-01 19:54:01 +0530[diff] [blame]1/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#ifndef _SPI_QSD_H
15#define _SPI_QSD_H
16
17#include <linux/pinctrl/consumer.h>
18#define SPI_DRV_NAME "spi_qsd"
19
20#if IS_ENABLED(CONFIG_SPI_QSD) || IS_ENABLED(CONFIG_SPI_QSD_MODULE)
21
22#define QSD_REG(x) (x)
23#define QUP_REG(x)
24
25#define SPI_FIFO_WORD_CNT 0x0048
26
27#else
28
29#define QSD_REG(x)
30#define QUP_REG(x) (x)
31
32#define QUP_CONFIG 0x0000 /* N & NO_INPUT/NO_OUTPUT bits */
33#define QUP_ERROR_FLAGS_EN 0x030C
34#define QUP_ERR_MASK 0x3
35#define SPI_OUTPUT_FIFO_WORD_CNT 0x010C
36#define SPI_INPUT_FIFO_WORD_CNT 0x0214
37#define QUP_MX_WRITE_COUNT 0x0150
38#define QUP_MX_WRITE_CNT_CURRENT 0x0154
39
40#define QUP_CONFIG_SPI_MODE 0x0100
41#endif
42
43#define GSBI_CTRL_REG 0x0
44#define GSBI_SPI_CONFIG 0x30
45/* B-family only registers */
46#define QUP_HARDWARE_VER 0x0030
47#define QUP_HARDWARE_VER_2_1_1 0X20010001
48#define QUP_OPERATIONAL_MASK 0x0028
49#define QUP_OP_MASK_OUTPUT_SERVICE_FLAG 0x100
50#define QUP_OP_MASK_INPUT_SERVICE_FLAG 0x200
51
52#define QUP_ERROR_FLAGS 0x0308
53
54#define SPI_CONFIG (QSD_REG(0x0000) QUP_REG(0x0300))
55#define SPI_IO_CONTROL (QSD_REG(0x0004) QUP_REG(0x0304))
56#define SPI_IO_MODES (QSD_REG(0x0008) QUP_REG(0x0008))
57#define SPI_SW_RESET (QSD_REG(0x000C) QUP_REG(0x000C))
58#define SPI_TIME_OUT_CURRENT (QSD_REG(0x0014) QUP_REG(0x0014))
59#define SPI_MX_OUTPUT_COUNT (QSD_REG(0x0018) QUP_REG(0x0100))
60#define SPI_MX_OUTPUT_CNT_CURRENT (QSD_REG(0x001C) QUP_REG(0x0104))
61#define SPI_MX_INPUT_COUNT (QSD_REG(0x0020) QUP_REG(0x0200))
62#define SPI_MX_INPUT_CNT_CURRENT (QSD_REG(0x0024) QUP_REG(0x0204))
63#define SPI_MX_READ_COUNT (QSD_REG(0x0028) QUP_REG(0x0208))
64#define SPI_MX_READ_CNT_CURRENT (QSD_REG(0x002C) QUP_REG(0x020C))
65#define SPI_OPERATIONAL (QSD_REG(0x0030) QUP_REG(0x0018))
66#define SPI_ERROR_FLAGS (QSD_REG(0x0034) QUP_REG(0x001C))
67#define SPI_ERROR_FLAGS_EN (QSD_REG(0x0038) QUP_REG(0x0020))
68#define SPI_DEASSERT_WAIT (QSD_REG(0x003C) QUP_REG(0x0310))
69#define SPI_OUTPUT_DEBUG (QSD_REG(0x0040) QUP_REG(0x0108))
70#define SPI_INPUT_DEBUG (QSD_REG(0x0044) QUP_REG(0x0210))
71#define SPI_TEST_CTRL (QSD_REG(0x004C) QUP_REG(0x0024))
72#define SPI_OUTPUT_FIFO (QSD_REG(0x0100) QUP_REG(0x0110))
73#define SPI_INPUT_FIFO (QSD_REG(0x0200) QUP_REG(0x0218))
74#define SPI_STATE (QSD_REG(SPI_OPERATIONAL) QUP_REG(0x0004))
75
76/* QUP_CONFIG fields */
77#define SPI_CFG_N 0x0000001F
78#define SPI_NO_INPUT 0x00000080
79#define SPI_NO_OUTPUT 0x00000040
80#define SPI_EN_EXT_OUT_FLAG 0x00010000
81
82/* SPI_CONFIG fields */
83#define SPI_CFG_LOOPBACK 0x00000100
84#define SPI_CFG_INPUT_FIRST 0x00000200
85#define SPI_CFG_HS_MODE 0x00000400
86
87/* SPI_IO_CONTROL fields */
88#define SPI_IO_C_FORCE_CS 0x00000800
89#define SPI_IO_C_CLK_IDLE_HIGH 0x00000400
90#define SPI_IO_C_MX_CS_MODE 0x00000100
91#define SPI_IO_C_CS_N_POLARITY 0x000000F0
92#define SPI_IO_C_CS_N_POLARITY_0 0x00000010
93#define SPI_IO_C_CS_SELECT 0x0000000C
94#define SPI_IO_C_TRISTATE_CS 0x00000002
95#define SPI_IO_C_NO_TRI_STATE 0x00000001
96
97/* SPI_IO_MODES fields */
98#define SPI_IO_M_OUTPUT_BIT_SHIFT_EN (QSD_REG(0x00004000) QUP_REG(0x00010000))
99#define SPI_IO_M_PACK_EN (QSD_REG(0x00002000) QUP_REG(0x00008000))
100#define SPI_IO_M_UNPACK_EN (QSD_REG(0x00001000) QUP_REG(0x00004000))
101#define SPI_IO_M_INPUT_MODE (QSD_REG(0x00000C00) QUP_REG(0x00003000))
102#define SPI_IO_M_OUTPUT_MODE (QSD_REG(0x00000300) QUP_REG(0x00000C00))
103#define SPI_IO_M_INPUT_FIFO_SIZE (QSD_REG(0x000000C0) QUP_REG(0x00000380))
104#define SPI_IO_M_INPUT_BLOCK_SIZE (QSD_REG(0x00000030) QUP_REG(0x00000060))
105#define SPI_IO_M_OUTPUT_FIFO_SIZE (QSD_REG(0x0000000C) QUP_REG(0x0000001C))
106#define SPI_IO_M_OUTPUT_BLOCK_SIZE (QSD_REG(0x00000003) QUP_REG(0x00000003))
107
108#define INPUT_BLOCK_SZ_SHIFT (QSD_REG(4) QUP_REG(5))
109#define INPUT_FIFO_SZ_SHIFT (QSD_REG(6) QUP_REG(7))
110#define OUTPUT_BLOCK_SZ_SHIFT (QSD_REG(0) QUP_REG(0))
111#define OUTPUT_FIFO_SZ_SHIFT (QSD_REG(2) QUP_REG(2))
112#define OUTPUT_MODE_SHIFT (QSD_REG(8) QUP_REG(10))
113#define INPUT_MODE_SHIFT (QSD_REG(10) QUP_REG(12))
114
115/* SPI_OPERATIONAL fields */
116#define SPI_OP_IN_BLK_RD_REQ_FLAG 0x00002000
117#define SPI_OP_OUT_BLK_WR_REQ_FLAG 0x00001000
118#define SPI_OP_MAX_INPUT_DONE_FLAG 0x00000800
119#define SPI_OP_MAX_OUTPUT_DONE_FLAG 0x00000400
120#define SPI_OP_INPUT_SERVICE_FLAG 0x00000200
121#define SPI_OP_OUTPUT_SERVICE_FLAG 0x00000100
122#define SPI_OP_INPUT_FIFO_FULL 0x00000080
123#define SPI_OP_OUTPUT_FIFO_FULL 0x00000040
124#define SPI_OP_IP_FIFO_NOT_EMPTY 0x00000020
125#define SPI_OP_OP_FIFO_NOT_EMPTY 0x00000010
126#define SPI_OP_STATE_VALID 0x00000004
127#define SPI_OP_STATE 0x00000003
128
129#define SPI_OP_STATE_CLEAR_BITS 0x2
130
131#define SPI_PINCTRL_STATE_DEFAULT "spi_default"
132#define SPI_PINCTRL_STATE_SLEEP "spi_sleep"
133
134enum msm_spi_state {
135 SPI_OP_STATE_RESET = 0x00000000,
136 SPI_OP_STATE_RUN = 0x00000001,
137 SPI_OP_STATE_PAUSE = 0x00000003,
138};
139
140/* SPI_ERROR_FLAGS fields */
141#define SPI_ERR_OUTPUT_OVER_RUN_ERR 0x00000020
142#define SPI_ERR_INPUT_UNDER_RUN_ERR 0x00000010
143#define SPI_ERR_OUTPUT_UNDER_RUN_ERR 0x00000008
144#define SPI_ERR_INPUT_OVER_RUN_ERR 0x00000004
145#define SPI_ERR_CLK_OVER_RUN_ERR 0x00000002
146#define SPI_ERR_CLK_UNDER_RUN_ERR 0x00000001
147
148/* We don't allow transactions larger than 4K-64 or 64K-64 due to
149 * mx_input/output_cnt register size
150 */
151#define SPI_MAX_TRANSFERS (QSD_REG(0xFC0) QUP_REG(0xFC0))
152#define SPI_MAX_LEN (SPI_MAX_TRANSFERS * dd->bytes_per_word)
153
154#define SPI_NUM_CHIPSELECTS 4
155#define SPI_SUPPORTED_MODES (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP)
156
157/* high speed mode is when bus rate is greater then 26MHz */
158#define SPI_HS_MIN_RATE (26000000)
159
160#define SPI_DELAY_THRESHOLD 1
161/* Default timeout is 10 milliseconds */
162#define SPI_DEFAULT_TIMEOUT 10
163/* 250 microseconds */
164#define SPI_TRYLOCK_DELAY 250
165
166/* Data Mover burst size */
167#define DM_BURST_SIZE 16
168/* Data Mover commands should be aligned to 64 bit(8 bytes) */
169#define DM_BYTE_ALIGN 8
170
171#if defined(CONFIG_ARM64) || defined(CONFIG_LPAE)
172#define spi_dma_mask(dev) (dma_set_mask((dev), DMA_BIT_MASK(36)))
173#else
174#define spi_dma_mask(dev) (dma_set_mask((dev), DMA_BIT_MASK(32)))
175#endif
176
177
178enum msm_spi_qup_version {
179 SPI_QUP_VERSION_NONE = 0x0,
180 SPI_QUP_VERSION_BFAM = 0x2,
181};
182
183enum msm_spi_pipe_direction {
184 SPI_BAM_CONSUMER_PIPE = 0x0,
185 SPI_BAM_PRODUCER_PIPE = 0x1,
186};
187
188#define SPI_BAM_MAX_DESC_NUM 32
189#define SPI_MAX_TRFR_BTWN_RESETS ((64 * 1024) - 16) /* 64KB - 16byte */
190
191enum msm_spi_clk_path_vec_idx {
192 MSM_SPI_CLK_PATH_SUSPEND_VEC = 0,
193 MSM_SPI_CLK_PATH_RESUME_VEC = 1,
194};
195#define MSM_SPI_CLK_PATH_AVRG_BW(dd) (76800000)
196#define MSM_SPI_CLK_PATH_BRST_BW(dd) (76800000)
197
198static char const * const spi_rsrcs[] = {
199 "spi_clk",
200 "spi_miso",
201 "spi_mosi"
202};
203
204static char const * const spi_cs_rsrcs[] = {
205 "spi_cs",
206 "spi_cs1",
207 "spi_cs2",
208 "spi_cs3",
209};
210
211enum msm_spi_mode {
212 SPI_FIFO_MODE = 0x0, /* 00 */
213 SPI_BLOCK_MODE = 0x1, /* 01 */
214 SPI_BAM_MODE = 0x3, /* 11 */
215 SPI_MODE_NONE = 0xFF, /* invalid value */
216};
217
218/* Structure for SPI CS GPIOs */
219struct spi_cs_gpio {
220 int gpio_num;
221 bool valid;
222};
223
224#ifdef CONFIG_DEBUG_FS
225struct msm_spi_debugfs_data {
226 int offset;
227 struct msm_spi *dd;
228};
229/* Used to create debugfs entries */
230static struct msm_spi_regs{
231 const char *name;
232 mode_t mode;
233 int offset;
234} debugfs_spi_regs[] = {
235 {"config", 0644, SPI_CONFIG },
236 {"io_control", 0644, SPI_IO_CONTROL },
237 {"io_modes", 0644, SPI_IO_MODES },
238 {"sw_reset", 0200, SPI_SW_RESET },
239 {"time_out_current", 0444, SPI_TIME_OUT_CURRENT },
240 {"mx_output_count", 0644, SPI_MX_OUTPUT_COUNT },
241 {"mx_output_cnt_current", 0444, SPI_MX_OUTPUT_CNT_CURRENT },
242 {"mx_input_count", 0644, SPI_MX_INPUT_COUNT },
243 {"mx_input_cnt_current", 0444, SPI_MX_INPUT_CNT_CURRENT },
244 {"mx_read_count", 0644, SPI_MX_READ_COUNT },
245 {"mx_read_cnt_current", 0444, SPI_MX_READ_CNT_CURRENT },
246 {"operational", 0644, SPI_OPERATIONAL },
247 {"error_flags", 0644, SPI_ERROR_FLAGS },
248 {"error_flags_en", 0644, SPI_ERROR_FLAGS_EN },
249 {"deassert_wait", 0644, SPI_DEASSERT_WAIT },
250 {"output_debug", 0444, SPI_OUTPUT_DEBUG },
251 {"input_debug", 0444, SPI_INPUT_DEBUG },
252 {"test_ctrl", 0644, SPI_TEST_CTRL },
253 {"output_fifo", 0200, SPI_OUTPUT_FIFO },
254 {"input_fifo", 0400, SPI_INPUT_FIFO },
255 {"spi_state", 0644, SPI_STATE },
256#if IS_ENABLED(CONFIG_SPI_QSD) || IS_ENABLED(CONFIG_SPI_QSD_MODULE)
257 {"fifo_word_cnt", 0444, SPI_FIFO_WORD_CNT},
258#else
259 {"qup_config", 0644, QUP_CONFIG},
260 {"qup_error_flags", 0644, QUP_ERROR_FLAGS},
261 {"qup_error_flags_en", 0644, QUP_ERROR_FLAGS_EN},
262 {"mx_write_cnt", 0644, QUP_MX_WRITE_COUNT},
263 {"mx_write_cnt_current", 0444, QUP_MX_WRITE_CNT_CURRENT},
264 {"output_fifo_word_cnt", 0444, SPI_OUTPUT_FIFO_WORD_CNT},
265 {"input_fifo_word_cnt", 0444, SPI_INPUT_FIFO_WORD_CNT},
266#endif
267};
268#endif
269
270struct msm_spi_bam_pipe {
271 const char *name;
272 struct sps_pipe *handle;
273 struct sps_connect config;
274 bool teardown_required;
275};
276
277struct msm_spi_bam {
278 void __iomem *base;
279 phys_addr_t phys_addr;
280 uintptr_t handle;
281 int irq;
282 struct msm_spi_bam_pipe prod;
283 struct msm_spi_bam_pipe cons;
284 bool deregister_required;
285 u32 curr_rx_bytes_recvd;
286 u32 curr_tx_bytes_sent;
287 u32 bam_rx_len;
288 u32 bam_tx_len;
289};
290
291struct msm_spi {
292 u8 *read_buf;
293 const u8 *write_buf;
294 void __iomem *base;
295 struct device *dev;
296 spinlock_t queue_lock;
297 struct mutex core_lock;
298 struct spi_device *spi;
299 struct spi_transfer *cur_transfer;
300 struct completion tx_transfer_complete;
301 struct completion rx_transfer_complete;
302 struct clk *clk; /* core clock */
303 struct clk *pclk; /* interface clock */
304 struct msm_bus_client_handle *bus_cl_hdl;
305 unsigned long mem_phys_addr;
306 size_t mem_size;
307 int input_fifo_size;
308 int output_fifo_size;
309 u32 rx_bytes_remaining;
310 u32 tx_bytes_remaining;
311 u32 clock_speed;
312 int irq_in;
313 int read_xfr_cnt;
314 int write_xfr_cnt;
315 int write_len;
316 int read_len;
317#if IS_ENABLED(CONFIG_SPI_QSD) || IS_ENABLED(CONFIG_SPI_QSD_MODULE)
318 int irq_out;
319 int irq_err;
320#endif
321 int bytes_per_word;
322 bool suspended;
323 bool transfer_pending;
324 wait_queue_head_t continue_suspend;
325 /* DMA data */
326 enum msm_spi_mode tx_mode;
327 enum msm_spi_mode rx_mode;
328 bool use_dma;
329 int tx_dma_chan;
330 int tx_dma_crci;
331 int rx_dma_chan;
332 int rx_dma_crci;
333 int (*dma_init)(struct msm_spi *dd);
334 void (*dma_teardown)(struct msm_spi *dd);
335 struct msm_spi_bam bam;
336 int input_block_size;
337 int output_block_size;
338 int input_burst_size;
339 int output_burst_size;
340 atomic_t rx_irq_called;
341 atomic_t tx_irq_called;
342 /* Used to pad messages unaligned to block size */
343 u8 *tx_padding;
344 dma_addr_t tx_padding_dma;
345 u8 *rx_padding;
346 dma_addr_t rx_padding_dma;
347 u32 tx_unaligned_len;
348 u32 rx_unaligned_len;
349 /* DMA statistics */
350 int stat_rx;
351 int stat_tx;
352#ifdef CONFIG_DEBUG_FS
353 struct dentry *dent_spi;
354 struct dentry *debugfs_spi_regs[ARRAY_SIZE(debugfs_spi_regs)];
355 struct msm_spi_debugfs_data reg_data[ARRAY_SIZE(debugfs_spi_regs)];
356#endif
357 struct msm_spi_platform_data *pdata; /* Platform data */
358 /* When set indicates multiple transfers in a single message */
359 bool rx_done;
360 bool tx_done;
361 u32 cur_msg_len;
362 /* Used in FIFO mode to keep track of the transfer being processed */
363 struct spi_transfer *cur_tx_transfer;
364 struct spi_transfer *cur_rx_transfer;
365 /* Temporary buffer used for WR-WR or WR-RD transfers */
366 u8 *temp_buf;
367 /* GPIO pin numbers for SPI clk, miso and mosi */
368 int spi_gpios[ARRAY_SIZE(spi_rsrcs)];
369 /* SPI CS GPIOs for each slave */
370 struct spi_cs_gpio cs_gpios[ARRAY_SIZE(spi_cs_rsrcs)];
371 enum msm_spi_qup_version qup_ver;
372 int max_trfr_len;
373 u16 xfrs_delay_usec;
374 struct pinctrl *pinctrl;
375 struct pinctrl_state *pins_active;
376 struct pinctrl_state *pins_sleep;
377 bool is_init_complete;
378 bool pack_words;
379};
380
381/* Forward declaration */
382static irqreturn_t msm_spi_input_irq(int irq, void *dev_id);
383static irqreturn_t msm_spi_output_irq(int irq, void *dev_id);
384static irqreturn_t msm_spi_error_irq(int irq, void *dev_id);
385static inline int msm_spi_set_state(struct msm_spi *dd,
386 enum msm_spi_state state);
387static void msm_spi_write_word_to_fifo(struct msm_spi *dd);
388static inline void msm_spi_write_rmn_to_fifo(struct msm_spi *dd);
389static irqreturn_t msm_spi_qup_irq(int irq, void *dev_id);
390
391#if IS_ENABLED(CONFIG_SPI_QSD) || IS_ENABLED(CONFIG_SPI_QSD_MODULE)
392static inline void msm_spi_disable_irqs(struct msm_spi *dd)
393{
394 disable_irq(dd->irq_in);
395 disable_irq(dd->irq_out);
396 disable_irq(dd->irq_err);
397}
398
399static inline void msm_spi_enable_irqs(struct msm_spi *dd)
400{
401 enable_irq(dd->irq_in);
402 enable_irq(dd->irq_out);
403 enable_irq(dd->irq_err);
404}
405
406static inline int msm_spi_request_irq(struct msm_spi *dd,
407 struct platform_device *pdev,
408 struct spi_master *master)
409{
410 int rc;
411
412 dd->irq_in = platform_get_irq(pdev, 0);
413 dd->irq_out = platform_get_irq(pdev, 1);
414 dd->irq_err = platform_get_irq(pdev, 2);
415 if ((dd->irq_in < 0) || (dd->irq_out < 0) || (dd->irq_err < 0))
416 return -EINVAL;
417
418 rc = devm_request_irq(dd->dev, dd->irq_in, msm_spi_input_irq,
419 IRQF_TRIGGER_RISING, pdev->name, dd);
420 if (rc)
421 goto error_irq;
422
423 rc = devm_request_irq(dd->dev, dd->irq_out, msm_spi_output_irq,
424 IRQF_TRIGGER_RISING, pdev->name, dd);
425 if (rc)
426 goto error_irq;
427
428 rc = devm_request_irq(dd->dev, dd->irq_err, msm_spi_error_irq,
429 IRQF_TRIGGER_RISING, pdev->name, master);
430 if (rc)
431 goto error_irq;
432
433error_irq:
434 return rc;
435}
436
437static inline void msm_spi_get_clk_err(struct msm_spi *dd, u32 *spi_err) {}
438static inline void msm_spi_ack_clk_err(struct msm_spi *dd) {}
439static inline void msm_spi_set_qup_config(struct msm_spi *dd, int bpw) {}
440
441static inline int msm_spi_prepare_for_write(struct msm_spi *dd) { return 0; }
442static inline void msm_spi_start_write(struct msm_spi *dd, u32 read_count)
443{
444 msm_spi_write_word_to_fifo(dd);
445}
446static inline void msm_spi_set_write_count(struct msm_spi *dd, int val) {}
447
448static inline void msm_spi_complete(struct msm_spi *dd)
449{
450 complete(&dd->transfer_complete);
451}
452
453static inline void msm_spi_enable_error_flags(struct msm_spi *dd)
454{
455 writel_relaxed(0x0000007B, dd->base + SPI_ERROR_FLAGS_EN);
456}
457
458static inline void msm_spi_clear_error_flags(struct msm_spi *dd)
459{
460 writel_relaxed(0x0000007F, dd->base + SPI_ERROR_FLAGS);
461}
462
463#else
464/* In QUP the same interrupt line is used for input, output and error*/
465static inline int msm_spi_request_irq(struct msm_spi *dd,
466 struct platform_device *pdev,
467 struct spi_master *master)
468{
469 dd->irq_in = platform_get_irq(pdev, 0);
470 if (dd->irq_in < 0)
471 return -EINVAL;
472
473 return devm_request_irq(dd->dev, dd->irq_in, msm_spi_qup_irq,
474 IRQF_TRIGGER_HIGH, pdev->name, dd);
475}
476
477static inline void msm_spi_disable_irqs(struct msm_spi *dd)
478{
479 disable_irq(dd->irq_in);
480}
481
482static inline void msm_spi_enable_irqs(struct msm_spi *dd)
483{
484 enable_irq(dd->irq_in);
485}
486
487static inline void msm_spi_get_clk_err(struct msm_spi *dd, u32 *spi_err)
488{
489 *spi_err = readl_relaxed(dd->base + QUP_ERROR_FLAGS);
490}
491
492static inline void msm_spi_ack_clk_err(struct msm_spi *dd)
493{
494 writel_relaxed(QUP_ERR_MASK, dd->base + QUP_ERROR_FLAGS);
495}
496
497static inline void
498msm_spi_set_bpw_and_no_io_flags(struct msm_spi *dd, u32 *config, int n);
499
500/**
501 * msm_spi_set_qup_config: set QUP_CONFIG to no_input, no_output, and N bits
502 */
503static inline void msm_spi_set_qup_config(struct msm_spi *dd, int bpw)
504{
505 u32 qup_config = readl_relaxed(dd->base + QUP_CONFIG);
506
507 msm_spi_set_bpw_and_no_io_flags(dd, &qup_config, bpw-1);
508 writel_relaxed(qup_config | QUP_CONFIG_SPI_MODE, dd->base + QUP_CONFIG);
509}
510
511static inline int msm_spi_prepare_for_write(struct msm_spi *dd)
512{
513 if (msm_spi_set_state(dd, SPI_OP_STATE_RUN))
514 return -EINVAL;
515 if (msm_spi_set_state(dd, SPI_OP_STATE_PAUSE))
516 return -EINVAL;
517 return 0;
518}
519
520static inline void msm_spi_start_write(struct msm_spi *dd, u32 read_count)
521{
522 msm_spi_write_rmn_to_fifo(dd);
523}
524
525static inline void msm_spi_set_write_count(struct msm_spi *dd, int val)
526{
527 writel_relaxed(val, dd->base + QUP_MX_WRITE_COUNT);
528}
529
530static inline void msm_spi_complete(struct msm_spi *dd)
531{
532 dd->tx_done = true;
533 dd->rx_done = true;
534}
535
536static inline void msm_spi_enable_error_flags(struct msm_spi *dd)
537{
538 if (dd->qup_ver == SPI_QUP_VERSION_BFAM)
539 writel_relaxed(
540 SPI_ERR_CLK_UNDER_RUN_ERR | SPI_ERR_CLK_OVER_RUN_ERR,
541 dd->base + SPI_ERROR_FLAGS_EN);
542 else
543 writel_relaxed(0x00000078, dd->base + SPI_ERROR_FLAGS_EN);
544}
545
546static inline void msm_spi_clear_error_flags(struct msm_spi *dd)
547{
548 if (dd->qup_ver == SPI_QUP_VERSION_BFAM)
549 writel_relaxed(
550 SPI_ERR_CLK_UNDER_RUN_ERR | SPI_ERR_CLK_OVER_RUN_ERR,
551 dd->base + SPI_ERROR_FLAGS);
552 else
553 writel_relaxed(0x0000007C, dd->base + SPI_ERROR_FLAGS);
554}
555
556#endif
557#endif