blob: 44c906097530a76b6d1a52e267b44221557db0fe [file] [log] [blame]
Ali Bahar0e54f602011-08-23 13:53:37 +08001/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
Ali Baharb4f62092011-08-23 13:53:38 +080018 * Modifications for inclusion into the Linux staging tree are
19 * Copyright(c) 2010 Larry Finger. All rights reserved.
20 *
21 * Contact information:
22 * WLAN FAE <wlanfae@realtek.com>
23 * Larry Finger <Larry.Finger@lwfinger.net>
Ali Bahar0e54f602011-08-23 13:53:37 +080024 *
25 ******************************************************************************/
Larry Finger2865d422010-08-20 10:15:30 -050026#ifndef __RTL8712_GP_BITDEF_H__
27#define __RTL8712_GP_BITDEF_H__
28
29/*GPIO_CTRL*/
30#define _GPIO_MOD_MSK 0xFF000000
31#define _GPIO_MOD_SHT 24
32#define _GPIO_IO_SEL_MSK 0x00FF0000
33#define _GPIO_IO_SEL_SHT 16
34#define _GPIO_OUT_MSK 0x0000FF00
35#define _GPIO_OUT_SHT 8
36#define _GPIO_IN_MSK 0x000000FF
37#define _GPIO_IN_SHT 0
38
39/*SYS_PINMUX_CFG*/
40#define _GPIOSEL_MSK 0x0003
41#define _GPIOSEL_SHT 0
42
43/*LED_CFG*/
44#define _LED1SV BIT(7)
45#define _LED1CM_MSK 0x0070
46#define _LED1CM_SHT 4
47#define _LED0SV BIT(3)
48#define _LED0CM_MSK 0x0007
49#define _LED0CM_SHT 0
50
51/*PHY_REG*/
52#define _HST_RDRDY_SHT 0
53#define _HST_RDRDY_MSK 0xFF
54#define _HST_RDRDY BIT(_HST_RDRDY_SHT)
55#define _CPU_WTBUSY_SHT 1
56#define _CPU_WTBUSY_MSK 0xFF
57#define _CPU_WTBUSY BIT(_CPU_WTBUSY_SHT)
58
59/* 11. General Purpose Registers (Offset: 0x02E0 - 0x02FF)*/
60
61/* 8192S GPIO Config Setting (offset 0x2F1, 1 byte)*/
62
63/*----------------------------------------------------------------------------*/
64
65#define GPIOMUX_EN BIT(3) /* When this bit is set to "1",
66 * GPIO PINs will switch to MAC
Punit Vara3d228d82015-10-08 01:25:22 +053067 * GPIO Function
68 */
Larry Finger2865d422010-08-20 10:15:30 -050069#define GPIOSEL_GPIO 0 /* UART or JTAG or pure GPIO*/
70#define GPIOSEL_PHYDBG 1 /* PHYDBG*/
71#define GPIOSEL_BT 2 /* BT_coex*/
72#define GPIOSEL_WLANDBG 3 /* WLANDBG*/
73#define GPIOSEL_GPIO_MASK (~(BIT(0)|BIT(1)))
Justin P. Mattockbe10ac22012-05-07 07:38:22 -070074/* HW Radio OFF switch (GPIO BIT) */
Larry Finger2865d422010-08-20 10:15:30 -050075#define HAL_8192S_HW_GPIO_OFF_BIT BIT(3)
76#define HAL_8192S_HW_GPIO_OFF_MASK 0xF7
77#define HAL_8192S_HW_GPIO_WPS_BIT BIT(4)
78
79#endif /*__RTL8712_GP_BITDEF_H__*/
80