Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | * Copyright 2008 Luotao Fu, kernel@pengutronix.de |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License |
| 7 | * as published by the Free Software Foundation; either version 2 |
| 8 | * of the License, or (at your option) any later version. |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 13 | */ |
| 14 | |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 15 | #include <linux/clk.h> |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/io.h> |
Alexander Shiyan | b0dceb6 | 2014-05-08 11:56:38 +0400 | [diff] [blame] | 18 | #include <linux/jiffies.h> |
Alexander Shiyan | 18fd9e359 | 2014-02-22 11:29:50 +0400 | [diff] [blame] | 19 | #include <linux/module.h> |
| 20 | #include <linux/platform_device.h> |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 21 | |
| 22 | #include "../w1.h" |
| 23 | #include "../w1_int.h" |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 24 | |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 25 | /* |
| 26 | * MXC W1 Register offsets |
| 27 | */ |
Alexander Shiyan | 18fd9e359 | 2014-02-22 11:29:50 +0400 | [diff] [blame] | 28 | #define MXC_W1_CONTROL 0x00 |
| 29 | # define MXC_W1_CONTROL_RDST BIT(3) |
| 30 | # define MXC_W1_CONTROL_WR(x) BIT(5 - (x)) |
| 31 | # define MXC_W1_CONTROL_PST BIT(6) |
| 32 | # define MXC_W1_CONTROL_RPP BIT(7) |
| 33 | #define MXC_W1_TIME_DIVIDER 0x02 |
| 34 | #define MXC_W1_RESET 0x04 |
Alexander Shiyan | b7ce0b5 | 2014-05-08 11:56:39 +0400 | [diff] [blame] | 35 | # define MXC_W1_RESET_RST BIT(0) |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 36 | |
| 37 | struct mxc_w1_device { |
| 38 | void __iomem *regs; |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 39 | struct clk *clk; |
| 40 | struct w1_bus_master bus_master; |
| 41 | }; |
| 42 | |
| 43 | /* |
| 44 | * this is the low level routine to |
| 45 | * reset the device on the One Wire interface |
| 46 | * on the hardware |
| 47 | */ |
| 48 | static u8 mxc_w1_ds2_reset_bus(void *data) |
| 49 | { |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 50 | struct mxc_w1_device *dev = data; |
Alexander Shiyan | b0dceb6 | 2014-05-08 11:56:38 +0400 | [diff] [blame] | 51 | unsigned long timeout; |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 52 | |
Alexander Shiyan | b0dceb6 | 2014-05-08 11:56:38 +0400 | [diff] [blame] | 53 | writeb(MXC_W1_CONTROL_RPP, dev->regs + MXC_W1_CONTROL); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 54 | |
Alexander Shiyan | b0dceb6 | 2014-05-08 11:56:38 +0400 | [diff] [blame] | 55 | /* Wait for reset sequence 511+512us, use 1500us for sure */ |
| 56 | timeout = jiffies + usecs_to_jiffies(1500); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 57 | |
Alexander Shiyan | b0dceb6 | 2014-05-08 11:56:38 +0400 | [diff] [blame] | 58 | udelay(511 + 512); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 59 | |
Alexander Shiyan | b0dceb6 | 2014-05-08 11:56:38 +0400 | [diff] [blame] | 60 | do { |
| 61 | u8 ctrl = readb(dev->regs + MXC_W1_CONTROL); |
| 62 | |
| 63 | /* PST bit is valid after the RPP bit is self-cleared */ |
| 64 | if (!(ctrl & MXC_W1_CONTROL_RPP)) |
| 65 | return !(ctrl & MXC_W1_CONTROL_PST); |
| 66 | } while (time_is_after_jiffies(timeout)); |
| 67 | |
| 68 | return 1; |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 69 | } |
| 70 | |
| 71 | /* |
| 72 | * this is the low level routine to read/write a bit on the One Wire |
| 73 | * interface on the hardware. It does write 0 if parameter bit is set |
| 74 | * to 0, otherwise a write 1/read. |
| 75 | */ |
| 76 | static u8 mxc_w1_ds2_touch_bit(void *data, u8 bit) |
| 77 | { |
Alexander Shiyan | f80b258 | 2014-05-08 11:56:40 +0400 | [diff] [blame] | 78 | struct mxc_w1_device *dev = data; |
| 79 | unsigned long timeout; |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 80 | |
Alexander Shiyan | f80b258 | 2014-05-08 11:56:40 +0400 | [diff] [blame] | 81 | writeb(MXC_W1_CONTROL_WR(bit), dev->regs + MXC_W1_CONTROL); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 82 | |
Alexander Shiyan | f80b258 | 2014-05-08 11:56:40 +0400 | [diff] [blame] | 83 | /* Wait for read/write bit (60us, Max 120us), use 200us for sure */ |
| 84 | timeout = jiffies + usecs_to_jiffies(200); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 85 | |
Alexander Shiyan | f80b258 | 2014-05-08 11:56:40 +0400 | [diff] [blame] | 86 | udelay(60); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 87 | |
Alexander Shiyan | f80b258 | 2014-05-08 11:56:40 +0400 | [diff] [blame] | 88 | do { |
| 89 | u8 ctrl = readb(dev->regs + MXC_W1_CONTROL); |
| 90 | |
| 91 | /* RDST bit is valid after the WR1/RD bit is self-cleared */ |
| 92 | if (!(ctrl & MXC_W1_CONTROL_WR(bit))) |
| 93 | return !!(ctrl & MXC_W1_CONTROL_RDST); |
| 94 | } while (time_is_after_jiffies(timeout)); |
| 95 | |
| 96 | return 0; |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 97 | } |
| 98 | |
Bill Pemberton | 479e2bc | 2012-11-19 13:21:43 -0500 | [diff] [blame] | 99 | static int mxc_w1_probe(struct platform_device *pdev) |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 100 | { |
| 101 | struct mxc_w1_device *mdev; |
Alexander Shiyan | 71531f5 | 2013-11-29 15:39:29 +0400 | [diff] [blame] | 102 | unsigned long clkrate; |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 103 | struct resource *res; |
Alexander Shiyan | a082263 | 2013-11-29 15:39:28 +0400 | [diff] [blame] | 104 | unsigned int clkdiv; |
Alexander Shiyan | 001d195 | 2013-11-29 15:39:30 +0400 | [diff] [blame] | 105 | int err; |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 106 | |
Julia Lawall | e5279ff | 2012-12-07 00:15:24 +0100 | [diff] [blame] | 107 | mdev = devm_kzalloc(&pdev->dev, sizeof(struct mxc_w1_device), |
| 108 | GFP_KERNEL); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 109 | if (!mdev) |
| 110 | return -ENOMEM; |
| 111 | |
Julia Lawall | e5279ff | 2012-12-07 00:15:24 +0100 | [diff] [blame] | 112 | mdev->clk = devm_clk_get(&pdev->dev, NULL); |
| 113 | if (IS_ERR(mdev->clk)) |
| 114 | return PTR_ERR(mdev->clk); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 115 | |
Stefan Potyra | aec3dd5 | 2018-05-02 10:55:31 +0200 | [diff] [blame] | 116 | err = clk_prepare_enable(mdev->clk); |
| 117 | if (err) |
| 118 | return err; |
| 119 | |
Alexander Shiyan | 71531f5 | 2013-11-29 15:39:29 +0400 | [diff] [blame] | 120 | clkrate = clk_get_rate(mdev->clk); |
| 121 | if (clkrate < 10000000) |
| 122 | dev_warn(&pdev->dev, |
| 123 | "Low clock frequency causes improper function\n"); |
| 124 | |
| 125 | clkdiv = DIV_ROUND_CLOSEST(clkrate, 1000000); |
| 126 | clkrate /= clkdiv; |
| 127 | if ((clkrate < 980000) || (clkrate > 1020000)) |
| 128 | dev_warn(&pdev->dev, |
| 129 | "Incorrect time base frequency %lu Hz\n", clkrate); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 130 | |
Julia Lawall | e5279ff | 2012-12-07 00:15:24 +0100 | [diff] [blame] | 131 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Fabio Estevam | 388f7bd | 2013-03-11 20:18:15 -0300 | [diff] [blame] | 132 | mdev->regs = devm_ioremap_resource(&pdev->dev, res); |
Stefan Potyra | aec3dd5 | 2018-05-02 10:55:31 +0200 | [diff] [blame] | 133 | if (IS_ERR(mdev->regs)) { |
| 134 | err = PTR_ERR(mdev->regs); |
| 135 | goto out_disable_clk; |
| 136 | } |
Alexander Shiyan | 001d195 | 2013-11-29 15:39:30 +0400 | [diff] [blame] | 137 | |
Alexander Shiyan | b7ce0b5 | 2014-05-08 11:56:39 +0400 | [diff] [blame] | 138 | /* Software reset 1-Wire module */ |
| 139 | writeb(MXC_W1_RESET_RST, mdev->regs + MXC_W1_RESET); |
| 140 | writeb(0, mdev->regs + MXC_W1_RESET); |
| 141 | |
Alexander Shiyan | fc945d6 | 2014-02-22 11:29:51 +0400 | [diff] [blame] | 142 | writeb(clkdiv - 1, mdev->regs + MXC_W1_TIME_DIVIDER); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 143 | |
| 144 | mdev->bus_master.data = mdev; |
| 145 | mdev->bus_master.reset_bus = mxc_w1_ds2_reset_bus; |
| 146 | mdev->bus_master.touch_bit = mxc_w1_ds2_touch_bit; |
| 147 | |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 148 | platform_set_drvdata(pdev, mdev); |
Alexander Shiyan | 001d195 | 2013-11-29 15:39:30 +0400 | [diff] [blame] | 149 | |
| 150 | err = w1_add_master_device(&mdev->bus_master); |
| 151 | if (err) |
Stefan Potyra | aec3dd5 | 2018-05-02 10:55:31 +0200 | [diff] [blame] | 152 | goto out_disable_clk; |
Alexander Shiyan | 001d195 | 2013-11-29 15:39:30 +0400 | [diff] [blame] | 153 | |
Stefan Potyra | aec3dd5 | 2018-05-02 10:55:31 +0200 | [diff] [blame] | 154 | return 0; |
| 155 | |
| 156 | out_disable_clk: |
| 157 | clk_disable_unprepare(mdev->clk); |
Alexander Shiyan | 001d195 | 2013-11-29 15:39:30 +0400 | [diff] [blame] | 158 | return err; |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 159 | } |
| 160 | |
| 161 | /* |
| 162 | * disassociate the w1 device from the driver |
| 163 | */ |
Bill Pemberton | 82849a9 | 2012-11-19 13:26:23 -0500 | [diff] [blame] | 164 | static int mxc_w1_remove(struct platform_device *pdev) |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 165 | { |
| 166 | struct mxc_w1_device *mdev = platform_get_drvdata(pdev); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 167 | |
| 168 | w1_remove_master_device(&mdev->bus_master); |
| 169 | |
Sascha Hauer | 60178b6 | 2012-03-07 20:59:36 +0100 | [diff] [blame] | 170 | clk_disable_unprepare(mdev->clk); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 171 | |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 172 | return 0; |
| 173 | } |
| 174 | |
Fabian Frederick | 0a56c0e | 2015-03-16 20:20:29 +0100 | [diff] [blame] | 175 | static const struct of_device_id mxc_w1_dt_ids[] = { |
Martin Fuzzey | 28c55dc | 2013-01-29 16:46:10 +0100 | [diff] [blame] | 176 | { .compatible = "fsl,imx21-owire" }, |
| 177 | { /* sentinel */ } |
| 178 | }; |
| 179 | MODULE_DEVICE_TABLE(of, mxc_w1_dt_ids); |
| 180 | |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 181 | static struct platform_driver mxc_w1_driver = { |
| 182 | .driver = { |
Martin Fuzzey | 28c55dc | 2013-01-29 16:46:10 +0100 | [diff] [blame] | 183 | .name = "mxc_w1", |
| 184 | .of_match_table = mxc_w1_dt_ids, |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 185 | }, |
| 186 | .probe = mxc_w1_probe, |
Greg Kroah-Hartman | 10532fe | 2012-12-21 12:55:26 -0800 | [diff] [blame] | 187 | .remove = mxc_w1_remove, |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 188 | }; |
Fabio Estevam | fd21bfc | 2012-11-19 10:19:48 -0200 | [diff] [blame] | 189 | module_platform_driver(mxc_w1_driver); |
Sascha Hauer | a5fd913 | 2009-01-07 18:08:58 -0800 | [diff] [blame] | 190 | |
| 191 | MODULE_LICENSE("GPL"); |
| 192 | MODULE_AUTHOR("Freescale Semiconductors Inc"); |
| 193 | MODULE_DESCRIPTION("Driver for One-Wire on MXC"); |