| Sergei Shtylyov | de0fae6 | 2016-06-12 23:53:04 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2016 Cogent Embedded, Inc. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | */ |
| 9 | |
| 10 | #ifndef __DT_BINDINGS_CLOCK_R8A7792_H__ |
| 11 | #define __DT_BINDINGS_CLOCK_R8A7792_H__ |
| 12 | |
| 13 | /* CPG */ |
| 14 | #define R8A7792_CLK_MAIN 0 |
| 15 | #define R8A7792_CLK_PLL0 1 |
| 16 | #define R8A7792_CLK_PLL1 2 |
| 17 | #define R8A7792_CLK_PLL3 3 |
| 18 | #define R8A7792_CLK_LB 4 |
| 19 | #define R8A7792_CLK_QSPI 5 |
| 20 | #define R8A7792_CLK_Z 6 |
| Sergei Shtylyov | de0fae6 | 2016-06-12 23:53:04 +0300 | [diff] [blame] | 21 | |
| 22 | /* MSTP0 */ |
| 23 | #define R8A7792_CLK_MSIOF0 0 |
| 24 | |
| 25 | /* MSTP1 */ |
| Sergei Shtylyov | eebc8e2 | 2016-06-17 01:02:48 +0300 | [diff] [blame] | 26 | #define R8A7792_CLK_JPU 6 |
| Sergei Shtylyov | de0fae6 | 2016-06-12 23:53:04 +0300 | [diff] [blame] | 27 | #define R8A7792_CLK_TMU1 11 |
| 28 | #define R8A7792_CLK_TMU3 21 |
| 29 | #define R8A7792_CLK_TMU2 22 |
| 30 | #define R8A7792_CLK_CMT0 24 |
| 31 | #define R8A7792_CLK_TMU0 25 |
| 32 | #define R8A7792_CLK_VSP1DU1 27 |
| 33 | #define R8A7792_CLK_VSP1DU0 28 |
| 34 | #define R8A7792_CLK_VSP1_SY 31 |
| 35 | |
| 36 | /* MSTP2 */ |
| 37 | #define R8A7792_CLK_MSIOF1 8 |
| 38 | #define R8A7792_CLK_SYS_DMAC1 18 |
| 39 | #define R8A7792_CLK_SYS_DMAC0 19 |
| 40 | |
| 41 | /* MSTP3 */ |
| 42 | #define R8A7792_CLK_TPU0 4 |
| 43 | #define R8A7792_CLK_SDHI0 14 |
| 44 | #define R8A7792_CLK_CMT1 29 |
| 45 | |
| 46 | /* MSTP4 */ |
| 47 | #define R8A7792_CLK_IRQC 7 |
| 48 | |
| 49 | /* MSTP5 */ |
| 50 | #define R8A7792_CLK_AUDIO_DMAC0 2 |
| 51 | #define R8A7792_CLK_THERMAL 22 |
| 52 | #define R8A7792_CLK_PWM 23 |
| 53 | |
| 54 | /* MSTP7 */ |
| 55 | #define R8A7792_CLK_HSCIF1 16 |
| 56 | #define R8A7792_CLK_HSCIF0 17 |
| 57 | #define R8A7792_CLK_SCIF3 18 |
| 58 | #define R8A7792_CLK_SCIF2 19 |
| 59 | #define R8A7792_CLK_SCIF1 20 |
| 60 | #define R8A7792_CLK_SCIF0 21 |
| 61 | #define R8A7792_CLK_DU1 23 |
| 62 | #define R8A7792_CLK_DU0 24 |
| 63 | |
| 64 | /* MSTP8 */ |
| 65 | #define R8A7792_CLK_VIN5 4 |
| 66 | #define R8A7792_CLK_VIN4 5 |
| 67 | #define R8A7792_CLK_VIN3 8 |
| 68 | #define R8A7792_CLK_VIN2 9 |
| 69 | #define R8A7792_CLK_VIN1 10 |
| 70 | #define R8A7792_CLK_VIN0 11 |
| 71 | #define R8A7792_CLK_ETHERAVB 12 |
| 72 | |
| 73 | /* MSTP9 */ |
| 74 | #define R8A7792_CLK_GPIO7 4 |
| 75 | #define R8A7792_CLK_GPIO6 5 |
| 76 | #define R8A7792_CLK_GPIO5 7 |
| 77 | #define R8A7792_CLK_GPIO4 8 |
| 78 | #define R8A7792_CLK_GPIO3 9 |
| 79 | #define R8A7792_CLK_GPIO2 10 |
| 80 | #define R8A7792_CLK_GPIO1 11 |
| 81 | #define R8A7792_CLK_GPIO0 12 |
| 82 | #define R8A7792_CLK_GPIO11 13 |
| 83 | #define R8A7792_CLK_GPIO10 14 |
| 84 | #define R8A7792_CLK_CAN1 15 |
| 85 | #define R8A7792_CLK_CAN0 16 |
| 86 | #define R8A7792_CLK_QSPI_MOD 17 |
| 87 | #define R8A7792_CLK_GPIO9 19 |
| 88 | #define R8A7792_CLK_GPIO8 21 |
| 89 | #define R8A7792_CLK_I2C5 25 |
| 90 | #define R8A7792_CLK_IICDVFS 26 |
| 91 | #define R8A7792_CLK_I2C4 27 |
| 92 | #define R8A7792_CLK_I2C3 28 |
| 93 | #define R8A7792_CLK_I2C2 29 |
| 94 | #define R8A7792_CLK_I2C1 30 |
| 95 | #define R8A7792_CLK_I2C0 31 |
| 96 | |
| 97 | /* MSTP10 */ |
| 98 | #define R8A7792_CLK_SSI_ALL 5 |
| 99 | #define R8A7792_CLK_SSI4 11 |
| 100 | #define R8A7792_CLK_SSI3 12 |
| 101 | |
| 102 | #endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */ |