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gerrit-public.fairphone.software / kernel / msm-4.9 / refs/tags/FP3-REL-Q-3.A.0107 / . / include / soc / qcom / msm_tz_smmu.h
blob: 1ae1dd944875b2bb9e6adff1b25b968a40861372 [file] [log] [blame]
Shiraz Hashima28a4792018-01-13 00:39:52 +0530[diff] [blame]1/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
Charan Teja Reddy35144b02017-09-05 16:20:46 +0530[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __MSM_TZ_SMMU_H__
14#define __MSM_TZ_SMMU_H__
15
16#include <linux/device.h>
17
18enum tz_smmu_device_id {
19 TZ_DEVICE_START = 0,
20 TZ_DEVICE_VIDEO = 0,
21 TZ_DEVICE_MDSS,
22 TZ_DEVICE_LPASS,
23 TZ_DEVICE_MDSS_BOOT,
24 TZ_DEVICE_USB1_HS,
25 TZ_DEVICE_OCMEM,
26 TZ_DEVICE_LPASS_CORE,
27 TZ_DEVICE_VPU,
28 TZ_DEVICE_COPSS_SMMU,
29 TZ_DEVICE_USB3_0,
30 TZ_DEVICE_USB3_1,
31 TZ_DEVICE_PCIE_0,
32 TZ_DEVICE_PCIE_1,
33 TZ_DEVICE_BCSS,
34 TZ_DEVICE_VCAP,
35 TZ_DEVICE_PCIE20,
36 TZ_DEVICE_IPA,
37 TZ_DEVICE_APPS,
38 TZ_DEVICE_GPU,
39 TZ_DEVICE_UFS,
40 TZ_DEVICE_ICE,
41 TZ_DEVICE_ROT,
42 TZ_DEVICE_VFE,
43 TZ_DEVICE_ANOC0,
44 TZ_DEVICE_ANOC1,
45 TZ_DEVICE_ANOC2,
46 TZ_DEVICE_CPP,
47 TZ_DEVICE_JPEG,
48 TZ_DEVICE_MAX,
49};
50
51#ifdef CONFIG_MSM_TZ_SMMU
52
53int msm_tz_smmu_atos_start(struct device *dev, int cb_num);
54int msm_tz_smmu_atos_end(struct device *dev, int cb_num);
55enum tz_smmu_device_id msm_dev_to_device_id(struct device *dev);
56int msm_tz_set_cb_format(enum tz_smmu_device_id sec_id, int cbndx);
57int msm_iommu_sec_pgtbl_init(void);
58int register_iommu_sec_ptbl(void);
Charan Teja Reddy6f5cbe7d2017-12-28 19:14:15 +0530[diff] [blame]59bool arm_smmu_skip_write(void __iomem *addr);
60
61/* Donot write to smmu global space with CONFIG_MSM_TZ_SMMU */
62#undef writel_relaxed
Shiraz Hashima28a4792018-01-13 00:39:52 +0530[diff] [blame]63#undef writeq_relaxed
Charan Teja Reddy6f5cbe7d2017-12-28 19:14:15 +0530[diff] [blame]64#define writel_relaxed(v, c) do { \
65 if (!arm_smmu_skip_write(c)) \
66 ((void)__raw_writel((__force u32)cpu_to_le32(v), (c))); \
67 } while (0)
68
Shiraz Hashima28a4792018-01-13 00:39:52 +0530[diff] [blame]69#define writeq_relaxed(v, c) do { \
70 if (!arm_smmu_skip_write(c)) \
71 ((void)__raw_writeq((__force u64)cpu_to_le64(v), (c))); \
72 } while (0)
Charan Teja Reddy35144b02017-09-05 16:20:46 +0530[diff] [blame]73#else
74
75static inline int msm_tz_smmu_atos_start(struct device *dev, int cb_num)
76{
77 return 0;
78}
79
80static inline int msm_tz_smmu_atos_end(struct device *dev, int cb_num)
81{
82 return 0;
83}
84
85static inline enum tz_smmu_device_id msm_dev_to_device_id(struct device *dev)
86{
87 return -EINVAL;
88}
89
90static inline int msm_tz_set_cb_format(enum tz_smmu_device_id sec_id,
91 int cbndx)
92{
93 return -EINVAL;
94}
95
96static inline int msm_iommu_sec_pgtbl_init(void)
97{
98 return -EINVAL;
99}
100
101static inline int register_iommu_sec_ptbl(void)
102{
103 return -EINVAL;
104}
Charan Teja Reddy313991e2018-03-12 12:19:31 +0530[diff] [blame]105
106static inline size_t msm_secure_smmu_unmap(struct iommu_domain *domain,
107 unsigned long iova,
108 size_t size)
109{
110 return -EINVAL;
111}
112
113static inline size_t msm_secure_smmu_map_sg(struct iommu_domain *domain,
114 unsigned long iova,
115 struct scatterlist *sg,
116 unsigned int nents, int prot)
117{
118 return -EINVAL;
119}
120
121static inline int msm_secure_smmu_map(struct iommu_domain *domain,
122 unsigned long iova,
123 phys_addr_t paddr, size_t size, int prot)
124{
125 return -EINVAL;
126}
127
Charan Teja Reddy35144b02017-09-05 16:20:46 +0530[diff] [blame]128#endif /* CONFIG_MSM_TZ_SMMU */
129
130#endif /* __MSM_TZ_SMMU_H__ */