David Howells | 718dced | 2012-10-04 18:21:50 +0100 | [diff] [blame] | 1 | /* exynos_drm.h |
| 2 | * |
| 3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
| 4 | * Authors: |
| 5 | * Inki Dae <inki.dae@samsung.com> |
| 6 | * Joonyoung Shim <jy0922.shim@samsung.com> |
| 7 | * Seung-Woo Kim <sw0312.kim@samsung.com> |
| 8 | * |
Inki Dae | d81aecb | 2012-12-18 02:30:17 +0900 | [diff] [blame] | 9 | * This program is free software; you can redistribute it and/or modify it |
| 10 | * under the terms of the GNU General Public License as published by the |
| 11 | * Free Software Foundation; either version 2 of the License, or (at your |
| 12 | * option) any later version. |
David Howells | 718dced | 2012-10-04 18:21:50 +0100 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #ifndef _UAPI_EXYNOS_DRM_H_ |
| 16 | #define _UAPI_EXYNOS_DRM_H_ |
| 17 | |
Gabriel Laskar | 19b1e97 | 2015-11-30 15:10:45 +0100 | [diff] [blame] | 18 | #include "drm.h" |
David Howells | 718dced | 2012-10-04 18:21:50 +0100 | [diff] [blame] | 19 | |
Emil Velikov | 37a96be | 2016-04-07 18:58:35 +0100 | [diff] [blame] | 20 | #if defined(__cplusplus) |
| 21 | extern "C" { |
| 22 | #endif |
| 23 | |
David Howells | 718dced | 2012-10-04 18:21:50 +0100 | [diff] [blame] | 24 | /** |
| 25 | * User-desired buffer creation information structure. |
| 26 | * |
| 27 | * @size: user-desired memory allocation size. |
| 28 | * - this size value would be page-aligned internally. |
| 29 | * @flags: user request for setting memory type or cache attributes. |
| 30 | * @handle: returned a handle to created gem object. |
| 31 | * - this handle will be set by gem module of kernel side. |
| 32 | */ |
| 33 | struct drm_exynos_gem_create { |
Mikko Rapeli | 6615b20 | 2014-08-31 13:07:31 +0200 | [diff] [blame] | 34 | __u64 size; |
Andrzej Hajda | cbf0ace | 2016-02-12 13:13:59 +0100 | [diff] [blame] | 35 | __u32 flags; |
| 36 | __u32 handle; |
David Howells | 718dced | 2012-10-04 18:21:50 +0100 | [diff] [blame] | 37 | }; |
| 38 | |
| 39 | /** |
Joonyoung Shim | 6564c65 | 2016-03-08 14:12:59 +0900 | [diff] [blame] | 40 | * A structure for getting a fake-offset that can be used with mmap. |
| 41 | * |
| 42 | * @handle: handle of gem object. |
| 43 | * @reserved: just padding to be 64-bit aligned. |
| 44 | * @offset: a fake-offset of gem object. |
| 45 | */ |
| 46 | struct drm_exynos_gem_map { |
| 47 | __u32 handle; |
| 48 | __u32 reserved; |
| 49 | __u64 offset; |
| 50 | }; |
| 51 | |
| 52 | /** |
David Howells | 718dced | 2012-10-04 18:21:50 +0100 | [diff] [blame] | 53 | * A structure to gem information. |
| 54 | * |
| 55 | * @handle: a handle to gem object created. |
| 56 | * @flags: flag value including memory type and cache attribute and |
| 57 | * this value would be set by driver. |
| 58 | * @size: size to memory region allocated by gem and this size would |
| 59 | * be set by driver. |
| 60 | */ |
| 61 | struct drm_exynos_gem_info { |
Andrzej Hajda | cbf0ace | 2016-02-12 13:13:59 +0100 | [diff] [blame] | 62 | __u32 handle; |
| 63 | __u32 flags; |
Mikko Rapeli | 6615b20 | 2014-08-31 13:07:31 +0200 | [diff] [blame] | 64 | __u64 size; |
David Howells | 718dced | 2012-10-04 18:21:50 +0100 | [diff] [blame] | 65 | }; |
| 66 | |
| 67 | /** |
| 68 | * A structure for user connection request of virtual display. |
| 69 | * |
| 70 | * @connection: indicate whether doing connetion or not by user. |
| 71 | * @extensions: if this value is 1 then the vidi driver would need additional |
| 72 | * 128bytes edid data. |
| 73 | * @edid: the edid data pointer from user side. |
| 74 | */ |
| 75 | struct drm_exynos_vidi_connection { |
Andrzej Hajda | cbf0ace | 2016-02-12 13:13:59 +0100 | [diff] [blame] | 76 | __u32 connection; |
| 77 | __u32 extensions; |
Mikko Rapeli | 6615b20 | 2014-08-31 13:07:31 +0200 | [diff] [blame] | 78 | __u64 edid; |
David Howells | 718dced | 2012-10-04 18:21:50 +0100 | [diff] [blame] | 79 | }; |
| 80 | |
| 81 | /* memory type definitions. */ |
| 82 | enum e_drm_exynos_gem_mem_type { |
| 83 | /* Physically Continuous memory and used as default. */ |
| 84 | EXYNOS_BO_CONTIG = 0 << 0, |
| 85 | /* Physically Non-Continuous memory. */ |
| 86 | EXYNOS_BO_NONCONTIG = 1 << 0, |
| 87 | /* non-cachable mapping and used as default. */ |
| 88 | EXYNOS_BO_NONCACHABLE = 0 << 1, |
| 89 | /* cachable mapping. */ |
| 90 | EXYNOS_BO_CACHABLE = 1 << 1, |
| 91 | /* write-combine mapping. */ |
| 92 | EXYNOS_BO_WC = 1 << 2, |
| 93 | EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE | |
| 94 | EXYNOS_BO_WC |
| 95 | }; |
| 96 | |
| 97 | struct drm_exynos_g2d_get_ver { |
| 98 | __u32 major; |
| 99 | __u32 minor; |
| 100 | }; |
| 101 | |
| 102 | struct drm_exynos_g2d_cmd { |
| 103 | __u32 offset; |
| 104 | __u32 data; |
| 105 | }; |
| 106 | |
Inki Dae | 2a3098f | 2012-11-04 05:48:52 -0800 | [diff] [blame] | 107 | enum drm_exynos_g2d_buf_type { |
| 108 | G2D_BUF_USERPTR = 1 << 31, |
| 109 | }; |
| 110 | |
David Howells | 718dced | 2012-10-04 18:21:50 +0100 | [diff] [blame] | 111 | enum drm_exynos_g2d_event_type { |
| 112 | G2D_EVENT_NOT, |
| 113 | G2D_EVENT_NONSTOP, |
| 114 | G2D_EVENT_STOP, /* not yet */ |
| 115 | }; |
| 116 | |
Inki Dae | 2a3098f | 2012-11-04 05:48:52 -0800 | [diff] [blame] | 117 | struct drm_exynos_g2d_userptr { |
| 118 | unsigned long userptr; |
| 119 | unsigned long size; |
| 120 | }; |
| 121 | |
David Howells | 718dced | 2012-10-04 18:21:50 +0100 | [diff] [blame] | 122 | struct drm_exynos_g2d_set_cmdlist { |
| 123 | __u64 cmd; |
Inki Dae | 2a3098f | 2012-11-04 05:48:52 -0800 | [diff] [blame] | 124 | __u64 cmd_buf; |
David Howells | 718dced | 2012-10-04 18:21:50 +0100 | [diff] [blame] | 125 | __u32 cmd_nr; |
Inki Dae | 2a3098f | 2012-11-04 05:48:52 -0800 | [diff] [blame] | 126 | __u32 cmd_buf_nr; |
David Howells | 718dced | 2012-10-04 18:21:50 +0100 | [diff] [blame] | 127 | |
| 128 | /* for g2d event */ |
| 129 | __u64 event_type; |
| 130 | __u64 user_data; |
| 131 | }; |
| 132 | |
| 133 | struct drm_exynos_g2d_exec { |
| 134 | __u64 async; |
| 135 | }; |
| 136 | |
Eunchul Kim | cb471f14 | 2012-12-14 18:10:31 +0900 | [diff] [blame] | 137 | enum drm_exynos_ops_id { |
| 138 | EXYNOS_DRM_OPS_SRC, |
| 139 | EXYNOS_DRM_OPS_DST, |
| 140 | EXYNOS_DRM_OPS_MAX, |
| 141 | }; |
| 142 | |
| 143 | struct drm_exynos_sz { |
| 144 | __u32 hsize; |
| 145 | __u32 vsize; |
| 146 | }; |
| 147 | |
| 148 | struct drm_exynos_pos { |
| 149 | __u32 x; |
| 150 | __u32 y; |
| 151 | __u32 w; |
| 152 | __u32 h; |
| 153 | }; |
| 154 | |
| 155 | enum drm_exynos_flip { |
| 156 | EXYNOS_DRM_FLIP_NONE = (0 << 0), |
| 157 | EXYNOS_DRM_FLIP_VERTICAL = (1 << 0), |
| 158 | EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1), |
Eunchul Kim | 4f21877 | 2012-12-22 17:49:24 +0900 | [diff] [blame] | 159 | EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL | |
| 160 | EXYNOS_DRM_FLIP_HORIZONTAL, |
Eunchul Kim | cb471f14 | 2012-12-14 18:10:31 +0900 | [diff] [blame] | 161 | }; |
| 162 | |
| 163 | enum drm_exynos_degree { |
| 164 | EXYNOS_DRM_DEGREE_0, |
| 165 | EXYNOS_DRM_DEGREE_90, |
| 166 | EXYNOS_DRM_DEGREE_180, |
| 167 | EXYNOS_DRM_DEGREE_270, |
| 168 | }; |
| 169 | |
| 170 | enum drm_exynos_planer { |
| 171 | EXYNOS_DRM_PLANAR_Y, |
| 172 | EXYNOS_DRM_PLANAR_CB, |
| 173 | EXYNOS_DRM_PLANAR_CR, |
| 174 | EXYNOS_DRM_PLANAR_MAX, |
| 175 | }; |
| 176 | |
| 177 | /** |
| 178 | * A structure for ipp supported property list. |
| 179 | * |
| 180 | * @version: version of this structure. |
| 181 | * @ipp_id: id of ipp driver. |
| 182 | * @count: count of ipp driver. |
| 183 | * @writeback: flag of writeback supporting. |
| 184 | * @flip: flag of flip supporting. |
| 185 | * @degree: flag of degree information. |
| 186 | * @csc: flag of csc supporting. |
| 187 | * @crop: flag of crop supporting. |
| 188 | * @scale: flag of scale supporting. |
| 189 | * @refresh_min: min hz of refresh. |
| 190 | * @refresh_max: max hz of refresh. |
| 191 | * @crop_min: crop min resolution. |
| 192 | * @crop_max: crop max resolution. |
| 193 | * @scale_min: scale min resolution. |
| 194 | * @scale_max: scale max resolution. |
| 195 | */ |
| 196 | struct drm_exynos_ipp_prop_list { |
| 197 | __u32 version; |
| 198 | __u32 ipp_id; |
| 199 | __u32 count; |
| 200 | __u32 writeback; |
| 201 | __u32 flip; |
| 202 | __u32 degree; |
| 203 | __u32 csc; |
| 204 | __u32 crop; |
| 205 | __u32 scale; |
| 206 | __u32 refresh_min; |
| 207 | __u32 refresh_max; |
| 208 | __u32 reserved; |
| 209 | struct drm_exynos_sz crop_min; |
| 210 | struct drm_exynos_sz crop_max; |
| 211 | struct drm_exynos_sz scale_min; |
| 212 | struct drm_exynos_sz scale_max; |
| 213 | }; |
| 214 | |
| 215 | /** |
| 216 | * A structure for ipp config. |
| 217 | * |
| 218 | * @ops_id: property of operation directions. |
| 219 | * @flip: property of mirror, flip. |
| 220 | * @degree: property of rotation degree. |
| 221 | * @fmt: property of image format. |
| 222 | * @sz: property of image size. |
| 223 | * @pos: property of image position(src-cropped,dst-scaler). |
| 224 | */ |
| 225 | struct drm_exynos_ipp_config { |
Andrzej Hajda | cbf0ace | 2016-02-12 13:13:59 +0100 | [diff] [blame] | 226 | __u32 ops_id; |
| 227 | __u32 flip; |
| 228 | __u32 degree; |
Eunchul Kim | cb471f14 | 2012-12-14 18:10:31 +0900 | [diff] [blame] | 229 | __u32 fmt; |
| 230 | struct drm_exynos_sz sz; |
| 231 | struct drm_exynos_pos pos; |
| 232 | }; |
| 233 | |
| 234 | enum drm_exynos_ipp_cmd { |
| 235 | IPP_CMD_NONE, |
| 236 | IPP_CMD_M2M, |
| 237 | IPP_CMD_WB, |
| 238 | IPP_CMD_OUTPUT, |
| 239 | IPP_CMD_MAX, |
| 240 | }; |
| 241 | |
| 242 | /** |
| 243 | * A structure for ipp property. |
| 244 | * |
| 245 | * @config: source, destination config. |
| 246 | * @cmd: definition of command. |
| 247 | * @ipp_id: id of ipp driver. |
| 248 | * @prop_id: id of property. |
| 249 | * @refresh_rate: refresh rate. |
| 250 | */ |
| 251 | struct drm_exynos_ipp_property { |
| 252 | struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX]; |
Andrzej Hajda | cbf0ace | 2016-02-12 13:13:59 +0100 | [diff] [blame] | 253 | __u32 cmd; |
Eunchul Kim | cb471f14 | 2012-12-14 18:10:31 +0900 | [diff] [blame] | 254 | __u32 ipp_id; |
| 255 | __u32 prop_id; |
| 256 | __u32 refresh_rate; |
| 257 | }; |
| 258 | |
| 259 | enum drm_exynos_ipp_buf_type { |
| 260 | IPP_BUF_ENQUEUE, |
| 261 | IPP_BUF_DEQUEUE, |
| 262 | }; |
| 263 | |
| 264 | /** |
| 265 | * A structure for ipp buffer operations. |
| 266 | * |
| 267 | * @ops_id: operation directions. |
| 268 | * @buf_type: definition of buffer. |
| 269 | * @prop_id: id of property. |
| 270 | * @buf_id: id of buffer. |
| 271 | * @handle: Y, Cb, Cr each planar handle. |
| 272 | * @user_data: user data. |
| 273 | */ |
| 274 | struct drm_exynos_ipp_queue_buf { |
Andrzej Hajda | cbf0ace | 2016-02-12 13:13:59 +0100 | [diff] [blame] | 275 | __u32 ops_id; |
| 276 | __u32 buf_type; |
Eunchul Kim | cb471f14 | 2012-12-14 18:10:31 +0900 | [diff] [blame] | 277 | __u32 prop_id; |
| 278 | __u32 buf_id; |
| 279 | __u32 handle[EXYNOS_DRM_PLANAR_MAX]; |
| 280 | __u32 reserved; |
| 281 | __u64 user_data; |
| 282 | }; |
| 283 | |
| 284 | enum drm_exynos_ipp_ctrl { |
| 285 | IPP_CTRL_PLAY, |
| 286 | IPP_CTRL_STOP, |
| 287 | IPP_CTRL_PAUSE, |
| 288 | IPP_CTRL_RESUME, |
| 289 | IPP_CTRL_MAX, |
| 290 | }; |
| 291 | |
| 292 | /** |
| 293 | * A structure for ipp start/stop operations. |
| 294 | * |
| 295 | * @prop_id: id of property. |
| 296 | * @ctrl: definition of control. |
| 297 | */ |
| 298 | struct drm_exynos_ipp_cmd_ctrl { |
| 299 | __u32 prop_id; |
Andrzej Hajda | cbf0ace | 2016-02-12 13:13:59 +0100 | [diff] [blame] | 300 | __u32 ctrl; |
Eunchul Kim | cb471f14 | 2012-12-14 18:10:31 +0900 | [diff] [blame] | 301 | }; |
| 302 | |
David Howells | 718dced | 2012-10-04 18:21:50 +0100 | [diff] [blame] | 303 | #define DRM_EXYNOS_GEM_CREATE 0x00 |
Joonyoung Shim | 6564c65 | 2016-03-08 14:12:59 +0900 | [diff] [blame] | 304 | #define DRM_EXYNOS_GEM_MAP 0x01 |
David Howells | 718dced | 2012-10-04 18:21:50 +0100 | [diff] [blame] | 305 | /* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */ |
| 306 | #define DRM_EXYNOS_GEM_GET 0x04 |
| 307 | #define DRM_EXYNOS_VIDI_CONNECTION 0x07 |
| 308 | |
| 309 | /* G2D */ |
| 310 | #define DRM_EXYNOS_G2D_GET_VER 0x20 |
| 311 | #define DRM_EXYNOS_G2D_SET_CMDLIST 0x21 |
| 312 | #define DRM_EXYNOS_G2D_EXEC 0x22 |
| 313 | |
Eunchul Kim | cb471f14 | 2012-12-14 18:10:31 +0900 | [diff] [blame] | 314 | /* IPP - Image Post Processing */ |
| 315 | #define DRM_EXYNOS_IPP_GET_PROPERTY 0x30 |
| 316 | #define DRM_EXYNOS_IPP_SET_PROPERTY 0x31 |
| 317 | #define DRM_EXYNOS_IPP_QUEUE_BUF 0x32 |
| 318 | #define DRM_EXYNOS_IPP_CMD_CTRL 0x33 |
| 319 | |
David Howells | 718dced | 2012-10-04 18:21:50 +0100 | [diff] [blame] | 320 | #define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \ |
| 321 | DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create) |
Joonyoung Shim | 6564c65 | 2016-03-08 14:12:59 +0900 | [diff] [blame] | 322 | #define DRM_IOCTL_EXYNOS_GEM_MAP DRM_IOWR(DRM_COMMAND_BASE + \ |
| 323 | DRM_EXYNOS_GEM_MAP, struct drm_exynos_gem_map) |
David Howells | 718dced | 2012-10-04 18:21:50 +0100 | [diff] [blame] | 324 | #define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \ |
| 325 | DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info) |
| 326 | |
| 327 | #define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \ |
| 328 | DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection) |
| 329 | |
| 330 | #define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \ |
| 331 | DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver) |
| 332 | #define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \ |
| 333 | DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist) |
| 334 | #define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \ |
| 335 | DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec) |
| 336 | |
Eunchul Kim | cb471f14 | 2012-12-14 18:10:31 +0900 | [diff] [blame] | 337 | #define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \ |
| 338 | DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list) |
| 339 | #define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \ |
| 340 | DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property) |
| 341 | #define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + \ |
| 342 | DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf) |
| 343 | #define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + \ |
| 344 | DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl) |
| 345 | |
David Howells | 718dced | 2012-10-04 18:21:50 +0100 | [diff] [blame] | 346 | /* EXYNOS specific events */ |
| 347 | #define DRM_EXYNOS_G2D_EVENT 0x80000000 |
Eunchul Kim | cb471f14 | 2012-12-14 18:10:31 +0900 | [diff] [blame] | 348 | #define DRM_EXYNOS_IPP_EVENT 0x80000001 |
David Howells | 718dced | 2012-10-04 18:21:50 +0100 | [diff] [blame] | 349 | |
| 350 | struct drm_exynos_g2d_event { |
| 351 | struct drm_event base; |
| 352 | __u64 user_data; |
| 353 | __u32 tv_sec; |
| 354 | __u32 tv_usec; |
| 355 | __u32 cmdlist_no; |
| 356 | __u32 reserved; |
| 357 | }; |
| 358 | |
Eunchul Kim | cb471f14 | 2012-12-14 18:10:31 +0900 | [diff] [blame] | 359 | struct drm_exynos_ipp_event { |
| 360 | struct drm_event base; |
| 361 | __u64 user_data; |
| 362 | __u32 tv_sec; |
| 363 | __u32 tv_usec; |
| 364 | __u32 prop_id; |
| 365 | __u32 reserved; |
| 366 | __u32 buf_id[EXYNOS_DRM_OPS_MAX]; |
| 367 | }; |
| 368 | |
Emil Velikov | 37a96be | 2016-04-07 18:58:35 +0100 | [diff] [blame] | 369 | #if defined(__cplusplus) |
| 370 | } |
| 371 | #endif |
| 372 | |
David Howells | 718dced | 2012-10-04 18:21:50 +0100 | [diff] [blame] | 373 | #endif /* _UAPI_EXYNOS_DRM_H_ */ |