Bruce Levy | 73944ad | 2017-03-10 15:56:41 -0800 | [diff] [blame] | 1 | #ifndef _UAPI_MSM_MDP_H_ |
| 2 | #define _UAPI_MSM_MDP_H_ |
| 3 | |
| 4 | #ifndef __KERNEL__ |
| 5 | #include <stdint.h> |
| 6 | #else |
| 7 | #include <linux/types.h> |
| 8 | #endif |
| 9 | #include <linux/fb.h> |
Krishna Manikandan | 695632e | 2020-03-04 20:50:28 +0530 | [diff] [blame] | 10 | #include <stdbool.h> |
Bruce Levy | 73944ad | 2017-03-10 15:56:41 -0800 | [diff] [blame] | 11 | |
| 12 | #define MSMFB_IOCTL_MAGIC 'm' |
| 13 | #define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) |
| 14 | #define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) |
| 15 | #define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) |
| 16 | #define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) |
| 17 | #define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) |
| 18 | #define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) |
| 19 | #define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) |
| 20 | /* new ioctls's for set/get ccs matrix */ |
| 21 | #define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) |
| 22 | #define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) |
| 23 | #define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, \ |
| 24 | struct mdp_overlay) |
| 25 | #define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) |
| 26 | |
| 27 | #define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, \ |
| 28 | struct msmfb_overlay_data) |
| 29 | #define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY |
| 30 | |
| 31 | #define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \ |
| 32 | struct mdp_page_protection) |
| 33 | #define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \ |
| 34 | struct mdp_page_protection) |
| 35 | #define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, \ |
| 36 | struct mdp_overlay) |
| 37 | #define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) |
| 38 | #define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, \ |
| 39 | struct msmfb_overlay_blt) |
| 40 | #define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) |
| 41 | #define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, \ |
| 42 | struct mdp_histogram_start_req) |
| 43 | #define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) |
| 44 | #define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) |
| 45 | |
| 46 | #define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, \ |
| 47 | struct msmfb_overlay_3d) |
| 48 | |
| 49 | #define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, \ |
| 50 | struct msmfb_mixer_info_req) |
| 51 | #define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \ |
| 52 | struct msmfb_overlay_data) |
| 53 | #define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) |
| 54 | #define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) |
| 55 | #define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) |
| 56 | #define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, \ |
| 57 | struct msmfb_data) |
| 58 | #define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, \ |
| 59 | struct msmfb_data) |
| 60 | #define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) |
| 61 | #define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) |
| 62 | #define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) |
| 63 | #define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) |
| 64 | #define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) |
| 65 | #define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) |
| 66 | #define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, \ |
| 67 | struct mdp_display_commit) |
| 68 | #define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) |
| 69 | #define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) |
| 70 | #define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, \ |
| 71 | unsigned int) |
| 72 | #define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) |
| 73 | #define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, \ |
| 74 | struct mdp_overlay_list) |
| 75 | #define MSMFB_LPM_ENABLE _IOWR(MSMFB_IOCTL_MAGIC, 170, unsigned int) |
| 76 | #define MSMFB_MDP_PP_GET_FEATURE_VERSION _IOWR(MSMFB_IOCTL_MAGIC, 171, \ |
| 77 | struct mdp_pp_feature_version) |
| 78 | |
| 79 | #define FB_TYPE_3D_PANEL 0x10101010 |
| 80 | #define MDP_IMGTYPE2_START 0x10000 |
| 81 | #define MSMFB_DRIVER_VERSION 0xF9E8D701 |
| 82 | /* Maximum number of formats supported by MDP*/ |
| 83 | #define MDP_IMGTYPE_END 0x100 |
| 84 | |
| 85 | /* HW Revisions for different MDSS targets */ |
| 86 | #define MDSS_GET_MAJOR(rev) ((rev) >> 28) |
| 87 | #define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) |
| 88 | #define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) |
| 89 | #define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) |
| 90 | |
| 91 | #define IS_MDSS_MAJOR_MINOR_SAME(rev1, rev2) \ |
| 92 | (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) |
| 93 | |
| 94 | #define MDSS_MDP_REV(major, minor, step) \ |
| 95 | ((((major) & 0x000F) << 28) | \ |
| 96 | (((minor) & 0x0FFF) << 16) | \ |
| 97 | ((step) & 0xFFFF)) |
| 98 | |
| 99 | #define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) /* 8974 v1.0 */ |
| 100 | #define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) /* 8x26 v1.0 */ |
| 101 | #define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) /* 8x26 v2.0, 8926 v1.0 */ |
| 102 | #define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) /* 8926 v2.0 */ |
| 103 | #define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) /* 8974 v2.0 */ |
| 104 | #define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) /* 8974 v3.0 (Pro) */ |
| 105 | #define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) /* 8084 v1.0 */ |
| 106 | #define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) /* 8084 v1.1 */ |
| 107 | #define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) /* 8994 v1.0 */ |
| 108 | #define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) /* 8916 v1.0 */ |
| 109 | #define MDSS_MDP_HW_REV_107 MDSS_MDP_REV(1, 7, 0) /* 8996 v1 */ |
| 110 | #define MDSS_MDP_HW_REV_107_1 MDSS_MDP_REV(1, 7, 1) /* 8996 v2 */ |
| 111 | #define MDSS_MDP_HW_REV_107_2 MDSS_MDP_REV(1, 7, 2) /* 8996 v3 */ |
| 112 | #define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) /* 8939 v1.0 */ |
| 113 | #define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) /* 8994 v2.0 */ |
| 114 | #define MDSS_MDP_HW_REV_110 MDSS_MDP_REV(1, 10, 0) /* 8992 v1.0 */ |
| 115 | #define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */ |
| 116 | #define MDSS_MDP_HW_REV_112 MDSS_MDP_REV(1, 12, 0) /* 8952 v1.0 */ |
| 117 | #define MDSS_MDP_HW_REV_114 MDSS_MDP_REV(1, 14, 0) /* 8937 v1.0 */ |
| 118 | #define MDSS_MDP_HW_REV_115 MDSS_MDP_REV(1, 15, 0) /* msmgold */ |
| 119 | #define MDSS_MDP_HW_REV_116 MDSS_MDP_REV(1, 16, 0) /* msmtitanium */ |
| 120 | #define MDSS_MDP_HW_REV_300 MDSS_MDP_REV(3, 0, 0) /* msmcobalt */ |
| 121 | #define MDSS_MDP_HW_REV_301 MDSS_MDP_REV(3, 0, 1) /* msmcobalt v1.0 */ |
| 122 | |
| 123 | enum { |
| 124 | NOTIFY_UPDATE_INIT, |
| 125 | NOTIFY_UPDATE_DEINIT, |
| 126 | NOTIFY_UPDATE_START, |
| 127 | NOTIFY_UPDATE_STOP, |
| 128 | NOTIFY_UPDATE_POWER_OFF, |
| 129 | }; |
| 130 | |
| 131 | enum { |
| 132 | NOTIFY_TYPE_NO_UPDATE, |
| 133 | NOTIFY_TYPE_SUSPEND, |
| 134 | NOTIFY_TYPE_UPDATE, |
| 135 | NOTIFY_TYPE_BL_UPDATE, |
| 136 | NOTIFY_TYPE_BL_AD_ATTEN_UPDATE, |
| 137 | }; |
| 138 | |
| 139 | enum { |
| 140 | MDP_RGB_565, /* RGB 565 planer */ |
| 141 | MDP_XRGB_8888, /* RGB 888 padded */ |
| 142 | MDP_Y_CBCR_H2V2, /* Y and CbCr, pseudo planer w/ Cb is in MSB */ |
| 143 | MDP_Y_CBCR_H2V2_ADRENO, |
| 144 | MDP_ARGB_8888, /* ARGB 888 */ |
| 145 | MDP_RGB_888, /* RGB 888 planer */ |
| 146 | MDP_Y_CRCB_H2V2, /* Y and CrCb, pseudo planer w/ Cr is in MSB */ |
| 147 | MDP_YCRYCB_H2V1, /* YCrYCb interleave */ |
| 148 | MDP_CBYCRY_H2V1, /* CbYCrY interleave */ |
| 149 | MDP_Y_CRCB_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ |
| 150 | MDP_Y_CBCR_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ |
| 151 | MDP_Y_CRCB_H1V2, |
| 152 | MDP_Y_CBCR_H1V2, |
| 153 | MDP_RGBA_8888, /* ARGB 888 */ |
| 154 | MDP_BGRA_8888, /* ABGR 888 */ |
| 155 | MDP_RGBX_8888, /* RGBX 888 */ |
| 156 | MDP_Y_CRCB_H2V2_TILE, /* Y and CrCb, pseudo planer tile */ |
| 157 | MDP_Y_CBCR_H2V2_TILE, /* Y and CbCr, pseudo planer tile */ |
| 158 | MDP_Y_CR_CB_H2V2, /* Y, Cr and Cb, planar */ |
| 159 | MDP_Y_CR_CB_GH2V2, /* Y, Cr and Cb, planar aligned to Android YV12 */ |
| 160 | MDP_Y_CB_CR_H2V2, /* Y, Cb and Cr, planar */ |
| 161 | MDP_Y_CRCB_H1V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ |
| 162 | MDP_Y_CBCR_H1V1, /* Y and CbCr, pseduo planer w/ Cb is in MSB */ |
| 163 | MDP_YCRCB_H1V1, /* YCrCb interleave */ |
| 164 | MDP_YCBCR_H1V1, /* YCbCr interleave */ |
| 165 | MDP_BGR_565, /* BGR 565 planer */ |
| 166 | MDP_BGR_888, /* BGR 888 */ |
| 167 | MDP_Y_CBCR_H2V2_VENUS, |
| 168 | MDP_BGRX_8888, /* BGRX 8888 */ |
| 169 | MDP_RGBA_8888_TILE, /* RGBA 8888 in tile format */ |
| 170 | MDP_ARGB_8888_TILE, /* ARGB 8888 in tile format */ |
| 171 | MDP_ABGR_8888_TILE, /* ABGR 8888 in tile format */ |
| 172 | MDP_BGRA_8888_TILE, /* BGRA 8888 in tile format */ |
| 173 | MDP_RGBX_8888_TILE, /* RGBX 8888 in tile format */ |
| 174 | MDP_XRGB_8888_TILE, /* XRGB 8888 in tile format */ |
| 175 | MDP_XBGR_8888_TILE, /* XBGR 8888 in tile format */ |
| 176 | MDP_BGRX_8888_TILE, /* BGRX 8888 in tile format */ |
| 177 | MDP_YCBYCR_H2V1, /* YCbYCr interleave */ |
| 178 | MDP_RGB_565_TILE, /* RGB 565 in tile format */ |
| 179 | MDP_BGR_565_TILE, /* BGR 565 in tile format */ |
| 180 | MDP_ARGB_1555, /*ARGB 1555*/ |
| 181 | MDP_RGBA_5551, /*RGBA 5551*/ |
| 182 | MDP_ARGB_4444, /*ARGB 4444*/ |
| 183 | MDP_RGBA_4444, /*RGBA 4444*/ |
| 184 | MDP_RGB_565_UBWC, |
| 185 | MDP_RGBA_8888_UBWC, |
| 186 | MDP_Y_CBCR_H2V2_UBWC, |
| 187 | MDP_RGBX_8888_UBWC, |
| 188 | MDP_Y_CRCB_H2V2_VENUS, |
| 189 | MDP_IMGTYPE_LIMIT, |
| 190 | MDP_RGB_BORDERFILL, /* border fill pipe */ |
| 191 | MDP_XRGB_1555, |
| 192 | MDP_RGBX_5551, |
| 193 | MDP_XRGB_4444, |
| 194 | MDP_RGBX_4444, |
| 195 | MDP_ABGR_1555, |
| 196 | MDP_BGRA_5551, |
| 197 | MDP_XBGR_1555, |
| 198 | MDP_BGRX_5551, |
| 199 | MDP_ABGR_4444, |
| 200 | MDP_BGRA_4444, |
| 201 | MDP_XBGR_4444, |
| 202 | MDP_BGRX_4444, |
| 203 | MDP_ABGR_8888, |
| 204 | MDP_XBGR_8888, |
| 205 | MDP_RGBA_1010102, |
| 206 | MDP_ARGB_2101010, |
| 207 | MDP_RGBX_1010102, |
| 208 | MDP_XRGB_2101010, |
| 209 | MDP_BGRA_1010102, |
| 210 | MDP_ABGR_2101010, |
| 211 | MDP_BGRX_1010102, |
| 212 | MDP_XBGR_2101010, |
| 213 | MDP_RGBA_1010102_UBWC, |
| 214 | MDP_RGBX_1010102_UBWC, |
| 215 | MDP_Y_CBCR_H2V2_P010, |
| 216 | MDP_Y_CBCR_H2V2_TP10_UBWC, |
| 217 | MDP_CRYCBY_H2V1, /* CrYCbY interleave */ |
| 218 | MDP_IMGTYPE_LIMIT1 = MDP_IMGTYPE_END, |
| 219 | MDP_FB_FORMAT = MDP_IMGTYPE2_START, /* framebuffer format */ |
| 220 | MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */ |
| 221 | }; |
| 222 | |
| 223 | #define MDP_CRYCBY_H2V1 MDP_CRYCBY_H2V1 |
| 224 | |
| 225 | enum { |
| 226 | PMEM_IMG, |
| 227 | FB_IMG, |
| 228 | }; |
| 229 | |
| 230 | enum { |
| 231 | HSIC_HUE = 0, |
| 232 | HSIC_SAT, |
| 233 | HSIC_INT, |
| 234 | HSIC_CON, |
| 235 | NUM_HSIC_PARAM, |
| 236 | }; |
| 237 | |
| 238 | enum mdss_mdp_max_bw_mode { |
| 239 | MDSS_MAX_BW_LIMIT_DEFAULT = 0x1, |
| 240 | MDSS_MAX_BW_LIMIT_CAMERA = 0x2, |
| 241 | MDSS_MAX_BW_LIMIT_HFLIP = 0x4, |
| 242 | MDSS_MAX_BW_LIMIT_VFLIP = 0x8, |
| 243 | }; |
| 244 | |
| 245 | #define MDSS_MDP_ROT_ONLY 0x80 |
| 246 | #define MDSS_MDP_RIGHT_MIXER 0x100 |
| 247 | #define MDSS_MDP_DUAL_PIPE 0x200 |
| 248 | |
| 249 | /* mdp_blit_req flag values */ |
| 250 | #define MDP_ROT_NOP 0 |
| 251 | #define MDP_FLIP_LR 0x1 |
| 252 | #define MDP_FLIP_UD 0x2 |
| 253 | #define MDP_ROT_90 0x4 |
| 254 | #define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR) |
| 255 | #define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR) |
| 256 | #define MDP_DITHER 0x8 |
| 257 | #define MDP_BLUR 0x10 |
| 258 | #define MDP_BLEND_FG_PREMULT 0x20000 |
| 259 | #define MDP_IS_FG 0x40000 |
| 260 | #define MDP_SOLID_FILL 0x00000020 |
| 261 | #define MDP_VPU_PIPE 0x00000040 |
| 262 | #define MDP_DEINTERLACE 0x80000000 |
| 263 | #define MDP_SHARPENING 0x40000000 |
| 264 | #define MDP_NO_DMA_BARRIER_START 0x20000000 |
| 265 | #define MDP_NO_DMA_BARRIER_END 0x10000000 |
| 266 | #define MDP_NO_BLIT 0x08000000 |
| 267 | #define MDP_BLIT_WITH_DMA_BARRIERS 0x000 |
| 268 | #define MDP_BLIT_WITH_NO_DMA_BARRIERS \ |
| 269 | (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) |
| 270 | #define MDP_BLIT_SRC_GEM 0x04000000 |
| 271 | #define MDP_BLIT_DST_GEM 0x02000000 |
| 272 | #define MDP_BLIT_NON_CACHED 0x01000000 |
| 273 | #define MDP_OV_PIPE_SHARE 0x00800000 |
| 274 | #define MDP_DEINTERLACE_ODD 0x00400000 |
| 275 | #define MDP_OV_PLAY_NOWAIT 0x00200000 |
| 276 | #define MDP_SOURCE_ROTATED_90 0x00100000 |
| 277 | #define MDP_OVERLAY_PP_CFG_EN 0x00080000 |
| 278 | #define MDP_BACKEND_COMPOSITION 0x00040000 |
| 279 | #define MDP_BORDERFILL_SUPPORTED 0x00010000 |
| 280 | #define MDP_SECURE_OVERLAY_SESSION 0x00008000 |
| 281 | #define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 |
| 282 | #define MDP_OV_PIPE_FORCE_DMA 0x00004000 |
| 283 | #define MDP_MEMORY_ID_TYPE_FB 0x00001000 |
| 284 | #define MDP_BWC_EN 0x00000400 |
| 285 | #define MDP_DECIMATION_EN 0x00000800 |
| 286 | #define MDP_SMP_FORCE_ALLOC 0x00200000 |
| 287 | #define MDP_TRANSP_NOP 0xffffffff |
| 288 | #define MDP_ALPHA_NOP 0xff |
| 289 | |
| 290 | #define MDP_FB_PAGE_PROTECTION_NONCACHED (0) |
| 291 | #define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) |
| 292 | #define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) |
| 293 | #define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) |
| 294 | #define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) |
| 295 | /* Sentinel: Don't use! */ |
| 296 | #define MDP_FB_PAGE_PROTECTION_INVALID (5) |
| 297 | /* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */ |
| 298 | #define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) |
| 299 | |
| 300 | #define MDP_DEEP_COLOR_YUV444 0x1 |
| 301 | #define MDP_DEEP_COLOR_RGB30B 0x2 |
| 302 | #define MDP_DEEP_COLOR_RGB36B 0x4 |
| 303 | #define MDP_DEEP_COLOR_RGB48B 0x8 |
| 304 | |
| 305 | struct mdp_rect { |
| 306 | uint32_t x; |
| 307 | uint32_t y; |
| 308 | uint32_t w; |
| 309 | uint32_t h; |
| 310 | }; |
| 311 | |
| 312 | struct mdp_img { |
| 313 | uint32_t width; |
| 314 | uint32_t height; |
| 315 | uint32_t format; |
| 316 | uint32_t offset; |
| 317 | int memory_id; /* the file descriptor */ |
| 318 | uint32_t priv; |
| 319 | }; |
| 320 | |
| 321 | struct mult_factor { |
| 322 | uint32_t numer; |
| 323 | uint32_t denom; |
| 324 | }; |
| 325 | |
| 326 | /* |
| 327 | * {3x3} + {3} ccs matrix |
| 328 | */ |
| 329 | |
| 330 | #define MDP_CCS_RGB2YUV 0 |
| 331 | #define MDP_CCS_YUV2RGB 1 |
| 332 | |
| 333 | #define MDP_CCS_SIZE 9 |
| 334 | #define MDP_BV_SIZE 3 |
| 335 | |
| 336 | struct mdp_ccs { |
| 337 | int direction; /* MDP_CCS_RGB2YUV or YUV2RGB */ |
| 338 | uint16_t ccs[MDP_CCS_SIZE]; /* 3x3 color coefficients */ |
| 339 | uint16_t bv[MDP_BV_SIZE]; /* 1x3 bias vector */ |
| 340 | }; |
| 341 | |
| 342 | struct mdp_csc { |
| 343 | int id; |
| 344 | uint32_t csc_mv[9]; |
| 345 | uint32_t csc_pre_bv[3]; |
| 346 | uint32_t csc_post_bv[3]; |
| 347 | uint32_t csc_pre_lv[6]; |
| 348 | uint32_t csc_post_lv[6]; |
| 349 | }; |
| 350 | |
| 351 | /* The version of the mdp_blit_req structure so that |
| 352 | * user applications can selectively decide which functionality |
| 353 | * to include |
| 354 | */ |
| 355 | |
| 356 | #define MDP_BLIT_REQ_VERSION 3 |
| 357 | |
| 358 | struct color { |
| 359 | uint32_t r; |
| 360 | uint32_t g; |
| 361 | uint32_t b; |
| 362 | uint32_t alpha; |
| 363 | }; |
| 364 | |
| 365 | struct mdp_blit_req { |
| 366 | struct mdp_img src; |
| 367 | struct mdp_img dst; |
| 368 | struct mdp_rect src_rect; |
| 369 | struct mdp_rect dst_rect; |
| 370 | struct color const_color; |
| 371 | uint32_t alpha; |
| 372 | uint32_t transp_mask; |
| 373 | uint32_t flags; |
| 374 | int sharpening_strength; /* -127 <--> 127, default 64 */ |
| 375 | uint8_t color_space; |
| 376 | uint32_t fps; |
| 377 | }; |
| 378 | |
| 379 | struct mdp_blit_req_list { |
| 380 | uint32_t count; |
| 381 | struct mdp_blit_req req[]; |
| 382 | }; |
| 383 | |
| 384 | #define MSMFB_DATA_VERSION 2 |
| 385 | |
| 386 | struct msmfb_data { |
| 387 | uint32_t offset; |
| 388 | int memory_id; |
| 389 | int id; |
| 390 | uint32_t flags; |
| 391 | uint32_t priv; |
| 392 | uint32_t iova; |
| 393 | }; |
| 394 | |
| 395 | #define MSMFB_NEW_REQUEST -1 |
| 396 | |
| 397 | struct msmfb_overlay_data { |
| 398 | uint32_t id; |
| 399 | struct msmfb_data data; |
| 400 | uint32_t version_key; |
| 401 | struct msmfb_data plane1_data; |
| 402 | struct msmfb_data plane2_data; |
| 403 | struct msmfb_data dst_data; |
| 404 | }; |
| 405 | |
| 406 | struct msmfb_img { |
| 407 | uint32_t width; |
| 408 | uint32_t height; |
| 409 | uint32_t format; |
| 410 | }; |
| 411 | |
| 412 | #define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 |
| 413 | struct msmfb_writeback_data { |
| 414 | struct msmfb_data buf_info; |
| 415 | struct msmfb_img img; |
| 416 | }; |
| 417 | |
| 418 | #define MDP_PP_OPS_ENABLE 0x1 |
| 419 | #define MDP_PP_OPS_READ 0x2 |
| 420 | #define MDP_PP_OPS_WRITE 0x4 |
| 421 | #define MDP_PP_OPS_DISABLE 0x8 |
| 422 | #define MDP_PP_IGC_FLAG_ROM0 0x10 |
| 423 | #define MDP_PP_IGC_FLAG_ROM1 0x20 |
| 424 | |
| 425 | |
| 426 | #define MDSS_PP_DSPP_CFG 0x000 |
| 427 | #define MDSS_PP_SSPP_CFG 0x100 |
| 428 | #define MDSS_PP_LM_CFG 0x200 |
| 429 | #define MDSS_PP_WB_CFG 0x300 |
| 430 | |
| 431 | #define MDSS_PP_ARG_MASK 0x3C00 |
| 432 | #define MDSS_PP_ARG_NUM 4 |
| 433 | #define MDSS_PP_ARG_SHIFT 10 |
| 434 | #define MDSS_PP_LOCATION_MASK 0x0300 |
| 435 | #define MDSS_PP_LOGICAL_MASK 0x00FF |
| 436 | |
| 437 | #define MDSS_PP_ADD_ARG(var, arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) |
| 438 | #define PP_ARG(x, var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) |
| 439 | #define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) |
| 440 | #define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) |
| 441 | |
| 442 | |
| 443 | struct mdp_qseed_cfg { |
| 444 | uint32_t table_num; |
| 445 | uint32_t ops; |
| 446 | uint32_t len; |
| 447 | uint32_t *data; |
| 448 | }; |
| 449 | |
| 450 | struct mdp_sharp_cfg { |
| 451 | uint32_t flags; |
| 452 | uint32_t strength; |
| 453 | uint32_t edge_thr; |
| 454 | uint32_t smooth_thr; |
| 455 | uint32_t noise_thr; |
| 456 | }; |
| 457 | |
| 458 | struct mdp_qseed_cfg_data { |
| 459 | uint32_t block; |
| 460 | struct mdp_qseed_cfg qseed_data; |
| 461 | }; |
| 462 | |
| 463 | #define MDP_OVERLAY_PP_CSC_CFG 0x1 |
| 464 | #define MDP_OVERLAY_PP_QSEED_CFG 0x2 |
| 465 | #define MDP_OVERLAY_PP_PA_CFG 0x4 |
| 466 | #define MDP_OVERLAY_PP_IGC_CFG 0x8 |
| 467 | #define MDP_OVERLAY_PP_SHARP_CFG 0x10 |
| 468 | #define MDP_OVERLAY_PP_HIST_CFG 0x20 |
| 469 | #define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 |
| 470 | #define MDP_OVERLAY_PP_PA_V2_CFG 0x80 |
| 471 | #define MDP_OVERLAY_PP_PCC_CFG 0x100 |
| 472 | |
| 473 | #define MDP_CSC_FLAG_ENABLE 0x1 |
| 474 | #define MDP_CSC_FLAG_YUV_IN 0x2 |
| 475 | #define MDP_CSC_FLAG_YUV_OUT 0x4 |
| 476 | |
| 477 | #define MDP_CSC_MATRIX_COEFF_SIZE 9 |
| 478 | #define MDP_CSC_CLAMP_SIZE 6 |
| 479 | #define MDP_CSC_BIAS_SIZE 3 |
| 480 | |
| 481 | struct mdp_csc_cfg { |
| 482 | /* flags for enable CSC, toggling RGB,YUV input/output */ |
| 483 | uint32_t flags; |
| 484 | uint32_t csc_mv[MDP_CSC_MATRIX_COEFF_SIZE]; |
| 485 | uint32_t csc_pre_bv[MDP_CSC_BIAS_SIZE]; |
| 486 | uint32_t csc_post_bv[MDP_CSC_BIAS_SIZE]; |
| 487 | uint32_t csc_pre_lv[MDP_CSC_CLAMP_SIZE]; |
| 488 | uint32_t csc_post_lv[MDP_CSC_CLAMP_SIZE]; |
| 489 | }; |
| 490 | |
| 491 | struct mdp_csc_cfg_data { |
| 492 | uint32_t block; |
| 493 | struct mdp_csc_cfg csc_data; |
| 494 | }; |
| 495 | |
| 496 | struct mdp_pa_cfg { |
| 497 | uint32_t flags; |
| 498 | uint32_t hue_adj; |
| 499 | uint32_t sat_adj; |
| 500 | uint32_t val_adj; |
| 501 | uint32_t cont_adj; |
| 502 | }; |
| 503 | |
| 504 | struct mdp_pa_mem_col_cfg { |
| 505 | uint32_t color_adjust_p0; |
| 506 | uint32_t color_adjust_p1; |
| 507 | uint32_t hue_region; |
| 508 | uint32_t sat_region; |
| 509 | uint32_t val_region; |
| 510 | }; |
| 511 | |
| 512 | #define MDP_SIX_ZONE_LUT_SIZE 384 |
| 513 | |
| 514 | /* PA Write/Read extension flags */ |
| 515 | #define MDP_PP_PA_HUE_ENABLE 0x10 |
| 516 | #define MDP_PP_PA_SAT_ENABLE 0x20 |
| 517 | #define MDP_PP_PA_VAL_ENABLE 0x40 |
| 518 | #define MDP_PP_PA_CONT_ENABLE 0x80 |
| 519 | #define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 |
| 520 | #define MDP_PP_PA_SKIN_ENABLE 0x200 |
| 521 | #define MDP_PP_PA_SKY_ENABLE 0x400 |
| 522 | #define MDP_PP_PA_FOL_ENABLE 0x800 |
| 523 | |
| 524 | /* PA masks */ |
| 525 | /* Masks used in PA v1_7 only */ |
| 526 | #define MDP_PP_PA_MEM_PROT_HUE_EN 0x1 |
| 527 | #define MDP_PP_PA_MEM_PROT_SAT_EN 0x2 |
| 528 | #define MDP_PP_PA_MEM_PROT_VAL_EN 0x4 |
| 529 | #define MDP_PP_PA_MEM_PROT_CONT_EN 0x8 |
| 530 | #define MDP_PP_PA_MEM_PROT_SIX_EN 0x10 |
| 531 | #define MDP_PP_PA_MEM_PROT_BLEND_EN 0x20 |
| 532 | /* Masks used in all PAv2 versions */ |
| 533 | #define MDP_PP_PA_HUE_MASK 0x1000 |
| 534 | #define MDP_PP_PA_SAT_MASK 0x2000 |
| 535 | #define MDP_PP_PA_VAL_MASK 0x4000 |
| 536 | #define MDP_PP_PA_CONT_MASK 0x8000 |
| 537 | #define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 |
| 538 | #define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 |
| 539 | #define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 |
| 540 | #define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 |
| 541 | #define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 |
| 542 | #define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 |
| 543 | #define MDP_PP_PA_MEM_PROTECT_EN 0x400000 |
| 544 | #define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 |
| 545 | |
| 546 | /* Flags for setting PA saturation and value hold */ |
| 547 | #define MDP_PP_PA_LEFT_HOLD 0x1 |
| 548 | #define MDP_PP_PA_RIGHT_HOLD 0x2 |
| 549 | |
| 550 | struct mdp_pa_v2_data { |
| 551 | /* Mask bits for PA features */ |
| 552 | uint32_t flags; |
| 553 | uint32_t global_hue_adj; |
| 554 | uint32_t global_sat_adj; |
| 555 | uint32_t global_val_adj; |
| 556 | uint32_t global_cont_adj; |
| 557 | struct mdp_pa_mem_col_cfg skin_cfg; |
| 558 | struct mdp_pa_mem_col_cfg sky_cfg; |
| 559 | struct mdp_pa_mem_col_cfg fol_cfg; |
| 560 | uint32_t six_zone_len; |
| 561 | uint32_t six_zone_thresh; |
| 562 | uint32_t *six_zone_curve_p0; |
| 563 | uint32_t *six_zone_curve_p1; |
| 564 | }; |
| 565 | |
| 566 | struct mdp_pa_mem_col_data_v1_7 { |
| 567 | uint32_t color_adjust_p0; |
| 568 | uint32_t color_adjust_p1; |
| 569 | uint32_t color_adjust_p2; |
| 570 | uint32_t blend_gain; |
| 571 | uint8_t sat_hold; |
| 572 | uint8_t val_hold; |
| 573 | uint32_t hue_region; |
| 574 | uint32_t sat_region; |
| 575 | uint32_t val_region; |
| 576 | }; |
| 577 | |
| 578 | struct mdp_pa_data_v1_7 { |
| 579 | uint32_t mode; |
| 580 | uint32_t global_hue_adj; |
| 581 | uint32_t global_sat_adj; |
| 582 | uint32_t global_val_adj; |
| 583 | uint32_t global_cont_adj; |
| 584 | struct mdp_pa_mem_col_data_v1_7 skin_cfg; |
| 585 | struct mdp_pa_mem_col_data_v1_7 sky_cfg; |
| 586 | struct mdp_pa_mem_col_data_v1_7 fol_cfg; |
| 587 | uint32_t six_zone_thresh; |
| 588 | uint32_t six_zone_adj_p0; |
| 589 | uint32_t six_zone_adj_p1; |
| 590 | uint8_t six_zone_sat_hold; |
| 591 | uint8_t six_zone_val_hold; |
| 592 | uint32_t six_zone_len; |
| 593 | uint32_t *six_zone_curve_p0; |
| 594 | uint32_t *six_zone_curve_p1; |
| 595 | }; |
| 596 | |
| 597 | |
| 598 | struct mdp_pa_v2_cfg_data { |
| 599 | uint32_t version; |
| 600 | uint32_t block; |
| 601 | uint32_t flags; |
| 602 | struct mdp_pa_v2_data pa_v2_data; |
| 603 | void *cfg_payload; |
| 604 | }; |
| 605 | |
| 606 | |
| 607 | enum { |
| 608 | mdp_igc_rec601 = 1, |
| 609 | mdp_igc_rec709, |
| 610 | mdp_igc_srgb, |
| 611 | mdp_igc_custom, |
| 612 | mdp_igc_rec_max, |
| 613 | }; |
| 614 | |
| 615 | struct mdp_igc_lut_data { |
| 616 | uint32_t block; |
| 617 | uint32_t version; |
| 618 | uint32_t len, ops; |
| 619 | uint32_t *c0_c1_data; |
| 620 | uint32_t *c2_data; |
| 621 | void *cfg_payload; |
| 622 | }; |
| 623 | |
| 624 | struct mdp_igc_lut_data_v1_7 { |
| 625 | uint32_t table_fmt; |
| 626 | uint32_t len; |
| 627 | uint32_t *c0_c1_data; |
| 628 | uint32_t *c2_data; |
| 629 | }; |
| 630 | |
| 631 | struct mdp_igc_lut_data_payload { |
| 632 | uint32_t table_fmt; |
| 633 | uint32_t len; |
| 634 | uint64_t __user c0_c1_data; |
| 635 | uint64_t __user c2_data; |
| 636 | uint32_t strength; |
| 637 | }; |
| 638 | |
| 639 | struct mdp_histogram_cfg { |
| 640 | uint32_t ops; |
| 641 | uint32_t block; |
| 642 | uint8_t frame_cnt; |
| 643 | uint8_t bit_mask; |
| 644 | uint16_t num_bins; |
| 645 | }; |
| 646 | |
| 647 | struct mdp_hist_lut_data_v1_7 { |
| 648 | uint32_t len; |
| 649 | uint32_t *data; |
| 650 | }; |
| 651 | |
| 652 | struct mdp_hist_lut_data { |
| 653 | uint32_t block; |
| 654 | uint32_t version; |
| 655 | uint32_t hist_lut_first; |
| 656 | uint32_t ops; |
| 657 | uint32_t len; |
| 658 | uint32_t *data; |
| 659 | void *cfg_payload; |
| 660 | }; |
| 661 | |
| 662 | struct mdp_pcc_coeff { |
| 663 | uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; |
| 664 | }; |
| 665 | |
| 666 | struct mdp_pcc_coeff_v1_7 { |
| 667 | uint32_t c, r, g, b, rg, gb, rb, rgb; |
| 668 | }; |
| 669 | |
| 670 | struct mdp_pcc_data_v1_7 { |
| 671 | struct mdp_pcc_coeff_v1_7 r, g, b; |
| 672 | }; |
| 673 | |
| 674 | struct mdp_pcc_cfg_data { |
| 675 | uint32_t version; |
| 676 | uint32_t block; |
| 677 | uint32_t ops; |
| 678 | struct mdp_pcc_coeff r, g, b; |
| 679 | void *cfg_payload; |
| 680 | }; |
| 681 | |
| 682 | enum { |
| 683 | mdp_lut_igc, |
| 684 | mdp_lut_pgc, |
| 685 | mdp_lut_hist, |
| 686 | mdp_lut_rgb, |
| 687 | mdp_lut_max, |
| 688 | }; |
| 689 | struct mdp_overlay_pp_params { |
| 690 | uint32_t config_ops; |
| 691 | struct mdp_csc_cfg csc_cfg; |
| 692 | struct mdp_qseed_cfg qseed_cfg[2]; |
| 693 | struct mdp_pa_cfg pa_cfg; |
| 694 | struct mdp_pa_v2_data pa_v2_cfg; |
| 695 | struct mdp_igc_lut_data igc_cfg; |
| 696 | struct mdp_sharp_cfg sharp_cfg; |
| 697 | struct mdp_histogram_cfg hist_cfg; |
| 698 | struct mdp_hist_lut_data hist_lut_cfg; |
| 699 | /* PAv2 cfg data for PA 2.x versions */ |
| 700 | struct mdp_pa_v2_cfg_data pa_v2_cfg_data; |
| 701 | struct mdp_pcc_cfg_data pcc_cfg_data; |
| 702 | }; |
| 703 | |
| 704 | /** |
| 705 | * enum mdss_mdp_blend_op - Different blend operations set by userspace |
| 706 | * |
| 707 | * @BLEND_OP_NOT_DEFINED: No blend operation defined for the layer. |
| 708 | * @BLEND_OP_OPAQUE: Apply a constant blend operation. The layer |
| 709 | * would appear opaque in case fg plane alpha is |
| 710 | * 0xff. |
| 711 | * @BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already has |
| 712 | * alpha pre-multiplication done. If fg plane alpha |
| 713 | * is less than 0xff, apply modulation as well. This |
| 714 | * operation is intended on layers having alpha |
| 715 | * channel. |
| 716 | * @BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not alpha |
| 717 | * pre-multiplied. Apply pre-multiplication. If fg |
| 718 | * plane alpha is less than 0xff, apply modulation as |
| 719 | * well. |
| 720 | * @BLEND_OP_MAX: Used to track maximum blend operation possible by |
| 721 | * mdp. |
| 722 | */ |
| 723 | enum mdss_mdp_blend_op { |
| 724 | BLEND_OP_NOT_DEFINED = 0, |
| 725 | BLEND_OP_OPAQUE, |
| 726 | BLEND_OP_PREMULTIPLIED, |
| 727 | BLEND_OP_COVERAGE, |
| 728 | BLEND_OP_MAX, |
| 729 | }; |
| 730 | |
| 731 | #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) |
| 732 | #define MAX_PLANES 4 |
| 733 | struct mdp_scale_data { |
| 734 | uint8_t enable_pxl_ext; |
| 735 | |
| 736 | int init_phase_x[MAX_PLANES]; |
| 737 | int phase_step_x[MAX_PLANES]; |
| 738 | int init_phase_y[MAX_PLANES]; |
| 739 | int phase_step_y[MAX_PLANES]; |
| 740 | |
| 741 | int num_ext_pxls_left[MAX_PLANES]; |
| 742 | int num_ext_pxls_right[MAX_PLANES]; |
| 743 | int num_ext_pxls_top[MAX_PLANES]; |
| 744 | int num_ext_pxls_btm[MAX_PLANES]; |
| 745 | |
| 746 | int left_ftch[MAX_PLANES]; |
| 747 | int left_rpt[MAX_PLANES]; |
| 748 | int right_ftch[MAX_PLANES]; |
| 749 | int right_rpt[MAX_PLANES]; |
| 750 | |
| 751 | int top_rpt[MAX_PLANES]; |
| 752 | int btm_rpt[MAX_PLANES]; |
| 753 | int top_ftch[MAX_PLANES]; |
| 754 | int btm_ftch[MAX_PLANES]; |
| 755 | |
| 756 | uint32_t roi_w[MAX_PLANES]; |
| 757 | }; |
| 758 | |
| 759 | /** |
| 760 | * enum mdp_overlay_pipe_type - Different pipe type set by userspace |
| 761 | * |
| 762 | * @PIPE_TYPE_AUTO: Not specified, pipe will be selected according to flags. |
| 763 | * @PIPE_TYPE_VIG: VIG pipe. |
| 764 | * @PIPE_TYPE_RGB: RGB pipe. |
| 765 | * @PIPE_TYPE_DMA: DMA pipe. |
| 766 | * @PIPE_TYPE_CURSOR: CURSOR pipe. |
| 767 | * @PIPE_TYPE_MAX: Used to track maximum number of pipe type. |
| 768 | */ |
| 769 | enum mdp_overlay_pipe_type { |
| 770 | PIPE_TYPE_AUTO = 0, |
| 771 | PIPE_TYPE_VIG, |
| 772 | PIPE_TYPE_RGB, |
| 773 | PIPE_TYPE_DMA, |
| 774 | PIPE_TYPE_CURSOR, |
| 775 | PIPE_TYPE_MAX, |
| 776 | }; |
| 777 | |
| 778 | /** |
| 779 | * struct mdp_overlay - overlay surface structure |
| 780 | * @src: Source image information (width, height, format). |
| 781 | * @src_rect: Source crop rectangle, portion of image that will be fetched. |
| 782 | * This should always be within boundaries of source image. |
| 783 | * @dst_rect: Destination rectangle, the position and size of image on screen. |
| 784 | * This should always be within panel boundaries. |
| 785 | * @z_order: Blending stage to occupy in display, if multiple layers are |
| 786 | * present, highest z_order usually means the top most visible |
| 787 | * layer. The range acceptable is from 0-3 to support blending |
| 788 | * up to 4 layers. |
| 789 | * @is_fg: This flag is used to disable blending of any layers with z_order |
| 790 | * less than this overlay. It means that any layers with z_order |
| 791 | * less than this layer will not be blended and will be replaced |
| 792 | * by the background border color. |
| 793 | * @alpha: Used to set plane opacity. The range can be from 0-255, where |
| 794 | * 0 means completely transparent and 255 means fully opaque. |
| 795 | * @transp_mask: Color used as color key for transparency. Any pixel in fetched |
| 796 | * image matching this color will be transparent when blending. |
| 797 | * The color should be in same format as the source image format. |
| 798 | * @flags: This is used to customize operation of overlay. See MDP flags |
| 799 | * for more information. |
| 800 | * @pipe_type: Used to specify the type of overlay pipe. |
| 801 | * @user_data: DEPRECATED* Used to store user application specific information. |
| 802 | * @bg_color: Solid color used to fill the overlay surface when no source |
| 803 | * buffer is provided. |
| 804 | * @horz_deci: Horizontal decimation value, this indicates the amount of pixels |
| 805 | * dropped for each pixel that is fetched from a line. The value |
| 806 | * given should be power of two of decimation amount. |
| 807 | * 0: no decimation |
| 808 | * 1: decimate by 2 (drop 1 pixel for each pixel fetched) |
| 809 | * 2: decimate by 4 (drop 3 pixels for each pixel fetched) |
| 810 | * 3: decimate by 8 (drop 7 pixels for each pixel fetched) |
| 811 | * 4: decimate by 16 (drop 15 pixels for each pixel fetched) |
| 812 | * @vert_deci: Vertical decimation value, this indicates the amount of lines |
| 813 | * dropped for each line that is fetched from overlay. The value |
| 814 | * given should be power of two of decimation amount. |
| 815 | * 0: no decimation |
| 816 | * 1: decimation by 2 (drop 1 line for each line fetched) |
| 817 | * 2: decimation by 4 (drop 3 lines for each line fetched) |
| 818 | * 3: decimation by 8 (drop 7 lines for each line fetched) |
| 819 | * 4: decimation by 16 (drop 15 lines for each line fetched) |
| 820 | * @overlay_pp_cfg: Overlay post processing configuration, for more information |
| 821 | * see struct mdp_overlay_pp_params. |
| 822 | * @priority: Priority is returned by the driver when overlay is set for the |
| 823 | * first time. It indicates the priority of the underlying pipe |
| 824 | * serving the overlay. This priority can be used by user-space |
| 825 | * in source split when pipes are re-used and shuffled around to |
| 826 | * reduce fallbacks. |
| 827 | */ |
| 828 | struct mdp_overlay { |
| 829 | struct msmfb_img src; |
| 830 | struct mdp_rect src_rect; |
| 831 | struct mdp_rect dst_rect; |
| 832 | uint32_t z_order; /* stage number */ |
| 833 | uint32_t is_fg; /* control alpha & transp */ |
| 834 | uint32_t alpha; |
| 835 | uint32_t blend_op; |
| 836 | uint32_t transp_mask; |
| 837 | uint32_t flags; |
| 838 | uint32_t pipe_type; |
| 839 | uint32_t id; |
| 840 | uint8_t priority; |
| 841 | uint32_t user_data[6]; |
| 842 | uint32_t bg_color; |
| 843 | uint8_t horz_deci; |
| 844 | uint8_t vert_deci; |
| 845 | struct mdp_overlay_pp_params overlay_pp_cfg; |
| 846 | struct mdp_scale_data scale; |
| 847 | uint8_t color_space; |
| 848 | uint32_t frame_rate; |
| 849 | }; |
| 850 | |
| 851 | struct msmfb_overlay_3d { |
| 852 | uint32_t is_3d; |
| 853 | uint32_t width; |
| 854 | uint32_t height; |
| 855 | }; |
| 856 | |
| 857 | |
| 858 | struct msmfb_overlay_blt { |
| 859 | uint32_t enable; |
| 860 | uint32_t offset; |
| 861 | uint32_t width; |
| 862 | uint32_t height; |
| 863 | uint32_t bpp; |
| 864 | }; |
| 865 | |
| 866 | struct mdp_histogram { |
| 867 | uint32_t frame_cnt; |
| 868 | uint32_t bin_cnt; |
| 869 | uint32_t *r; |
| 870 | uint32_t *g; |
| 871 | uint32_t *b; |
| 872 | }; |
| 873 | |
| 874 | #define MISR_CRC_BATCH_SIZE 32 |
| 875 | enum { |
| 876 | DISPLAY_MISR_EDP, |
| 877 | DISPLAY_MISR_DSI0, |
| 878 | DISPLAY_MISR_DSI1, |
| 879 | DISPLAY_MISR_HDMI, |
| 880 | DISPLAY_MISR_LCDC, |
| 881 | DISPLAY_MISR_MDP, |
| 882 | DISPLAY_MISR_ATV, |
| 883 | DISPLAY_MISR_DSI_CMD, |
| 884 | DISPLAY_MISR_MAX |
| 885 | }; |
| 886 | |
| 887 | enum { |
| 888 | MISR_OP_NONE, |
| 889 | MISR_OP_SFM, |
| 890 | MISR_OP_MFM, |
| 891 | MISR_OP_BM, |
| 892 | MISR_OP_MAX |
| 893 | }; |
| 894 | |
| 895 | struct mdp_misr { |
| 896 | uint32_t block_id; |
| 897 | uint32_t frame_count; |
| 898 | uint32_t crc_op_mode; |
| 899 | uint32_t crc_value[MISR_CRC_BATCH_SIZE]; |
| 900 | }; |
| 901 | |
| 902 | /* |
| 903 | * mdp_block_type defines the identifiers for pipes in MDP 4.3 and up |
| 904 | * |
| 905 | * MDP_BLOCK_RESERVED is provided for backward compatibility and is |
| 906 | * deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used |
| 907 | * instead. |
| 908 | * |
| 909 | * MDP_LOGICAL_BLOCK_DISP_0 identifies the display pipe which fb0 uses, |
| 910 | * same for others. |
| 911 | */ |
| 912 | |
| 913 | enum { |
| 914 | MDP_BLOCK_RESERVED = 0, |
| 915 | MDP_BLOCK_OVERLAY_0, |
| 916 | MDP_BLOCK_OVERLAY_1, |
| 917 | MDP_BLOCK_VG_1, |
| 918 | MDP_BLOCK_VG_2, |
| 919 | MDP_BLOCK_RGB_1, |
| 920 | MDP_BLOCK_RGB_2, |
| 921 | MDP_BLOCK_DMA_P, |
| 922 | MDP_BLOCK_DMA_S, |
| 923 | MDP_BLOCK_DMA_E, |
| 924 | MDP_BLOCK_OVERLAY_2, |
| 925 | MDP_LOGICAL_BLOCK_DISP_0 = 0x10, |
| 926 | MDP_LOGICAL_BLOCK_DISP_1, |
| 927 | MDP_LOGICAL_BLOCK_DISP_2, |
| 928 | MDP_BLOCK_MAX, |
| 929 | }; |
| 930 | |
| 931 | /* |
| 932 | * mdp_histogram_start_req is used to provide the parameters for |
| 933 | * histogram start request |
| 934 | */ |
| 935 | |
| 936 | struct mdp_histogram_start_req { |
| 937 | uint32_t block; |
| 938 | uint8_t frame_cnt; |
| 939 | uint8_t bit_mask; |
| 940 | uint16_t num_bins; |
| 941 | }; |
| 942 | |
| 943 | /* |
| 944 | * mdp_histogram_data is used to return the histogram data, once |
| 945 | * the histogram is done/stopped/cance |
| 946 | */ |
| 947 | |
| 948 | struct mdp_histogram_data { |
| 949 | uint32_t block; |
| 950 | uint32_t bin_cnt; |
| 951 | uint32_t *c0; |
| 952 | uint32_t *c1; |
| 953 | uint32_t *c2; |
| 954 | uint32_t *extra_info; |
| 955 | }; |
| 956 | |
| 957 | |
| 958 | #define GC_LUT_ENTRIES_V1_7 512 |
| 959 | |
| 960 | struct mdp_ar_gc_lut_data { |
| 961 | uint32_t x_start; |
| 962 | uint32_t slope; |
| 963 | uint32_t offset; |
| 964 | }; |
| 965 | |
| 966 | #define MDP_PP_PGC_ROUNDING_ENABLE 0x10 |
| 967 | struct mdp_pgc_lut_data { |
| 968 | uint32_t version; |
| 969 | uint32_t block; |
| 970 | uint32_t flags; |
| 971 | uint8_t num_r_stages; |
| 972 | uint8_t num_g_stages; |
| 973 | uint8_t num_b_stages; |
| 974 | struct mdp_ar_gc_lut_data *r_data; |
| 975 | struct mdp_ar_gc_lut_data *g_data; |
| 976 | struct mdp_ar_gc_lut_data *b_data; |
| 977 | void *cfg_payload; |
| 978 | }; |
| 979 | |
| 980 | #define PGC_LUT_ENTRIES 1024 |
| 981 | struct mdp_pgc_lut_data_v1_7 { |
| 982 | uint32_t len; |
| 983 | uint32_t *c0_data; |
| 984 | uint32_t *c1_data; |
| 985 | uint32_t *c2_data; |
| 986 | }; |
| 987 | |
| 988 | /* |
| 989 | * mdp_rgb_lut_data is used to provide parameters for configuring the |
| 990 | * generic RGB lut in case of gamma correction or other LUT updation usecases |
| 991 | */ |
| 992 | struct mdp_rgb_lut_data { |
| 993 | uint32_t flags; |
| 994 | uint32_t lut_type; |
| 995 | struct fb_cmap cmap; |
| 996 | }; |
| 997 | |
| 998 | enum { |
| 999 | mdp_rgb_lut_gc, |
| 1000 | mdp_rgb_lut_hist, |
| 1001 | }; |
| 1002 | |
| 1003 | struct mdp_lut_cfg_data { |
| 1004 | uint32_t lut_type; |
| 1005 | union { |
| 1006 | struct mdp_igc_lut_data igc_lut_data; |
| 1007 | struct mdp_pgc_lut_data pgc_lut_data; |
| 1008 | struct mdp_hist_lut_data hist_lut_data; |
| 1009 | struct mdp_rgb_lut_data rgb_lut_data; |
| 1010 | } data; |
| 1011 | }; |
| 1012 | |
| 1013 | struct mdp_bl_scale_data { |
| 1014 | uint32_t min_lvl; |
| 1015 | uint32_t scale; |
| 1016 | }; |
| 1017 | |
| 1018 | struct mdp_pa_cfg_data { |
| 1019 | uint32_t block; |
| 1020 | struct mdp_pa_cfg pa_data; |
| 1021 | }; |
| 1022 | |
| 1023 | #define MDP_DITHER_DATA_V1_7_SZ 16 |
| 1024 | |
| 1025 | struct mdp_dither_data_v1_7 { |
| 1026 | uint32_t g_y_depth; |
| 1027 | uint32_t r_cr_depth; |
| 1028 | uint32_t b_cb_depth; |
| 1029 | uint32_t len; |
| 1030 | uint32_t data[MDP_DITHER_DATA_V1_7_SZ]; |
| 1031 | uint32_t temporal_en; |
| 1032 | }; |
| 1033 | |
| 1034 | struct mdp_pa_dither_data { |
| 1035 | uint64_t data_flags; |
| 1036 | uint32_t matrix_sz; |
| 1037 | uint64_t __user matrix_data; |
| 1038 | uint32_t strength; |
| 1039 | uint32_t offset_en; |
| 1040 | }; |
| 1041 | |
| 1042 | struct mdp_dither_cfg_data { |
| 1043 | uint32_t version; |
| 1044 | uint32_t block; |
| 1045 | uint32_t flags; |
| 1046 | uint32_t mode; |
| 1047 | uint32_t g_y_depth; |
| 1048 | uint32_t r_cr_depth; |
| 1049 | uint32_t b_cb_depth; |
| 1050 | void *cfg_payload; |
| 1051 | }; |
| 1052 | |
| 1053 | #define MDP_GAMUT_TABLE_NUM 8 |
| 1054 | #define MDP_GAMUT_TABLE_NUM_V1_7 4 |
| 1055 | #define MDP_GAMUT_SCALE_OFF_TABLE_NUM 3 |
| 1056 | #define MDP_GAMUT_TABLE_V1_7_SZ 1229 |
| 1057 | #define MDP_GAMUT_SCALE_OFF_SZ 16 |
| 1058 | #define MDP_GAMUT_TABLE_V1_7_COARSE_SZ 32 |
| 1059 | |
| 1060 | struct mdp_gamut_cfg_data { |
| 1061 | uint32_t block; |
| 1062 | uint32_t flags; |
| 1063 | uint32_t version; |
| 1064 | /* v1 version specific params */ |
| 1065 | uint32_t gamut_first; |
| 1066 | uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; |
| 1067 | uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM]; |
| 1068 | uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM]; |
| 1069 | uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM]; |
| 1070 | /* params for newer versions of gamut */ |
| 1071 | void *cfg_payload; |
| 1072 | }; |
| 1073 | |
| 1074 | enum { |
| 1075 | mdp_gamut_fine_mode = 0x1, |
| 1076 | mdp_gamut_coarse_mode, |
| 1077 | }; |
| 1078 | |
| 1079 | struct mdp_gamut_data_v1_7 { |
| 1080 | uint32_t mode; |
| 1081 | uint32_t map_en; |
| 1082 | uint32_t tbl_size[MDP_GAMUT_TABLE_NUM_V1_7]; |
| 1083 | uint32_t *c0_data[MDP_GAMUT_TABLE_NUM_V1_7]; |
| 1084 | uint32_t *c1_c2_data[MDP_GAMUT_TABLE_NUM_V1_7]; |
| 1085 | uint32_t tbl_scale_off_sz[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; |
| 1086 | uint32_t *scale_off_data[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; |
| 1087 | }; |
| 1088 | |
| 1089 | struct mdp_calib_config_data { |
| 1090 | uint32_t ops; |
| 1091 | uint32_t addr; |
| 1092 | uint32_t data; |
| 1093 | }; |
| 1094 | |
| 1095 | struct mdp_calib_config_buffer { |
| 1096 | uint32_t ops; |
| 1097 | uint32_t size; |
| 1098 | uint32_t *buffer; |
| 1099 | }; |
| 1100 | |
| 1101 | struct mdp_calib_dcm_state { |
| 1102 | uint32_t ops; |
| 1103 | uint32_t dcm_state; |
| 1104 | }; |
| 1105 | |
| 1106 | enum { |
| 1107 | DCM_UNINIT, |
| 1108 | DCM_UNBLANK, |
| 1109 | DCM_ENTER, |
| 1110 | DCM_EXIT, |
| 1111 | DCM_BLANK, |
| 1112 | DTM_ENTER, |
| 1113 | DTM_EXIT, |
| 1114 | }; |
| 1115 | |
| 1116 | #define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 |
| 1117 | #define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 |
| 1118 | #define MDSS_PP_SPLIT_MASK 0x30000000 |
| 1119 | |
| 1120 | #define MDSS_MAX_BL_BRIGHTNESS 255 |
| 1121 | #define AD_BL_LIN_LEN 256 |
| 1122 | #define AD_BL_ATT_LUT_LEN 33 |
| 1123 | |
| 1124 | #define MDSS_AD_MODE_AUTO_BL 0x0 |
| 1125 | #define MDSS_AD_MODE_AUTO_STR 0x1 |
| 1126 | #define MDSS_AD_MODE_TARG_STR 0x3 |
| 1127 | #define MDSS_AD_MODE_MAN_STR 0x7 |
| 1128 | #define MDSS_AD_MODE_CALIB 0xF |
| 1129 | |
| 1130 | #define MDP_PP_AD_INIT 0x10 |
| 1131 | #define MDP_PP_AD_CFG 0x20 |
| 1132 | |
| 1133 | struct mdss_ad_init { |
| 1134 | uint32_t asym_lut[33]; |
| 1135 | uint32_t color_corr_lut[33]; |
| 1136 | uint8_t i_control[2]; |
| 1137 | uint16_t black_lvl; |
| 1138 | uint16_t white_lvl; |
| 1139 | uint8_t var; |
| 1140 | uint8_t limit_ampl; |
| 1141 | uint8_t i_dither; |
| 1142 | uint8_t slope_max; |
| 1143 | uint8_t slope_min; |
| 1144 | uint8_t dither_ctl; |
| 1145 | uint8_t format; |
| 1146 | uint8_t auto_size; |
| 1147 | uint16_t frame_w; |
| 1148 | uint16_t frame_h; |
| 1149 | uint8_t logo_v; |
| 1150 | uint8_t logo_h; |
| 1151 | uint32_t alpha; |
| 1152 | uint32_t alpha_base; |
| 1153 | uint32_t al_thresh; |
| 1154 | uint32_t bl_lin_len; |
| 1155 | uint32_t bl_att_len; |
| 1156 | uint32_t *bl_lin; |
| 1157 | uint32_t *bl_lin_inv; |
| 1158 | uint32_t *bl_att_lut; |
| 1159 | }; |
| 1160 | |
| 1161 | #define MDSS_AD_BL_CTRL_MODE_EN 1 |
| 1162 | #define MDSS_AD_BL_CTRL_MODE_DIS 0 |
| 1163 | struct mdss_ad_cfg { |
| 1164 | uint32_t mode; |
| 1165 | uint32_t al_calib_lut[33]; |
| 1166 | uint16_t backlight_min; |
| 1167 | uint16_t backlight_max; |
| 1168 | uint16_t backlight_scale; |
| 1169 | uint16_t amb_light_min; |
| 1170 | uint16_t filter[2]; |
| 1171 | uint16_t calib[4]; |
| 1172 | uint8_t strength_limit; |
| 1173 | uint8_t t_filter_recursion; |
| 1174 | uint16_t stab_itr; |
| 1175 | uint32_t bl_ctrl_mode; |
| 1176 | }; |
| 1177 | |
| 1178 | struct mdss_ad_bl_cfg { |
| 1179 | uint32_t bl_min_delta; |
| 1180 | uint32_t bl_low_limit; |
| 1181 | }; |
| 1182 | |
| 1183 | /* ops uses standard MDP_PP_* flags */ |
| 1184 | struct mdss_ad_init_cfg { |
| 1185 | uint32_t ops; |
| 1186 | union { |
| 1187 | struct mdss_ad_init init; |
| 1188 | struct mdss_ad_cfg cfg; |
| 1189 | } params; |
| 1190 | }; |
| 1191 | |
| 1192 | /* mode uses MDSS_AD_MODE_* flags */ |
| 1193 | struct mdss_ad_input { |
| 1194 | uint32_t mode; |
| 1195 | union { |
| 1196 | uint32_t amb_light; |
| 1197 | uint32_t strength; |
| 1198 | uint32_t calib_bl; |
| 1199 | } in; |
| 1200 | uint32_t output; |
| 1201 | }; |
| 1202 | |
| 1203 | #define MDSS_CALIB_MODE_BL 0x1 |
| 1204 | struct mdss_calib_cfg { |
| 1205 | uint32_t ops; |
| 1206 | uint32_t calib_mask; |
| 1207 | }; |
| 1208 | |
| 1209 | enum { |
| 1210 | mdp_op_pcc_cfg, |
| 1211 | mdp_op_csc_cfg, |
| 1212 | mdp_op_lut_cfg, |
| 1213 | mdp_op_qseed_cfg, |
| 1214 | mdp_bl_scale_cfg, |
| 1215 | mdp_op_pa_cfg, |
| 1216 | mdp_op_pa_v2_cfg, |
| 1217 | mdp_op_dither_cfg, |
| 1218 | mdp_op_gamut_cfg, |
| 1219 | mdp_op_calib_cfg, |
| 1220 | mdp_op_ad_cfg, |
| 1221 | mdp_op_ad_input, |
| 1222 | mdp_op_calib_mode, |
| 1223 | mdp_op_calib_buffer, |
| 1224 | mdp_op_calib_dcm_state, |
| 1225 | mdp_op_max, |
| 1226 | mdp_op_pa_dither_cfg, |
| 1227 | mdp_op_ad_bl_cfg, |
| 1228 | mdp_op_pp_max = 255, |
| 1229 | }; |
| 1230 | #define mdp_op_pa_dither_cfg mdp_op_pa_dither_cfg |
| 1231 | #define mdp_op_pp_max mdp_op_pp_max |
| 1232 | |
| 1233 | #define mdp_op_ad_bl_cfg mdp_op_ad_bl_cfg |
| 1234 | |
| 1235 | enum { |
| 1236 | WB_FORMAT_NV12, |
| 1237 | WB_FORMAT_RGB_565, |
| 1238 | WB_FORMAT_RGB_888, |
| 1239 | WB_FORMAT_xRGB_8888, |
| 1240 | WB_FORMAT_ARGB_8888, |
| 1241 | WB_FORMAT_BGRA_8888, |
| 1242 | WB_FORMAT_BGRX_8888, |
| 1243 | WB_FORMAT_ARGB_8888_INPUT_ALPHA /* Need to support */ |
| 1244 | }; |
| 1245 | |
| 1246 | struct msmfb_mdp_pp { |
| 1247 | uint32_t op; |
| 1248 | union { |
| 1249 | struct mdp_pcc_cfg_data pcc_cfg_data; |
| 1250 | struct mdp_csc_cfg_data csc_cfg_data; |
| 1251 | struct mdp_lut_cfg_data lut_cfg_data; |
| 1252 | struct mdp_qseed_cfg_data qseed_cfg_data; |
| 1253 | struct mdp_bl_scale_data bl_scale_data; |
| 1254 | struct mdp_pa_cfg_data pa_cfg_data; |
| 1255 | struct mdp_pa_v2_cfg_data pa_v2_cfg_data; |
| 1256 | struct mdp_dither_cfg_data dither_cfg_data; |
| 1257 | struct mdp_gamut_cfg_data gamut_cfg_data; |
| 1258 | struct mdp_calib_config_data calib_cfg; |
| 1259 | struct mdss_ad_init_cfg ad_init_cfg; |
| 1260 | struct mdss_calib_cfg mdss_calib_cfg; |
| 1261 | struct mdss_ad_input ad_input; |
| 1262 | struct mdp_calib_config_buffer calib_buffer; |
| 1263 | struct mdp_calib_dcm_state calib_dcm; |
| 1264 | struct mdss_ad_bl_cfg ad_bl_cfg; |
| 1265 | } data; |
| 1266 | }; |
| 1267 | |
| 1268 | #define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 |
| 1269 | enum { |
| 1270 | metadata_op_none, |
| 1271 | metadata_op_base_blend, |
| 1272 | metadata_op_frame_rate, |
| 1273 | metadata_op_vic, |
| 1274 | metadata_op_wb_format, |
| 1275 | metadata_op_wb_secure, |
| 1276 | metadata_op_get_caps, |
| 1277 | metadata_op_crc, |
| 1278 | metadata_op_get_ion_fd, |
Krishna Manikandan | 695632e | 2020-03-04 20:50:28 +0530 | [diff] [blame] | 1279 | metadata_op_secure_bl_set, |
| 1280 | metadata_op_secure_reg, |
Bruce Levy | 73944ad | 2017-03-10 15:56:41 -0800 | [diff] [blame] | 1281 | metadata_op_max |
| 1282 | }; |
| 1283 | |
| 1284 | struct mdp_blend_cfg { |
| 1285 | uint32_t is_premultiplied; |
| 1286 | }; |
| 1287 | |
| 1288 | struct mdp_mixer_cfg { |
| 1289 | uint32_t writeback_format; |
| 1290 | uint32_t alpha; |
| 1291 | }; |
| 1292 | |
| 1293 | struct mdss_hw_caps { |
| 1294 | uint32_t mdp_rev; |
| 1295 | uint8_t rgb_pipes; |
| 1296 | uint8_t vig_pipes; |
| 1297 | uint8_t dma_pipes; |
| 1298 | uint8_t max_smp_cnt; |
| 1299 | uint8_t smp_per_pipe; |
| 1300 | uint32_t features; |
| 1301 | }; |
| 1302 | |
| 1303 | struct msmfb_metadata { |
| 1304 | uint32_t op; |
| 1305 | uint32_t flags; |
| 1306 | union { |
| 1307 | struct mdp_misr misr_request; |
| 1308 | struct mdp_blend_cfg blend_cfg; |
| 1309 | struct mdp_mixer_cfg mixer_cfg; |
| 1310 | uint32_t panel_frame_rate; |
| 1311 | uint32_t video_info_code; |
| 1312 | struct mdss_hw_caps caps; |
| 1313 | uint8_t secure_en; |
| 1314 | int fbmem_ionfd; |
Krishna Manikandan | 695632e | 2020-03-04 20:50:28 +0530 | [diff] [blame] | 1315 | bool sec_bl_update_en; |
| 1316 | bool sec_reg_on; |
Bruce Levy | 73944ad | 2017-03-10 15:56:41 -0800 | [diff] [blame] | 1317 | } data; |
| 1318 | }; |
| 1319 | |
| 1320 | #define MDP_MAX_FENCE_FD 32 |
| 1321 | #define MDP_BUF_SYNC_FLAG_WAIT 1 |
| 1322 | #define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 |
| 1323 | |
| 1324 | struct mdp_buf_sync { |
| 1325 | uint32_t flags; |
| 1326 | uint32_t acq_fen_fd_cnt; |
| 1327 | uint32_t session_id; |
| 1328 | int *acq_fen_fd; |
| 1329 | int *rel_fen_fd; |
| 1330 | int *retire_fen_fd; |
| 1331 | }; |
| 1332 | |
| 1333 | struct mdp_async_blit_req_list { |
| 1334 | struct mdp_buf_sync sync; |
| 1335 | uint32_t count; |
| 1336 | struct mdp_blit_req req[]; |
| 1337 | }; |
| 1338 | |
| 1339 | #define MDP_DISPLAY_COMMIT_OVERLAY 1 |
| 1340 | |
| 1341 | struct mdp_display_commit { |
| 1342 | uint32_t flags; |
| 1343 | uint32_t wait_for_finish; |
| 1344 | struct fb_var_screeninfo var; |
| 1345 | /* |
| 1346 | * user needs to follow guidelines as per below rules |
| 1347 | * 1. source split is enabled: l_roi = roi and r_roi = 0 |
| 1348 | * 2. source split is disabled: |
| 1349 | * 2.1 split display: l_roi = l_roi and r_roi = r_roi |
| 1350 | * 2.2 non split display: l_roi = roi and r_roi = 0 |
| 1351 | */ |
| 1352 | struct mdp_rect l_roi; |
| 1353 | struct mdp_rect r_roi; |
| 1354 | }; |
| 1355 | |
| 1356 | /** |
| 1357 | * struct mdp_overlay_list - argument for ioctl MSMFB_OVERLAY_PREPARE |
| 1358 | * @num_overlays: Number of overlay layers as part of the frame. |
| 1359 | * @overlay_list: Pointer to a list of overlay structures identifying |
| 1360 | * the layers as part of the frame |
| 1361 | * @flags: Flags can be used to extend behavior. |
| 1362 | * @processed_overlays: Output parameter indicating how many pipes were |
| 1363 | * successful. If there are no errors this number should |
| 1364 | * match num_overlays. Otherwise it will indicate the last |
| 1365 | * successful index for overlay that couldn't be set. |
| 1366 | */ |
| 1367 | struct mdp_overlay_list { |
| 1368 | uint32_t num_overlays; |
| 1369 | struct mdp_overlay **overlay_list; |
| 1370 | uint32_t flags; |
| 1371 | uint32_t processed_overlays; |
| 1372 | }; |
| 1373 | |
| 1374 | struct mdp_page_protection { |
| 1375 | uint32_t page_protection; |
| 1376 | }; |
| 1377 | |
| 1378 | |
| 1379 | struct mdp_mixer_info { |
| 1380 | int pndx; |
| 1381 | int pnum; |
| 1382 | int ptype; |
| 1383 | int mixer_num; |
| 1384 | int z_order; |
| 1385 | }; |
| 1386 | |
| 1387 | #define MAX_PIPE_PER_MIXER 7 |
| 1388 | |
| 1389 | struct msmfb_mixer_info_req { |
| 1390 | int mixer_num; |
| 1391 | int cnt; |
| 1392 | struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; |
| 1393 | }; |
| 1394 | |
| 1395 | enum { |
| 1396 | DISPLAY_SUBSYSTEM_ID, |
| 1397 | ROTATOR_SUBSYSTEM_ID, |
| 1398 | }; |
| 1399 | |
| 1400 | enum { |
| 1401 | MDP_IOMMU_DOMAIN_CP, |
| 1402 | MDP_IOMMU_DOMAIN_NS, |
| 1403 | }; |
| 1404 | |
| 1405 | enum { |
| 1406 | MDP_WRITEBACK_MIRROR_OFF, |
| 1407 | MDP_WRITEBACK_MIRROR_ON, |
| 1408 | MDP_WRITEBACK_MIRROR_PAUSE, |
| 1409 | MDP_WRITEBACK_MIRROR_RESUME, |
| 1410 | }; |
| 1411 | |
| 1412 | enum mdp_color_space { |
| 1413 | MDP_CSC_ITU_R_601, |
| 1414 | MDP_CSC_ITU_R_601_FR, |
| 1415 | MDP_CSC_ITU_R_709, |
| 1416 | }; |
| 1417 | |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 1418 | /* |
| 1419 | * These definitions are a continuation of the mdp_color_space enum above |
| 1420 | */ |
| 1421 | #define MDP_CSC_ITU_R_2020 (MDP_CSC_ITU_R_709 + 1) |
| 1422 | #define MDP_CSC_ITU_R_2020_FR (MDP_CSC_ITU_R_2020 + 1) |
Bruce Levy | 73944ad | 2017-03-10 15:56:41 -0800 | [diff] [blame] | 1423 | enum { |
| 1424 | mdp_igc_v1_7 = 1, |
| 1425 | mdp_igc_vmax, |
| 1426 | mdp_hist_lut_v1_7, |
| 1427 | mdp_hist_lut_vmax, |
| 1428 | mdp_pgc_v1_7, |
| 1429 | mdp_pgc_vmax, |
| 1430 | mdp_dither_v1_7, |
| 1431 | mdp_dither_vmax, |
| 1432 | mdp_gamut_v1_7, |
| 1433 | mdp_gamut_vmax, |
| 1434 | mdp_pa_v1_7, |
| 1435 | mdp_pa_vmax, |
| 1436 | mdp_pcc_v1_7, |
| 1437 | mdp_pcc_vmax, |
| 1438 | mdp_pp_legacy, |
| 1439 | mdp_dither_pa_v1_7, |
| 1440 | mdp_igc_v3, |
| 1441 | mdp_pp_unknown = 255 |
| 1442 | }; |
| 1443 | |
| 1444 | #define mdp_dither_pa_v1_7 mdp_dither_pa_v1_7 |
| 1445 | #define mdp_pp_unknown mdp_pp_unknown |
| 1446 | #define mdp_igc_v3 mdp_igc_v3 |
| 1447 | |
| 1448 | /* PP Features */ |
| 1449 | enum { |
| 1450 | IGC = 1, |
| 1451 | PCC, |
| 1452 | GC, |
| 1453 | PA, |
| 1454 | GAMUT, |
| 1455 | DITHER, |
| 1456 | QSEED, |
| 1457 | HIST_LUT, |
| 1458 | HIST, |
| 1459 | PP_FEATURE_MAX, |
| 1460 | PA_DITHER, |
| 1461 | PP_MAX_FEATURES = 25, |
| 1462 | }; |
| 1463 | |
| 1464 | #define PA_DITHER PA_DITHER |
| 1465 | #define PP_MAX_FEATURES PP_MAX_FEATURES |
| 1466 | |
| 1467 | struct mdp_pp_feature_version { |
| 1468 | uint32_t pp_feature; |
| 1469 | uint32_t version_info; |
| 1470 | }; |
| 1471 | #endif /*_UAPI_MSM_MDP_H_*/ |