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Bard Liaod3cb2de2015-11-09 14:47:34 +08001/*
2 * rt5659.h -- RT5659/RT5658 ALSA SoC audio driver
3 *
4 * Copyright 2015 Realtek Microelectronics
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __RT5659_H__
13#define __RT5659_H__
14
15#include <sound/rt5659.h>
16
17#define DEVICE_ID 0x6311
18
19/* Info */
20#define RT5659_RESET 0x0000
21#define RT5659_VENDOR_ID 0x00fd
22#define RT5659_VENDOR_ID_1 0x00fe
23#define RT5659_DEVICE_ID 0x00ff
24/* I/O - Output */
25#define RT5659_SPO_VOL 0x0001
26#define RT5659_HP_VOL 0x0002
27#define RT5659_LOUT 0x0003
28#define RT5659_MONO_OUT 0x0004
29#define RT5659_HPL_GAIN 0x0005
30#define RT5659_HPR_GAIN 0x0006
31#define RT5659_MONO_GAIN 0x0007
32#define RT5659_SPDIF_CTRL_1 0x0008
33#define RT5659_SPDIF_CTRL_2 0x0009
34/* I/O - Input */
35#define RT5659_CAL_BST_CTRL 0x000a
36#define RT5659_IN1_IN2 0x000c
37#define RT5659_IN3_IN4 0x000d
38#define RT5659_INL1_INR1_VOL 0x000f
39/* I/O - Speaker */
40#define RT5659_EJD_CTRL_1 0x0010
41#define RT5659_EJD_CTRL_2 0x0011
42#define RT5659_EJD_CTRL_3 0x0012
43#define RT5659_SILENCE_CTRL 0x0015
44#define RT5659_PSV_CTRL 0x0016
45/* I/O - Sidetone */
46#define RT5659_SIDETONE_CTRL 0x0018
47/* I/O - ADC/DAC/DMIC */
48#define RT5659_DAC1_DIG_VOL 0x0019
49#define RT5659_DAC2_DIG_VOL 0x001a
50#define RT5659_DAC_CTRL 0x001b
51#define RT5659_STO1_ADC_DIG_VOL 0x001c
52#define RT5659_MONO_ADC_DIG_VOL 0x001d
53#define RT5659_STO2_ADC_DIG_VOL 0x001e
54#define RT5659_STO1_BOOST 0x001f
55#define RT5659_MONO_BOOST 0x0020
56#define RT5659_STO2_BOOST 0x0021
57#define RT5659_HP_IMP_GAIN_1 0x0022
58#define RT5659_HP_IMP_GAIN_2 0x0023
59/* Mixer - D-D */
60#define RT5659_STO1_ADC_MIXER 0x0026
61#define RT5659_MONO_ADC_MIXER 0x0027
62#define RT5659_AD_DA_MIXER 0x0029
63#define RT5659_STO_DAC_MIXER 0x002a
64#define RT5659_MONO_DAC_MIXER 0x002b
65#define RT5659_DIG_MIXER 0x002c
66#define RT5659_A_DAC_MUX 0x002d
67#define RT5659_DIG_INF23_DATA 0x002f
68/* Mixer - PDM */
69#define RT5659_PDM_OUT_CTRL 0x0031
70#define RT5659_PDM_DATA_CTRL_1 0x0032
71#define RT5659_PDM_DATA_CTRL_2 0x0033
72#define RT5659_PDM_DATA_CTRL_3 0x0034
73#define RT5659_PDM_DATA_CTRL_4 0x0035
74#define RT5659_SPDIF_CTRL 0x0036
75
76/* Mixer - ADC */
77#define RT5659_REC1_GAIN 0x003a
78#define RT5659_REC1_L1_MIXER 0x003b
79#define RT5659_REC1_L2_MIXER 0x003c
80#define RT5659_REC1_R1_MIXER 0x003d
81#define RT5659_REC1_R2_MIXER 0x003e
82#define RT5659_CAL_REC 0x0040
83#define RT5659_REC2_L1_MIXER 0x009b
84#define RT5659_REC2_L2_MIXER 0x009c
85#define RT5659_REC2_R1_MIXER 0x009d
86#define RT5659_REC2_R2_MIXER 0x009e
87#define RT5659_RC_CLK_CTRL 0x009f
88/* Mixer - DAC */
89#define RT5659_SPK_L_MIXER 0x0046
90#define RT5659_SPK_R_MIXER 0x0047
91#define RT5659_SPO_AMP_GAIN 0x0048
92#define RT5659_ALC_BACK_GAIN 0x0049
93#define RT5659_MONOMIX_GAIN 0x004a
94#define RT5659_MONOMIX_IN_GAIN 0x004b
95#define RT5659_OUT_L_GAIN 0x004d
96#define RT5659_OUT_L_MIXER 0x004e
97#define RT5659_OUT_R_GAIN 0x004f
98#define RT5659_OUT_R_MIXER 0x0050
99#define RT5659_LOUT_MIXER 0x0052
100
101#define RT5659_HAPTIC_GEN_CTRL_1 0x0053
102#define RT5659_HAPTIC_GEN_CTRL_2 0x0054
103#define RT5659_HAPTIC_GEN_CTRL_3 0x0055
104#define RT5659_HAPTIC_GEN_CTRL_4 0x0056
105#define RT5659_HAPTIC_GEN_CTRL_5 0x0057
106#define RT5659_HAPTIC_GEN_CTRL_6 0x0058
107#define RT5659_HAPTIC_GEN_CTRL_7 0x0059
108#define RT5659_HAPTIC_GEN_CTRL_8 0x005a
109#define RT5659_HAPTIC_GEN_CTRL_9 0x005b
110#define RT5659_HAPTIC_GEN_CTRL_10 0x005c
111#define RT5659_HAPTIC_GEN_CTRL_11 0x005d
112#define RT5659_HAPTIC_LPF_CTRL_1 0x005e
113#define RT5659_HAPTIC_LPF_CTRL_2 0x005f
114#define RT5659_HAPTIC_LPF_CTRL_3 0x0060
115/* Power */
116#define RT5659_PWR_DIG_1 0x0061
117#define RT5659_PWR_DIG_2 0x0062
118#define RT5659_PWR_ANLG_1 0x0063
119#define RT5659_PWR_ANLG_2 0x0064
120#define RT5659_PWR_ANLG_3 0x0065
121#define RT5659_PWR_MIXER 0x0066
122#define RT5659_PWR_VOL 0x0067
123/* Private Register Control */
124#define RT5659_PRIV_INDEX 0x006a
125#define RT5659_CLK_DET 0x006b
126#define RT5659_PRIV_DATA 0x006c
127/* System Clock Pre Divider Gating Control */
128#define RT5659_PRE_DIV_1 0x006e
129#define RT5659_PRE_DIV_2 0x006f
130/* Format - ADC/DAC */
131#define RT5659_I2S1_SDP 0x0070
132#define RT5659_I2S2_SDP 0x0071
133#define RT5659_I2S3_SDP 0x0072
134#define RT5659_ADDA_CLK_1 0x0073
135#define RT5659_ADDA_CLK_2 0x0074
136#define RT5659_DMIC_CTRL_1 0x0075
137#define RT5659_DMIC_CTRL_2 0x0076
138/* Format - TDM Control */
139#define RT5659_TDM_CTRL_1 0x0077
140#define RT5659_TDM_CTRL_2 0x0078
141#define RT5659_TDM_CTRL_3 0x0079
142#define RT5659_TDM_CTRL_4 0x007a
143#define RT5659_TDM_CTRL_5 0x007b
144
145/* Function - Analog */
146#define RT5659_GLB_CLK 0x0080
147#define RT5659_PLL_CTRL_1 0x0081
148#define RT5659_PLL_CTRL_2 0x0082
149#define RT5659_ASRC_1 0x0083
150#define RT5659_ASRC_2 0x0084
151#define RT5659_ASRC_3 0x0085
152#define RT5659_ASRC_4 0x0086
153#define RT5659_ASRC_5 0x0087
154#define RT5659_ASRC_6 0x0088
155#define RT5659_ASRC_7 0x0089
156#define RT5659_ASRC_8 0x008a
157#define RT5659_ASRC_9 0x008b
158#define RT5659_ASRC_10 0x008c
159#define RT5659_DEPOP_1 0x008e
160#define RT5659_DEPOP_2 0x008f
161#define RT5659_DEPOP_3 0x0090
162#define RT5659_HP_CHARGE_PUMP_1 0x0091
163#define RT5659_HP_CHARGE_PUMP_2 0x0092
164#define RT5659_MICBIAS_1 0x0093
165#define RT5659_MICBIAS_2 0x0094
166#define RT5659_ASRC_11 0x0097
167#define RT5659_ASRC_12 0x0098
168#define RT5659_ASRC_13 0x0099
169#define RT5659_REC_M1_M2_GAIN_CTRL 0x009a
170#define RT5659_CLASSD_CTRL_1 0x00a0
171#define RT5659_CLASSD_CTRL_2 0x00a1
172
173/* Function - Digital */
174#define RT5659_ADC_EQ_CTRL_1 0x00ae
175#define RT5659_ADC_EQ_CTRL_2 0x00af
176#define RT5659_DAC_EQ_CTRL_1 0x00b0
177#define RT5659_DAC_EQ_CTRL_2 0x00b1
178#define RT5659_DAC_EQ_CTRL_3 0x00b2
179
180#define RT5659_IRQ_CTRL_1 0x00b6
181#define RT5659_IRQ_CTRL_2 0x00b7
182#define RT5659_IRQ_CTRL_3 0x00b8
Nicolin Chen8cc12362016-08-24 11:00:27 -0700183#define RT5659_IRQ_CTRL_4 0x00ba
184#define RT5659_IRQ_CTRL_5 0x00bb
185#define RT5659_IRQ_CTRL_6 0x00bc
Bard Liaod3cb2de2015-11-09 14:47:34 +0800186#define RT5659_INT_ST_1 0x00be
187#define RT5659_INT_ST_2 0x00bf
188#define RT5659_GPIO_CTRL_1 0x00c0
189#define RT5659_GPIO_CTRL_2 0x00c1
190#define RT5659_GPIO_CTRL_3 0x00c2
191#define RT5659_GPIO_CTRL_4 0x00c3
192#define RT5659_GPIO_CTRL_5 0x00c4
193#define RT5659_GPIO_STA 0x00c5
194#define RT5659_SINE_GEN_CTRL_1 0x00cb
195#define RT5659_SINE_GEN_CTRL_2 0x00cc
196#define RT5659_SINE_GEN_CTRL_3 0x00cd
197#define RT5659_HP_AMP_DET_CTRL_1 0x00d6
198#define RT5659_HP_AMP_DET_CTRL_2 0x00d7
199#define RT5659_SV_ZCD_1 0x00d9
200#define RT5659_SV_ZCD_2 0x00da
201#define RT5659_IL_CMD_1 0x00db
202#define RT5659_IL_CMD_2 0x00dc
203#define RT5659_IL_CMD_3 0x00dd
204#define RT5659_IL_CMD_4 0x00de
205#define RT5659_4BTN_IL_CMD_1 0x00df
206#define RT5659_4BTN_IL_CMD_2 0x00e0
207#define RT5659_4BTN_IL_CMD_3 0x00e1
208#define RT5659_PSV_IL_CMD_1 0x00e4
209#define RT5659_PSV_IL_CMD_2 0x00e5
210
211#define RT5659_ADC_STO1_HP_CTRL_1 0x00ea
212#define RT5659_ADC_STO1_HP_CTRL_2 0x00eb
213#define RT5659_ADC_MONO_HP_CTRL_1 0x00ec
214#define RT5659_ADC_MONO_HP_CTRL_2 0x00ed
215#define RT5659_AJD1_CTRL 0x00f0
216#define RT5659_AJD2_AJD3_CTRL 0x00f1
217#define RT5659_JD1_THD 0x00f2
218#define RT5659_JD2_THD 0x00f3
219#define RT5659_JD3_THD 0x00f4
220#define RT5659_JD_CTRL_1 0x00f6
221#define RT5659_JD_CTRL_2 0x00f7
222#define RT5659_JD_CTRL_3 0x00f8
223#define RT5659_JD_CTRL_4 0x00f9
224/* General Control */
225#define RT5659_DIG_MISC 0x00fa
226#define RT5659_DUMMY_2 0x00fb
227#define RT5659_DUMMY_3 0x00fc
228
229#define RT5659_DAC_ADC_DIG_VOL 0x0100
230#define RT5659_BIAS_CUR_CTRL_1 0x010a
231#define RT5659_BIAS_CUR_CTRL_2 0x010b
232#define RT5659_BIAS_CUR_CTRL_3 0x010c
233#define RT5659_BIAS_CUR_CTRL_4 0x010d
234#define RT5659_BIAS_CUR_CTRL_5 0x010e
235#define RT5659_BIAS_CUR_CTRL_6 0x010f
236#define RT5659_BIAS_CUR_CTRL_7 0x0110
237#define RT5659_BIAS_CUR_CTRL_8 0x0111
238#define RT5659_BIAS_CUR_CTRL_9 0x0112
239#define RT5659_BIAS_CUR_CTRL_10 0x0113
240#define RT5659_MEMORY_TEST 0x0116
241#define RT5659_VREF_REC_OP_FB_CAP_CTRL 0x0117
242#define RT5659_CLASSD_0 0x011a
243#define RT5659_CLASSD_1 0x011b
244#define RT5659_CLASSD_2 0x011c
245#define RT5659_CLASSD_3 0x011d
246#define RT5659_CLASSD_4 0x011e
247#define RT5659_CLASSD_5 0x011f
248#define RT5659_CLASSD_6 0x0120
249#define RT5659_CLASSD_7 0x0121
250#define RT5659_CLASSD_8 0x0122
251#define RT5659_CLASSD_9 0x0123
252#define RT5659_CLASSD_10 0x0124
253#define RT5659_CHARGE_PUMP_1 0x0125
254#define RT5659_CHARGE_PUMP_2 0x0126
255#define RT5659_DIG_IN_CTRL_1 0x0132
256#define RT5659_DIG_IN_CTRL_2 0x0133
257#define RT5659_PAD_DRIVING_CTRL 0x0137
258#define RT5659_SOFT_RAMP_DEPOP 0x0138
259#define RT5659_PLL 0x0139
260#define RT5659_CHOP_DAC 0x013a
261#define RT5659_CHOP_ADC 0x013b
262#define RT5659_CALIB_ADC_CTRL 0x013c
263#define RT5659_SOFT_RAMP_DEPOP_DAC_CLK_CTRL 0x013e
264#define RT5659_VOL_TEST 0x013f
265#define RT5659_TEST_MODE_CTRL_1 0x0145
266#define RT5659_TEST_MODE_CTRL_2 0x0146
267#define RT5659_TEST_MODE_CTRL_3 0x0147
268#define RT5659_TEST_MODE_CTRL_4 0x0148
269#define RT5659_BASSBACK_CTRL 0x0150
270#define RT5659_MP3_PLUS_CTRL_1 0x0151
271#define RT5659_MP3_PLUS_CTRL_2 0x0152
272#define RT5659_MP3_HPF_A1 0x0153
273#define RT5659_MP3_HPF_A2 0x0154
274#define RT5659_MP3_HPF_H0 0x0155
275#define RT5659_MP3_LPF_H0 0x0156
276#define RT5659_3D_SPK_CTRL 0x0157
277#define RT5659_3D_SPK_COEF_1 0x0158
278#define RT5659_3D_SPK_COEF_2 0x0159
279#define RT5659_3D_SPK_COEF_3 0x015a
280#define RT5659_3D_SPK_COEF_4 0x015b
281#define RT5659_3D_SPK_COEF_5 0x015c
282#define RT5659_3D_SPK_COEF_6 0x015d
283#define RT5659_3D_SPK_COEF_7 0x015e
284#define RT5659_STO_NG2_CTRL_1 0x0160
285#define RT5659_STO_NG2_CTRL_2 0x0161
286#define RT5659_STO_NG2_CTRL_3 0x0162
287#define RT5659_STO_NG2_CTRL_4 0x0163
288#define RT5659_STO_NG2_CTRL_5 0x0164
289#define RT5659_STO_NG2_CTRL_6 0x0165
290#define RT5659_STO_NG2_CTRL_7 0x0166
291#define RT5659_STO_NG2_CTRL_8 0x0167
292#define RT5659_MONO_NG2_CTRL_1 0x0170
293#define RT5659_MONO_NG2_CTRL_2 0x0171
294#define RT5659_MONO_NG2_CTRL_3 0x0172
295#define RT5659_MONO_NG2_CTRL_4 0x0173
296#define RT5659_MONO_NG2_CTRL_5 0x0174
297#define RT5659_MONO_NG2_CTRL_6 0x0175
298#define RT5659_MID_HP_AMP_DET 0x0190
299#define RT5659_LOW_HP_AMP_DET 0x0191
300#define RT5659_LDO_CTRL 0x0192
301#define RT5659_HP_DECROSS_CTRL_1 0x01b0
302#define RT5659_HP_DECROSS_CTRL_2 0x01b1
303#define RT5659_HP_DECROSS_CTRL_3 0x01b2
304#define RT5659_HP_DECROSS_CTRL_4 0x01b3
305#define RT5659_HP_IMP_SENS_CTRL_1 0x01c0
306#define RT5659_HP_IMP_SENS_CTRL_2 0x01c1
307#define RT5659_HP_IMP_SENS_CTRL_3 0x01c2
308#define RT5659_HP_IMP_SENS_CTRL_4 0x01c3
309#define RT5659_HP_IMP_SENS_MAP_1 0x01c7
310#define RT5659_HP_IMP_SENS_MAP_2 0x01c8
311#define RT5659_HP_IMP_SENS_MAP_3 0x01c9
312#define RT5659_HP_IMP_SENS_MAP_4 0x01ca
313#define RT5659_HP_IMP_SENS_MAP_5 0x01cb
314#define RT5659_HP_IMP_SENS_MAP_6 0x01cc
315#define RT5659_HP_IMP_SENS_MAP_7 0x01cd
316#define RT5659_HP_IMP_SENS_MAP_8 0x01ce
317#define RT5659_HP_LOGIC_CTRL_1 0x01da
318#define RT5659_HP_LOGIC_CTRL_2 0x01db
319#define RT5659_HP_CALIB_CTRL_1 0x01de
320#define RT5659_HP_CALIB_CTRL_2 0x01df
321#define RT5659_HP_CALIB_CTRL_3 0x01e0
322#define RT5659_HP_CALIB_CTRL_4 0x01e1
323#define RT5659_HP_CALIB_CTRL_5 0x01e2
324#define RT5659_HP_CALIB_CTRL_6 0x01e3
325#define RT5659_HP_CALIB_CTRL_7 0x01e4
326#define RT5659_HP_CALIB_CTRL_9 0x01e6
327#define RT5659_HP_CALIB_CTRL_10 0x01e7
328#define RT5659_HP_CALIB_CTRL_11 0x01e8
329#define RT5659_HP_CALIB_STA_1 0x01ea
330#define RT5659_HP_CALIB_STA_2 0x01eb
331#define RT5659_HP_CALIB_STA_3 0x01ec
332#define RT5659_HP_CALIB_STA_4 0x01ed
333#define RT5659_HP_CALIB_STA_5 0x01ee
334#define RT5659_HP_CALIB_STA_6 0x01ef
335#define RT5659_HP_CALIB_STA_7 0x01f0
336#define RT5659_HP_CALIB_STA_8 0x01f1
337#define RT5659_HP_CALIB_STA_9 0x01f2
338#define RT5659_MONO_AMP_CALIB_CTRL_1 0x01f6
339#define RT5659_MONO_AMP_CALIB_CTRL_2 0x01f7
340#define RT5659_MONO_AMP_CALIB_CTRL_3 0x01f8
341#define RT5659_MONO_AMP_CALIB_CTRL_4 0x01f9
342#define RT5659_MONO_AMP_CALIB_CTRL_5 0x01fa
343#define RT5659_MONO_AMP_CALIB_STA_1 0x01fb
344#define RT5659_MONO_AMP_CALIB_STA_2 0x01fc
345#define RT5659_MONO_AMP_CALIB_STA_3 0x01fd
346#define RT5659_MONO_AMP_CALIB_STA_4 0x01fe
347#define RT5659_SPK_PWR_LMT_CTRL_1 0x0200
348#define RT5659_SPK_PWR_LMT_CTRL_2 0x0201
349#define RT5659_SPK_PWR_LMT_CTRL_3 0x0202
350#define RT5659_SPK_PWR_LMT_STA_1 0x0203
351#define RT5659_SPK_PWR_LMT_STA_2 0x0204
352#define RT5659_SPK_PWR_LMT_STA_3 0x0205
353#define RT5659_SPK_PWR_LMT_STA_4 0x0206
354#define RT5659_SPK_PWR_LMT_STA_5 0x0207
355#define RT5659_SPK_PWR_LMT_STA_6 0x0208
356#define RT5659_FLEX_SPK_BST_CTRL_1 0x0256
357#define RT5659_FLEX_SPK_BST_CTRL_2 0x0257
358#define RT5659_FLEX_SPK_BST_CTRL_3 0x0258
359#define RT5659_FLEX_SPK_BST_CTRL_4 0x0259
360#define RT5659_SPK_EX_LMT_CTRL_1 0x025a
361#define RT5659_SPK_EX_LMT_CTRL_2 0x025b
362#define RT5659_SPK_EX_LMT_CTRL_3 0x025c
363#define RT5659_SPK_EX_LMT_CTRL_4 0x025d
364#define RT5659_SPK_EX_LMT_CTRL_5 0x025e
365#define RT5659_SPK_EX_LMT_CTRL_6 0x025f
366#define RT5659_SPK_EX_LMT_CTRL_7 0x0260
367#define RT5659_ADJ_HPF_CTRL_1 0x0261
368#define RT5659_ADJ_HPF_CTRL_2 0x0262
369#define RT5659_SPK_DC_CAILB_CTRL_1 0x0265
370#define RT5659_SPK_DC_CAILB_CTRL_2 0x0266
371#define RT5659_SPK_DC_CAILB_CTRL_3 0x0267
372#define RT5659_SPK_DC_CAILB_CTRL_4 0x0268
373#define RT5659_SPK_DC_CAILB_CTRL_5 0x0269
374#define RT5659_SPK_DC_CAILB_STA_1 0x026a
375#define RT5659_SPK_DC_CAILB_STA_2 0x026b
376#define RT5659_SPK_DC_CAILB_STA_3 0x026c
377#define RT5659_SPK_DC_CAILB_STA_4 0x026d
378#define RT5659_SPK_DC_CAILB_STA_5 0x026e
379#define RT5659_SPK_DC_CAILB_STA_6 0x026f
380#define RT5659_SPK_DC_CAILB_STA_7 0x0270
381#define RT5659_SPK_DC_CAILB_STA_8 0x0271
382#define RT5659_SPK_DC_CAILB_STA_9 0x0272
383#define RT5659_SPK_DC_CAILB_STA_10 0x0273
384#define RT5659_SPK_VDD_STA_1 0x0280
385#define RT5659_SPK_VDD_STA_2 0x0281
386#define RT5659_SPK_DC_DET_CTRL_1 0x0282
387#define RT5659_SPK_DC_DET_CTRL_2 0x0283
388#define RT5659_SPK_DC_DET_CTRL_3 0x0284
389#define RT5659_PURE_DC_DET_CTRL_1 0x0290
390#define RT5659_PURE_DC_DET_CTRL_2 0x0291
391#define RT5659_DUMMY_4 0x02fa
392#define RT5659_DUMMY_5 0x02fb
393#define RT5659_DUMMY_6 0x02fc
394#define RT5659_DRC1_CTRL_1 0x0300
395#define RT5659_DRC1_CTRL_2 0x0301
396#define RT5659_DRC1_CTRL_3 0x0302
397#define RT5659_DRC1_CTRL_4 0x0303
398#define RT5659_DRC1_CTRL_5 0x0304
399#define RT5659_DRC1_CTRL_6 0x0305
400#define RT5659_DRC1_HARD_LMT_CTRL_1 0x0306
401#define RT5659_DRC1_HARD_LMT_CTRL_2 0x0307
402#define RT5659_DRC2_CTRL_1 0x0308
403#define RT5659_DRC2_CTRL_2 0x0309
404#define RT5659_DRC2_CTRL_3 0x030a
405#define RT5659_DRC2_CTRL_4 0x030b
406#define RT5659_DRC2_CTRL_5 0x030c
407#define RT5659_DRC2_CTRL_6 0x030d
408#define RT5659_DRC2_HARD_LMT_CTRL_1 0x030e
409#define RT5659_DRC2_HARD_LMT_CTRL_2 0x030f
410#define RT5659_DRC1_PRIV_1 0x0310
411#define RT5659_DRC1_PRIV_2 0x0311
412#define RT5659_DRC1_PRIV_3 0x0312
413#define RT5659_DRC1_PRIV_4 0x0313
414#define RT5659_DRC1_PRIV_5 0x0314
415#define RT5659_DRC1_PRIV_6 0x0315
416#define RT5659_DRC1_PRIV_7 0x0316
417#define RT5659_DRC2_PRIV_1 0x0317
418#define RT5659_DRC2_PRIV_2 0x0318
419#define RT5659_DRC2_PRIV_3 0x0319
420#define RT5659_DRC2_PRIV_4 0x031a
421#define RT5659_DRC2_PRIV_5 0x031b
422#define RT5659_DRC2_PRIV_6 0x031c
423#define RT5659_DRC2_PRIV_7 0x031d
424#define RT5659_MULTI_DRC_CTRL 0x0320
425#define RT5659_CROSS_OVER_1 0x0321
426#define RT5659_CROSS_OVER_2 0x0322
427#define RT5659_CROSS_OVER_3 0x0323
428#define RT5659_CROSS_OVER_4 0x0324
429#define RT5659_CROSS_OVER_5 0x0325
430#define RT5659_CROSS_OVER_6 0x0326
431#define RT5659_CROSS_OVER_7 0x0327
432#define RT5659_CROSS_OVER_8 0x0328
433#define RT5659_CROSS_OVER_9 0x0329
434#define RT5659_CROSS_OVER_10 0x032a
435#define RT5659_ALC_PGA_CTRL_1 0x0330
436#define RT5659_ALC_PGA_CTRL_2 0x0331
437#define RT5659_ALC_PGA_CTRL_3 0x0332
438#define RT5659_ALC_PGA_CTRL_4 0x0333
439#define RT5659_ALC_PGA_CTRL_5 0x0334
440#define RT5659_ALC_PGA_CTRL_6 0x0335
441#define RT5659_ALC_PGA_CTRL_7 0x0336
442#define RT5659_ALC_PGA_CTRL_8 0x0337
443#define RT5659_ALC_PGA_STA_1 0x0338
444#define RT5659_ALC_PGA_STA_2 0x0339
445#define RT5659_ALC_PGA_STA_3 0x033a
446#define RT5659_DAC_L_EQ_PRE_VOL 0x0340
447#define RT5659_DAC_R_EQ_PRE_VOL 0x0341
448#define RT5659_DAC_L_EQ_POST_VOL 0x0342
449#define RT5659_DAC_R_EQ_POST_VOL 0x0343
450#define RT5659_DAC_L_EQ_LPF1_A1 0x0344
451#define RT5659_DAC_L_EQ_LPF1_H0 0x0345
452#define RT5659_DAC_R_EQ_LPF1_A1 0x0346
453#define RT5659_DAC_R_EQ_LPF1_H0 0x0347
454#define RT5659_DAC_L_EQ_BPF2_A1 0x0348
455#define RT5659_DAC_L_EQ_BPF2_A2 0x0349
456#define RT5659_DAC_L_EQ_BPF2_H0 0x034a
457#define RT5659_DAC_R_EQ_BPF2_A1 0x034b
458#define RT5659_DAC_R_EQ_BPF2_A2 0x034c
459#define RT5659_DAC_R_EQ_BPF2_H0 0x034d
460#define RT5659_DAC_L_EQ_BPF3_A1 0x034e
461#define RT5659_DAC_L_EQ_BPF3_A2 0x034f
462#define RT5659_DAC_L_EQ_BPF3_H0 0x0350
463#define RT5659_DAC_R_EQ_BPF3_A1 0x0351
464#define RT5659_DAC_R_EQ_BPF3_A2 0x0352
465#define RT5659_DAC_R_EQ_BPF3_H0 0x0353
466#define RT5659_DAC_L_EQ_BPF4_A1 0x0354
467#define RT5659_DAC_L_EQ_BPF4_A2 0x0355
468#define RT5659_DAC_L_EQ_BPF4_H0 0x0356
469#define RT5659_DAC_R_EQ_BPF4_A1 0x0357
470#define RT5659_DAC_R_EQ_BPF4_A2 0x0358
471#define RT5659_DAC_R_EQ_BPF4_H0 0x0359
472#define RT5659_DAC_L_EQ_HPF1_A1 0x035a
473#define RT5659_DAC_L_EQ_HPF1_H0 0x035b
474#define RT5659_DAC_R_EQ_HPF1_A1 0x035c
475#define RT5659_DAC_R_EQ_HPF1_H0 0x035d
476#define RT5659_DAC_L_EQ_HPF2_A1 0x035e
477#define RT5659_DAC_L_EQ_HPF2_A2 0x035f
478#define RT5659_DAC_L_EQ_HPF2_H0 0x0360
479#define RT5659_DAC_R_EQ_HPF2_A1 0x0361
480#define RT5659_DAC_R_EQ_HPF2_A2 0x0362
481#define RT5659_DAC_R_EQ_HPF2_H0 0x0363
482#define RT5659_DAC_L_BI_EQ_BPF1_H0_1 0x0364
483#define RT5659_DAC_L_BI_EQ_BPF1_H0_2 0x0365
484#define RT5659_DAC_L_BI_EQ_BPF1_B1_1 0x0366
485#define RT5659_DAC_L_BI_EQ_BPF1_B1_2 0x0367
486#define RT5659_DAC_L_BI_EQ_BPF1_B2_1 0x0368
487#define RT5659_DAC_L_BI_EQ_BPF1_B2_2 0x0369
488#define RT5659_DAC_L_BI_EQ_BPF1_A1_1 0x036a
489#define RT5659_DAC_L_BI_EQ_BPF1_A1_2 0x036b
490#define RT5659_DAC_L_BI_EQ_BPF1_A2_1 0x036c
491#define RT5659_DAC_L_BI_EQ_BPF1_A2_2 0x036d
492#define RT5659_DAC_R_BI_EQ_BPF1_H0_1 0x036e
493#define RT5659_DAC_R_BI_EQ_BPF1_H0_2 0x036f
494#define RT5659_DAC_R_BI_EQ_BPF1_B1_1 0x0370
495#define RT5659_DAC_R_BI_EQ_BPF1_B1_2 0x0371
496#define RT5659_DAC_R_BI_EQ_BPF1_B2_1 0x0372
497#define RT5659_DAC_R_BI_EQ_BPF1_B2_2 0x0373
498#define RT5659_DAC_R_BI_EQ_BPF1_A1_1 0x0374
499#define RT5659_DAC_R_BI_EQ_BPF1_A1_2 0x0375
500#define RT5659_DAC_R_BI_EQ_BPF1_A2_1 0x0376
501#define RT5659_DAC_R_BI_EQ_BPF1_A2_2 0x0377
502#define RT5659_ADC_L_EQ_LPF1_A1 0x03d0
503#define RT5659_ADC_R_EQ_LPF1_A1 0x03d1
504#define RT5659_ADC_L_EQ_LPF1_H0 0x03d2
505#define RT5659_ADC_R_EQ_LPF1_H0 0x03d3
506#define RT5659_ADC_L_EQ_BPF1_A1 0x03d4
507#define RT5659_ADC_R_EQ_BPF1_A1 0x03d5
508#define RT5659_ADC_L_EQ_BPF1_A2 0x03d6
509#define RT5659_ADC_R_EQ_BPF1_A2 0x03d7
510#define RT5659_ADC_L_EQ_BPF1_H0 0x03d8
511#define RT5659_ADC_R_EQ_BPF1_H0 0x03d9
512#define RT5659_ADC_L_EQ_BPF2_A1 0x03da
513#define RT5659_ADC_R_EQ_BPF2_A1 0x03db
514#define RT5659_ADC_L_EQ_BPF2_A2 0x03dc
515#define RT5659_ADC_R_EQ_BPF2_A2 0x03dd
516#define RT5659_ADC_L_EQ_BPF2_H0 0x03de
517#define RT5659_ADC_R_EQ_BPF2_H0 0x03df
518#define RT5659_ADC_L_EQ_BPF3_A1 0x03e0
519#define RT5659_ADC_R_EQ_BPF3_A1 0x03e1
520#define RT5659_ADC_L_EQ_BPF3_A2 0x03e2
521#define RT5659_ADC_R_EQ_BPF3_A2 0x03e3
522#define RT5659_ADC_L_EQ_BPF3_H0 0x03e4
523#define RT5659_ADC_R_EQ_BPF3_H0 0x03e5
524#define RT5659_ADC_L_EQ_BPF4_A1 0x03e6
525#define RT5659_ADC_R_EQ_BPF4_A1 0x03e7
526#define RT5659_ADC_L_EQ_BPF4_A2 0x03e8
527#define RT5659_ADC_R_EQ_BPF4_A2 0x03e9
528#define RT5659_ADC_L_EQ_BPF4_H0 0x03ea
529#define RT5659_ADC_R_EQ_BPF4_H0 0x03eb
530#define RT5659_ADC_L_EQ_HPF1_A1 0x03ec
531#define RT5659_ADC_R_EQ_HPF1_A1 0x03ed
532#define RT5659_ADC_L_EQ_HPF1_H0 0x03ee
533#define RT5659_ADC_R_EQ_HPF1_H0 0x03ef
534#define RT5659_ADC_L_EQ_PRE_VOL 0x03f0
535#define RT5659_ADC_R_EQ_PRE_VOL 0x03f1
536#define RT5659_ADC_L_EQ_POST_VOL 0x03f2
537#define RT5659_ADC_R_EQ_POST_VOL 0x03f3
538
539
540
541/* global definition */
542#define RT5659_L_MUTE (0x1 << 15)
543#define RT5659_L_MUTE_SFT 15
544#define RT5659_VOL_L_MUTE (0x1 << 14)
545#define RT5659_VOL_L_SFT 14
546#define RT5659_R_MUTE (0x1 << 7)
547#define RT5659_R_MUTE_SFT 7
548#define RT5659_VOL_R_MUTE (0x1 << 6)
549#define RT5659_VOL_R_SFT 6
550#define RT5659_L_VOL_MASK (0x3f << 8)
551#define RT5659_L_VOL_SFT 8
552#define RT5659_R_VOL_MASK (0x3f)
553#define RT5659_R_VOL_SFT 0
554
555/*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/
556#define RT5659_G_HP (0x1f << 8)
557#define RT5659_G_HP_SFT 8
558#define RT5659_G_STO_DA_DMIX (0x1f)
559#define RT5659_G_STO_DA_SFT 0
560
561/* IN1/IN2 Control (0x000c) */
562#define RT5659_IN1_DF_MASK (0x1 << 15)
563#define RT5659_IN1_DF 15
564#define RT5659_BST1_MASK (0x7f << 8)
565#define RT5659_BST1_SFT 8
566#define RT5659_BST2_MASK (0x7f)
567#define RT5659_BST2_SFT 0
568
569/* IN3/IN4 Control (0x000d) */
570#define RT5659_IN3_DF_MASK (0x1 << 15)
571#define RT5659_IN3_DF 15
572#define RT5659_BST3_MASK (0x7f << 8)
573#define RT5659_BST3_SFT 8
574#define RT5659_IN4_DF_MASK (0x1 << 7)
575#define RT5659_IN4_DF 7
576#define RT5659_BST4_MASK (0x7f)
577#define RT5659_BST4_SFT 0
578
579/* INL and INR Volume Control (0x000f) */
580#define RT5659_INL_VOL_MASK (0x1f << 8)
581#define RT5659_INL_VOL_SFT 8
582#define RT5659_INR_VOL_MASK (0x1f)
583#define RT5659_INR_VOL_SFT 0
584
585/* Embeeded Jack and Type Detection Control 1 (0x0010) */
586#define RT5659_EMB_JD_EN (0x1 << 15)
587#define RT5659_EMB_JD_EN_SFT 15
588#define RT5659_JD_MODE (0x1 << 13)
589#define RT5659_JD_MODE_SFT 13
590#define RT5659_EXT_JD_EN (0x1 << 11)
591#define RT5659_EXT_JD_EN_SFT 11
592#define RT5659_EXT_JD_DIG (0x1 << 9)
593
594/* Embeeded Jack and Type Detection Control 2 (0x0011) */
595#define RT5659_EXT_JD_SRC (0x7 << 4)
596#define RT5659_EXT_JD_SRC_SFT 4
597#define RT5659_EXT_JD_SRC_GPIO_JD1 (0x0 << 4)
598#define RT5659_EXT_JD_SRC_GPIO_JD2 (0x1 << 4)
599#define RT5659_EXT_JD_SRC_JD1_1 (0x2 << 4)
600#define RT5659_EXT_JD_SRC_JD1_2 (0x3 << 4)
601#define RT5659_EXT_JD_SRC_JD2 (0x4 << 4)
602#define RT5659_EXT_JD_SRC_JD3 (0x5 << 4)
603#define RT5659_EXT_JD_SRC_MANUAL (0x6 << 4)
604
605/* Slience Detection Control (0x0015) */
606#define RT5659_SIL_DET_MASK (0x1 << 15)
607#define RT5659_SIL_DET_DIS (0x0 << 15)
608#define RT5659_SIL_DET_EN (0x1 << 15)
609
610/* Sidetone Control (0x0018) */
611#define RT5659_ST_SEL_MASK (0x7 << 9)
612#define RT5659_ST_SEL_SFT 9
613#define RT5659_ST_EN (0x1 << 6)
614#define RT5659_ST_EN_SFT 6
615
616/* DAC1 Digital Volume (0x0019) */
617#define RT5659_DAC_L1_VOL_MASK (0xff << 8)
618#define RT5659_DAC_L1_VOL_SFT 8
619#define RT5659_DAC_R1_VOL_MASK (0xff)
620#define RT5659_DAC_R1_VOL_SFT 0
621
622/* DAC2 Digital Volume (0x001a) */
623#define RT5659_DAC_L2_VOL_MASK (0xff << 8)
624#define RT5659_DAC_L2_VOL_SFT 8
625#define RT5659_DAC_R2_VOL_MASK (0xff)
626#define RT5659_DAC_R2_VOL_SFT 0
627
628/* DAC2 Control (0x001b) */
629#define RT5659_M_DAC2_L_VOL (0x1 << 13)
630#define RT5659_M_DAC2_L_VOL_SFT 13
631#define RT5659_M_DAC2_R_VOL (0x1 << 12)
632#define RT5659_M_DAC2_R_VOL_SFT 12
633#define RT5659_DAC_L2_SEL_MASK (0x7 << 4)
634#define RT5659_DAC_L2_SEL_SFT 4
635#define RT5659_DAC_R2_SEL_MASK (0x7 << 0)
636#define RT5659_DAC_R2_SEL_SFT 0
637
638/* ADC Digital Volume Control (0x001c) */
639#define RT5659_ADC_L_VOL_MASK (0x7f << 8)
640#define RT5659_ADC_L_VOL_SFT 8
641#define RT5659_ADC_R_VOL_MASK (0x7f)
642#define RT5659_ADC_R_VOL_SFT 0
643
644/* Mono ADC Digital Volume Control (0x001d) */
645#define RT5659_MONO_ADC_L_VOL_MASK (0x7f << 8)
646#define RT5659_MONO_ADC_L_VOL_SFT 8
647#define RT5659_MONO_ADC_R_VOL_MASK (0x7f)
648#define RT5659_MONO_ADC_R_VOL_SFT 0
649
650/* Stereo1 ADC Boost Gain Control (0x001f) */
651#define RT5659_STO1_ADC_L_BST_MASK (0x3 << 14)
652#define RT5659_STO1_ADC_L_BST_SFT 14
653#define RT5659_STO1_ADC_R_BST_MASK (0x3 << 12)
654#define RT5659_STO1_ADC_R_BST_SFT 12
655
656/* Mono ADC Boost Gain Control (0x0020) */
657#define RT5659_MONO_ADC_L_BST_MASK (0x3 << 14)
658#define RT5659_MONO_ADC_L_BST_SFT 14
659#define RT5659_MONO_ADC_R_BST_MASK (0x3 << 12)
660#define RT5659_MONO_ADC_R_BST_SFT 12
661
662/* Stereo1 ADC Boost Gain Control (0x001f) */
663#define RT5659_STO2_ADC_L_BST_MASK (0x3 << 14)
664#define RT5659_STO2_ADC_L_BST_SFT 14
665#define RT5659_STO2_ADC_R_BST_MASK (0x3 << 12)
666#define RT5659_STO2_ADC_R_BST_SFT 12
667
668/* Stereo ADC Mixer Control (0x0026) */
669#define RT5659_M_STO1_ADC_L1 (0x1 << 15)
670#define RT5659_M_STO1_ADC_L1_SFT 15
671#define RT5659_M_STO1_ADC_L2 (0x1 << 14)
672#define RT5659_M_STO1_ADC_L2_SFT 14
673#define RT5659_STO1_ADC1_SRC_MASK (0x1 << 13)
674#define RT5659_STO1_ADC1_SRC_SFT 13
675#define RT5659_STO1_ADC1_SRC_ADC (0x1 << 13)
676#define RT5659_STO1_ADC1_SRC_DACMIX (0x0 << 13)
677#define RT5659_STO1_ADC_SRC_MASK (0x1 << 12)
678#define RT5659_STO1_ADC_SRC_SFT 12
679#define RT5659_STO1_ADC_SRC_ADC1 (0x1 << 12)
680#define RT5659_STO1_ADC_SRC_ADC2 (0x0 << 12)
681#define RT5659_STO1_ADC2_SRC_MASK (0x1 << 11)
682#define RT5659_STO1_ADC2_SRC_SFT 11
683#define RT5659_STO1_DMIC_SRC_MASK (0x1 << 8)
684#define RT5659_STO1_DMIC_SRC_SFT 8
685#define RT5659_STO1_DMIC_SRC_DMIC2 (0x1 << 8)
686#define RT5659_STO1_DMIC_SRC_DMIC1 (0x0 << 8)
687#define RT5659_M_STO1_ADC_R1 (0x1 << 6)
688#define RT5659_M_STO1_ADC_R1_SFT 6
689#define RT5659_M_STO1_ADC_R2 (0x1 << 5)
690#define RT5659_M_STO1_ADC_R2_SFT 5
691
692/* Mono1 ADC Mixer control (0x0027) */
693#define RT5659_M_MONO_ADC_L1 (0x1 << 15)
694#define RT5659_M_MONO_ADC_L1_SFT 15
695#define RT5659_M_MONO_ADC_L2 (0x1 << 14)
696#define RT5659_M_MONO_ADC_L2_SFT 14
697#define RT5659_MONO_ADC_L2_SRC_MASK (0x1 << 12)
698#define RT5659_MONO_ADC_L2_SRC_SFT 12
699#define RT5659_MONO_ADC_L1_SRC_MASK (0x1 << 11)
700#define RT5659_MONO_ADC_L1_SRC_SFT 11
701#define RT5659_MONO_ADC_L_SRC_MASK (0x3 << 9)
702#define RT5659_MONO_ADC_L_SRC_SFT 9
703#define RT5659_MONO_DMIC_L_SRC_MASK (0x1 << 8)
704#define RT5659_MONO_DMIC_L_SRC_SFT 8
705#define RT5659_M_MONO_ADC_R1 (0x1 << 7)
706#define RT5659_M_MONO_ADC_R1_SFT 7
707#define RT5659_M_MONO_ADC_R2 (0x1 << 6)
708#define RT5659_M_MONO_ADC_R2_SFT 6
709#define RT5659_STO2_ADC_SRC_MASK (0x1 << 5)
710#define RT5659_STO2_ADC_SRC_SFT 5
711#define RT5659_MONO_ADC_R2_SRC_MASK (0x1 << 4)
712#define RT5659_MONO_ADC_R2_SRC_SFT 4
713#define RT5659_MONO_ADC_R1_SRC_MASK (0x1 << 3)
714#define RT5659_MONO_ADC_R1_SRC_SFT 3
715#define RT5659_MONO_ADC_R_SRC_MASK (0x3 << 1)
716#define RT5659_MONO_ADC_R_SRC_SFT 1
717#define RT5659_MONO_DMIC_R_SRC_MASK 0x1
718#define RT5659_MONO_DMIC_R_SRC_SFT 0
719
720/* ADC Mixer to DAC Mixer Control (0x0029) */
721#define RT5659_M_ADCMIX_L (0x1 << 15)
722#define RT5659_M_ADCMIX_L_SFT 15
723#define RT5659_M_DAC1_L (0x1 << 14)
724#define RT5659_M_DAC1_L_SFT 14
725#define RT5659_DAC1_R_SEL_MASK (0x3 << 10)
726#define RT5659_DAC1_R_SEL_SFT 10
727#define RT5659_DAC1_R_SEL_IF1 (0x0 << 10)
728#define RT5659_DAC1_R_SEL_IF2 (0x1 << 10)
729#define RT5659_DAC1_R_SEL_IF3 (0x2 << 10)
730#define RT5659_DAC1_L_SEL_MASK (0x3 << 8)
731#define RT5659_DAC1_L_SEL_SFT 8
732#define RT5659_DAC1_L_SEL_IF1 (0x0 << 8)
733#define RT5659_DAC1_L_SEL_IF2 (0x1 << 8)
734#define RT5659_DAC1_L_SEL_IF3 (0x2 << 8)
735#define RT5659_M_ADCMIX_R (0x1 << 7)
736#define RT5659_M_ADCMIX_R_SFT 7
737#define RT5659_M_DAC1_R (0x1 << 6)
738#define RT5659_M_DAC1_R_SFT 6
739
740/* Stereo DAC Mixer Control (0x002a) */
741#define RT5659_M_DAC_L1_STO_L (0x1 << 15)
742#define RT5659_M_DAC_L1_STO_L_SFT 15
743#define RT5659_G_DAC_L1_STO_L_MASK (0x1 << 14)
744#define RT5659_G_DAC_L1_STO_L_SFT 14
745#define RT5659_M_DAC_R1_STO_L (0x1 << 13)
746#define RT5659_M_DAC_R1_STO_L_SFT 13
747#define RT5659_G_DAC_R1_STO_L_MASK (0x1 << 12)
748#define RT5659_G_DAC_R1_STO_L_SFT 12
749#define RT5659_M_DAC_L2_STO_L (0x1 << 11)
750#define RT5659_M_DAC_L2_STO_L_SFT 11
751#define RT5659_G_DAC_L2_STO_L_MASK (0x1 << 10)
752#define RT5659_G_DAC_L2_STO_L_SFT 10
753#define RT5659_M_DAC_R2_STO_L (0x1 << 9)
754#define RT5659_M_DAC_R2_STO_L_SFT 9
755#define RT5659_G_DAC_R2_STO_L_MASK (0x1 << 8)
756#define RT5659_G_DAC_R2_STO_L_SFT 8
757#define RT5659_M_DAC_L1_STO_R (0x1 << 7)
758#define RT5659_M_DAC_L1_STO_R_SFT 7
759#define RT5659_G_DAC_L1_STO_R_MASK (0x1 << 6)
760#define RT5659_G_DAC_L1_STO_R_SFT 6
761#define RT5659_M_DAC_R1_STO_R (0x1 << 5)
762#define RT5659_M_DAC_R1_STO_R_SFT 5
763#define RT5659_G_DAC_R1_STO_R_MASK (0x1 << 4)
764#define RT5659_G_DAC_R1_STO_R_SFT 4
765#define RT5659_M_DAC_L2_STO_R (0x1 << 3)
766#define RT5659_M_DAC_L2_STO_R_SFT 3
767#define RT5659_G_DAC_L2_STO_R_MASK (0x1 << 2)
768#define RT5659_G_DAC_L2_STO_R_SFT 2
769#define RT5659_M_DAC_R2_STO_R (0x1 << 1)
770#define RT5659_M_DAC_R2_STO_R_SFT 1
771#define RT5659_G_DAC_R2_STO_R_MASK (0x1)
772#define RT5659_G_DAC_R2_STO_R_SFT 0
773
774/* Mono DAC Mixer Control (0x002b) */
775#define RT5659_M_DAC_L1_MONO_L (0x1 << 15)
776#define RT5659_M_DAC_L1_MONO_L_SFT 15
777#define RT5659_G_DAC_L1_MONO_L_MASK (0x1 << 14)
778#define RT5659_G_DAC_L1_MONO_L_SFT 14
779#define RT5659_M_DAC_R1_MONO_L (0x1 << 13)
780#define RT5659_M_DAC_R1_MONO_L_SFT 13
781#define RT5659_G_DAC_R1_MONO_L_MASK (0x1 << 12)
782#define RT5659_G_DAC_R1_MONO_L_SFT 12
783#define RT5659_M_DAC_L2_MONO_L (0x1 << 11)
784#define RT5659_M_DAC_L2_MONO_L_SFT 11
785#define RT5659_G_DAC_L2_MONO_L_MASK (0x1 << 10)
786#define RT5659_G_DAC_L2_MONO_L_SFT 10
787#define RT5659_M_DAC_R2_MONO_L (0x1 << 9)
788#define RT5659_M_DAC_R2_MONO_L_SFT 9
789#define RT5659_G_DAC_R2_MONO_L_MASK (0x1 << 8)
790#define RT5659_G_DAC_R2_MONO_L_SFT 8
791#define RT5659_M_DAC_L1_MONO_R (0x1 << 7)
792#define RT5659_M_DAC_L1_MONO_R_SFT 7
793#define RT5659_G_DAC_L1_MONO_R_MASK (0x1 << 6)
794#define RT5659_G_DAC_L1_MONO_R_SFT 6
795#define RT5659_M_DAC_R1_MONO_R (0x1 << 5)
796#define RT5659_M_DAC_R1_MONO_R_SFT 5
797#define RT5659_G_DAC_R1_MONO_R_MASK (0x1 << 4)
798#define RT5659_G_DAC_R1_MONO_R_SFT 4
799#define RT5659_M_DAC_L2_MONO_R (0x1 << 3)
800#define RT5659_M_DAC_L2_MONO_R_SFT 3
801#define RT5659_G_DAC_L2_MONO_R_MASK (0x1 << 2)
802#define RT5659_G_DAC_L2_MONO_R_SFT 2
803#define RT5659_M_DAC_R2_MONO_R (0x1 << 1)
804#define RT5659_M_DAC_R2_MONO_R_SFT 1
805#define RT5659_G_DAC_R2_MONO_R_MASK (0x1)
806#define RT5659_G_DAC_R2_MONO_R_SFT 0
807
808/* Digital Mixer Control (0x002c) */
809#define RT5659_M_DAC_MIX_L (0x1 << 7)
810#define RT5659_M_DAC_MIX_L_SFT 7
811#define RT5659_DAC_MIX_L_MASK (0x1 << 6)
812#define RT5659_DAC_MIX_L_SFT 6
813#define RT5659_M_DAC_MIX_R (0x1 << 5)
814#define RT5659_M_DAC_MIX_R_SFT 5
815#define RT5659_DAC_MIX_R_MASK (0x1 << 4)
816#define RT5659_DAC_MIX_R_SFT 4
817
818/* Analog DAC Input Source Control (0x002d) */
819#define RT5659_A_DACL1_SEL (0x1 << 3)
820#define RT5659_A_DACL1_SFT 3
821#define RT5659_A_DACR1_SEL (0x1 << 2)
822#define RT5659_A_DACR1_SFT 2
823#define RT5659_A_DACL2_SEL (0x1 << 1)
824#define RT5659_A_DACL2_SFT 1
825#define RT5659_A_DACR2_SEL (0x1 << 0)
826#define RT5659_A_DACR2_SFT 0
827
828/* Digital Interface Data Control (0x002f) */
829#define RT5659_IF2_ADC3_IN_MASK (0x3 << 14)
830#define RT5659_IF2_ADC3_IN_SFT 14
831#define RT5659_IF2_ADC_IN_MASK (0x3 << 12)
832#define RT5659_IF2_ADC_IN_SFT 12
833#define RT5659_IF2_DAC_SEL_MASK (0x3 << 10)
834#define RT5659_IF2_DAC_SEL_SFT 10
835#define RT5659_IF2_ADC_SEL_MASK (0x3 << 8)
836#define RT5659_IF2_ADC_SEL_SFT 8
837#define RT5659_IF3_DAC_SEL_MASK (0x3 << 6)
838#define RT5659_IF3_DAC_SEL_SFT 6
839#define RT5659_IF3_ADC_SEL_MASK (0x3 << 4)
840#define RT5659_IF3_ADC_SEL_SFT 4
841#define RT5659_IF3_ADC_IN_MASK (0x3 << 0)
842#define RT5659_IF3_ADC_IN_SFT 0
843
844/* PDM Output Control (0x0031) */
845#define RT5659_PDM1_L_MASK (0x1 << 15)
846#define RT5659_PDM1_L_SFT 15
847#define RT5659_M_PDM1_L (0x1 << 14)
848#define RT5659_M_PDM1_L_SFT 14
849#define RT5659_PDM1_R_MASK (0x1 << 13)
850#define RT5659_PDM1_R_SFT 13
851#define RT5659_M_PDM1_R (0x1 << 12)
852#define RT5659_M_PDM1_R_SFT 12
853#define RT5659_PDM2_BUSY (0x1 << 7)
854#define RT5659_PDM1_BUSY (0x1 << 6)
855#define RT5659_PDM_PATTERN (0x1 << 5)
856#define RT5659_PDM_GAIN (0x1 << 4)
857#define RT5659_PDM_DIV_MASK (0x3)
858
859/*S/PDIF Output Control (0x0036) */
860#define RT5659_SPDIF_SEL_MASK (0x3 << 0)
861#define RT5659_SPDIF_SEL_SFT 0
862
863/* REC Left Mixer Control 2 (0x003c) */
864#define RT5659_M_BST1_RM1_L (0x1 << 5)
865#define RT5659_M_BST1_RM1_L_SFT 5
866#define RT5659_M_BST2_RM1_L (0x1 << 4)
867#define RT5659_M_BST2_RM1_L_SFT 4
868#define RT5659_M_BST3_RM1_L (0x1 << 3)
869#define RT5659_M_BST3_RM1_L_SFT 3
870#define RT5659_M_BST4_RM1_L (0x1 << 2)
871#define RT5659_M_BST4_RM1_L_SFT 2
872#define RT5659_M_INL_RM1_L (0x1 << 1)
873#define RT5659_M_INL_RM1_L_SFT 1
874#define RT5659_M_SPKVOLL_RM1_L (0x1)
875#define RT5659_M_SPKVOLL_RM1_L_SFT 0
876
877/* REC Right Mixer Control 2 (0x003e) */
878#define RT5659_M_BST1_RM1_R (0x1 << 5)
879#define RT5659_M_BST1_RM1_R_SFT 5
880#define RT5659_M_BST2_RM1_R (0x1 << 4)
881#define RT5659_M_BST2_RM1_R_SFT 4
882#define RT5659_M_BST3_RM1_R (0x1 << 3)
883#define RT5659_M_BST3_RM1_R_SFT 3
884#define RT5659_M_BST4_RM1_R (0x1 << 2)
885#define RT5659_M_BST4_RM1_R_SFT 2
886#define RT5659_M_INR_RM1_R (0x1 << 1)
887#define RT5659_M_INR_RM1_R_SFT 1
888#define RT5659_M_HPOVOLR_RM1_R (0x1)
889#define RT5659_M_HPOVOLR_RM1_R_SFT 0
890
891/* SPK Left Mixer Control (0x0046) */
892#define RT5659_M_BST3_SM_L (0x1 << 4)
893#define RT5659_M_BST3_SM_L_SFT 4
894#define RT5659_M_IN_R_SM_L (0x1 << 3)
895#define RT5659_M_IN_R_SM_L_SFT 3
896#define RT5659_M_IN_L_SM_L (0x1 << 2)
897#define RT5659_M_IN_L_SM_L_SFT 2
898#define RT5659_M_BST1_SM_L (0x1 << 1)
899#define RT5659_M_BST1_SM_L_SFT 1
900#define RT5659_M_DAC_L2_SM_L (0x1)
901#define RT5659_M_DAC_L2_SM_L_SFT 0
902
903/* SPK Right Mixer Control (0x0047) */
904#define RT5659_M_BST3_SM_R (0x1 << 4)
905#define RT5659_M_BST3_SM_R_SFT 4
906#define RT5659_M_IN_R_SM_R (0x1 << 3)
907#define RT5659_M_IN_R_SM_R_SFT 3
908#define RT5659_M_IN_L_SM_R (0x1 << 2)
909#define RT5659_M_IN_L_SM_R_SFT 2
910#define RT5659_M_BST4_SM_R (0x1 << 1)
911#define RT5659_M_BST4_SM_R_SFT 1
912#define RT5659_M_DAC_R2_SM_R (0x1)
913#define RT5659_M_DAC_R2_SM_R_SFT 0
914
915/* SPO Amp Input and Gain Control (0x0048) */
916#define RT5659_M_DAC_L2_SPKOMIX (0x1 << 13)
917#define RT5659_M_DAC_L2_SPKOMIX_SFT 13
918#define RT5659_M_SPKVOLL_SPKOMIX (0x1 << 12)
919#define RT5659_M_SPKVOLL_SPKOMIX_SFT 12
920#define RT5659_M_DAC_R2_SPKOMIX (0x1 << 9)
921#define RT5659_M_DAC_R2_SPKOMIX_SFT 9
922#define RT5659_M_SPKVOLR_SPKOMIX (0x1 << 8)
923#define RT5659_M_SPKVOLR_SPKOMIX_SFT 8
924
925/* MONOMIX Input and Gain Control (0x004b) */
926#define RT5659_M_MONOVOL_MA (0x1 << 9)
927#define RT5659_M_MONOVOL_MA_SFT 9
928#define RT5659_M_DAC_L2_MA (0x1 << 8)
929#define RT5659_M_DAC_L2_MA_SFT 8
930#define RT5659_M_BST3_MM (0x1 << 4)
931#define RT5659_M_BST3_MM_SFT 4
932#define RT5659_M_BST2_MM (0x1 << 3)
933#define RT5659_M_BST2_MM_SFT 3
934#define RT5659_M_BST1_MM (0x1 << 2)
935#define RT5659_M_BST1_MM_SFT 2
936#define RT5659_M_DAC_R2_MM (0x1 << 1)
937#define RT5659_M_DAC_R2_MM_SFT 1
938#define RT5659_M_DAC_L2_MM (0x1)
939#define RT5659_M_DAC_L2_MM_SFT 0
940
941/* Output Left Mixer Control 1 (0x004d) */
942#define RT5659_G_BST3_OM_L_MASK (0x7 << 12)
943#define RT5659_G_BST3_OM_L_SFT 12
944#define RT5659_G_BST2_OM_L_MASK (0x7 << 9)
945#define RT5659_G_BST2_OM_L_SFT 9
946#define RT5659_G_BST1_OM_L_MASK (0x7 << 6)
947#define RT5659_G_BST1_OM_L_SFT 6
948#define RT5659_G_IN_L_OM_L_MASK (0x7 << 3)
949#define RT5659_G_IN_L_OM_L_SFT 3
950#define RT5659_G_DAC_L2_OM_L_MASK (0x7 << 0)
951#define RT5659_G_DAC_L2_OM_L_SFT 0
952
953/* Output Left Mixer Input Control (0x004e) */
954#define RT5659_M_BST3_OM_L (0x1 << 4)
955#define RT5659_M_BST3_OM_L_SFT 4
956#define RT5659_M_BST2_OM_L (0x1 << 3)
957#define RT5659_M_BST2_OM_L_SFT 3
958#define RT5659_M_BST1_OM_L (0x1 << 2)
959#define RT5659_M_BST1_OM_L_SFT 2
960#define RT5659_M_IN_L_OM_L (0x1 << 1)
961#define RT5659_M_IN_L_OM_L_SFT 1
962#define RT5659_M_DAC_L2_OM_L (0x1)
963#define RT5659_M_DAC_L2_OM_L_SFT 0
964
965/* Output Right Mixer Input Control (0x0050) */
966#define RT5659_M_BST4_OM_R (0x1 << 4)
967#define RT5659_M_BST4_OM_R_SFT 4
968#define RT5659_M_BST3_OM_R (0x1 << 3)
969#define RT5659_M_BST3_OM_R_SFT 3
970#define RT5659_M_BST2_OM_R (0x1 << 2)
971#define RT5659_M_BST2_OM_R_SFT 2
972#define RT5659_M_IN_R_OM_R (0x1 << 1)
973#define RT5659_M_IN_R_OM_R_SFT 1
974#define RT5659_M_DAC_R2_OM_R (0x1)
975#define RT5659_M_DAC_R2_OM_R_SFT 0
976
977/* LOUT Mixer Control (0x0052) */
978#define RT5659_M_DAC_L2_LM (0x1 << 15)
979#define RT5659_M_DAC_L2_LM_SFT 15
980#define RT5659_M_DAC_R2_LM (0x1 << 14)
981#define RT5659_M_DAC_R2_LM_SFT 14
982#define RT5659_M_OV_L_LM (0x1 << 13)
983#define RT5659_M_OV_L_LM_SFT 13
984#define RT5659_M_OV_R_LM (0x1 << 12)
985#define RT5659_M_OV_R_LM_SFT 12
986
987/* Power Management for Digital 1 (0x0061) */
988#define RT5659_PWR_I2S1 (0x1 << 15)
989#define RT5659_PWR_I2S1_BIT 15
990#define RT5659_PWR_I2S2 (0x1 << 14)
991#define RT5659_PWR_I2S2_BIT 14
992#define RT5659_PWR_I2S3 (0x1 << 13)
993#define RT5659_PWR_I2S3_BIT 13
994#define RT5659_PWR_SPDIF (0x1 << 12)
995#define RT5659_PWR_SPDIF_BIT 12
996#define RT5659_PWR_DAC_L1 (0x1 << 11)
997#define RT5659_PWR_DAC_L1_BIT 11
998#define RT5659_PWR_DAC_R1 (0x1 << 10)
999#define RT5659_PWR_DAC_R1_BIT 10
1000#define RT5659_PWR_DAC_L2 (0x1 << 9)
1001#define RT5659_PWR_DAC_L2_BIT 9
1002#define RT5659_PWR_DAC_R2 (0x1 << 8)
1003#define RT5659_PWR_DAC_R2_BIT 8
1004#define RT5659_PWR_LDO (0x1 << 7)
1005#define RT5659_PWR_LDO_BIT 7
1006#define RT5659_PWR_ADC_L1 (0x1 << 4)
1007#define RT5659_PWR_ADC_L1_BIT 4
1008#define RT5659_PWR_ADC_R1 (0x1 << 3)
1009#define RT5659_PWR_ADC_R1_BIT 3
1010#define RT5659_PWR_ADC_L2 (0x1 << 2)
1011#define RT5659_PWR_ADC_L2_BIT 4
1012#define RT5659_PWR_ADC_R2 (0x1 << 1)
1013#define RT5659_PWR_ADC_R2_BIT 1
1014#define RT5659_PWR_CLS_D (0x1)
1015#define RT5659_PWR_CLS_D_BIT 0
1016
1017/* Power Management for Digital 2 (0x0062) */
1018#define RT5659_PWR_ADC_S1F (0x1 << 15)
1019#define RT5659_PWR_ADC_S1F_BIT 15
1020#define RT5659_PWR_ADC_S2F (0x1 << 14)
1021#define RT5659_PWR_ADC_S2F_BIT 14
1022#define RT5659_PWR_ADC_MF_L (0x1 << 13)
1023#define RT5659_PWR_ADC_MF_L_BIT 13
1024#define RT5659_PWR_ADC_MF_R (0x1 << 12)
1025#define RT5659_PWR_ADC_MF_R_BIT 12
1026#define RT5659_PWR_DAC_S1F (0x1 << 10)
1027#define RT5659_PWR_DAC_S1F_BIT 10
1028#define RT5659_PWR_DAC_MF_L (0x1 << 9)
1029#define RT5659_PWR_DAC_MF_L_BIT 9
1030#define RT5659_PWR_DAC_MF_R (0x1 << 8)
1031#define RT5659_PWR_DAC_MF_R_BIT 8
1032#define RT5659_PWR_PDM1 (0x1 << 7)
1033#define RT5659_PWR_PDM1_BIT 7
1034
1035/* Power Management for Analog 1 (0x0063) */
1036#define RT5659_PWR_VREF1 (0x1 << 15)
1037#define RT5659_PWR_VREF1_BIT 15
1038#define RT5659_PWR_FV1 (0x1 << 14)
1039#define RT5659_PWR_FV1_BIT 14
1040#define RT5659_PWR_VREF2 (0x1 << 13)
1041#define RT5659_PWR_VREF2_BIT 13
1042#define RT5659_PWR_FV2 (0x1 << 12)
1043#define RT5659_PWR_FV2_BIT 12
1044#define RT5659_PWR_VREF3 (0x1 << 11)
1045#define RT5659_PWR_VREF3_BIT 11
1046#define RT5659_PWR_FV3 (0x1 << 10)
1047#define RT5659_PWR_FV3_BIT 10
1048#define RT5659_PWR_MB (0x1 << 9)
1049#define RT5659_PWR_MB_BIT 9
1050#define RT5659_PWR_LM (0x1 << 8)
1051#define RT5659_PWR_LM_BIT 8
1052#define RT5659_PWR_BG (0x1 << 7)
1053#define RT5659_PWR_BG_BIT 7
1054#define RT5659_PWR_MA (0x1 << 6)
1055#define RT5659_PWR_MA_BIT 6
1056#define RT5659_PWR_HA_L (0x1 << 5)
1057#define RT5659_PWR_HA_L_BIT 5
1058#define RT5659_PWR_HA_R (0x1 << 4)
1059#define RT5659_PWR_HA_R_BIT 4
1060
1061/* Power Management for Analog 2 (0x0064) */
1062#define RT5659_PWR_BST1 (0x1 << 15)
1063#define RT5659_PWR_BST1_BIT 15
1064#define RT5659_PWR_BST2 (0x1 << 14)
1065#define RT5659_PWR_BST2_BIT 14
1066#define RT5659_PWR_BST3 (0x1 << 13)
1067#define RT5659_PWR_BST3_BIT 13
1068#define RT5659_PWR_BST4 (0x1 << 12)
1069#define RT5659_PWR_BST4_BIT 12
1070#define RT5659_PWR_MB1 (0x1 << 11)
1071#define RT5659_PWR_MB1_BIT 11
1072#define RT5659_PWR_MB2 (0x1 << 10)
1073#define RT5659_PWR_MB2_BIT 10
1074#define RT5659_PWR_MB3 (0x1 << 9)
1075#define RT5659_PWR_MB3_BIT 9
1076#define RT5659_PWR_BST1_P (0x1 << 6)
1077#define RT5659_PWR_BST1_P_BIT 6
1078#define RT5659_PWR_BST2_P (0x1 << 5)
1079#define RT5659_PWR_BST2_P_BIT 5
1080#define RT5659_PWR_BST3_P (0x1 << 4)
1081#define RT5659_PWR_BST3_P_BIT 4
1082#define RT5659_PWR_BST4_P (0x1 << 3)
1083#define RT5659_PWR_BST4_P_BIT 3
1084#define RT5659_PWR_JD1 (0x1 << 2)
1085#define RT5659_PWR_JD1_BIT 2
1086#define RT5659_PWR_JD2 (0x1 << 1)
1087#define RT5659_PWR_JD2_BIT 1
1088#define RT5659_PWR_JD3 (0x1)
1089#define RT5659_PWR_JD3_BIT 0
1090
1091/* Power Management for Analog 3 (0x0065) */
1092#define RT5659_PWR_BST_L (0x1 << 8)
1093#define RT5659_PWR_BST_L_BIT 8
1094#define RT5659_PWR_BST_R (0x1 << 7)
1095#define RT5659_PWR_BST_R_BIT 7
1096#define RT5659_PWR_PLL (0x1 << 6)
1097#define RT5659_PWR_PLL_BIT 6
1098#define RT5659_PWR_LDO5 (0x1 << 5)
1099#define RT5659_PWR_LDO5_BIT 5
1100#define RT5659_PWR_LDO4 (0x1 << 4)
1101#define RT5659_PWR_LDO4_BIT 4
1102#define RT5659_PWR_LDO3 (0x1 << 3)
1103#define RT5659_PWR_LDO3_BIT 3
1104#define RT5659_PWR_LDO2 (0x1 << 2)
1105#define RT5659_PWR_LDO2_BIT 2
1106#define RT5659_PWR_SVD (0x1 << 1)
1107#define RT5659_PWR_SVD_BIT 1
1108
1109/* Power Management for Mixer (0x0066) */
1110#define RT5659_PWR_OM_L (0x1 << 15)
1111#define RT5659_PWR_OM_L_BIT 15
1112#define RT5659_PWR_OM_R (0x1 << 14)
1113#define RT5659_PWR_OM_R_BIT 14
1114#define RT5659_PWR_SM_L (0x1 << 13)
1115#define RT5659_PWR_SM_L_BIT 13
1116#define RT5659_PWR_SM_R (0x1 << 12)
1117#define RT5659_PWR_SM_R_BIT 12
1118#define RT5659_PWR_RM1_L (0x1 << 11)
1119#define RT5659_PWR_RM1_L_BIT 11
1120#define RT5659_PWR_RM1_R (0x1 << 10)
1121#define RT5659_PWR_RM1_R_BIT 10
1122#define RT5659_PWR_MM (0x1 << 8)
1123#define RT5659_PWR_MM_BIT 8
1124#define RT5659_PWR_RM2_L (0x1 << 3)
1125#define RT5659_PWR_RM2_L_BIT 3
1126#define RT5659_PWR_RM2_R (0x1 << 2)
1127#define RT5659_PWR_RM2_R_BIT 2
1128
1129/* Power Management for Volume (0x0067) */
1130#define RT5659_PWR_SV_L (0x1 << 15)
1131#define RT5659_PWR_SV_L_BIT 15
1132#define RT5659_PWR_SV_R (0x1 << 14)
1133#define RT5659_PWR_SV_R_BIT 14
1134#define RT5659_PWR_OV_L (0x1 << 13)
1135#define RT5659_PWR_OV_L_BIT 13
1136#define RT5659_PWR_OV_R (0x1 << 12)
1137#define RT5659_PWR_OV_R_BIT 12
1138#define RT5659_PWR_IN_L (0x1 << 9)
1139#define RT5659_PWR_IN_L_BIT 9
1140#define RT5659_PWR_IN_R (0x1 << 8)
1141#define RT5659_PWR_IN_R_BIT 8
1142#define RT5659_PWR_MV (0x1 << 7)
1143#define RT5659_PWR_MV_BIT 7
1144#define RT5659_PWR_MIC_DET (0x1 << 5)
1145#define RT5659_PWR_MIC_DET_BIT 5
1146
1147/* I2S1/2/3 Audio Serial Data Port Control (0x0070 0x0071 0x0072) */
1148#define RT5659_I2S_MS_MASK (0x1 << 15)
1149#define RT5659_I2S_MS_SFT 15
1150#define RT5659_I2S_MS_M (0x0 << 15)
1151#define RT5659_I2S_MS_S (0x1 << 15)
1152#define RT5659_I2S_O_CP_MASK (0x3 << 12)
1153#define RT5659_I2S_O_CP_SFT 12
1154#define RT5659_I2S_O_CP_OFF (0x0 << 12)
1155#define RT5659_I2S_O_CP_U_LAW (0x1 << 12)
1156#define RT5659_I2S_O_CP_A_LAW (0x2 << 12)
1157#define RT5659_I2S_I_CP_MASK (0x3 << 10)
1158#define RT5659_I2S_I_CP_SFT 10
1159#define RT5659_I2S_I_CP_OFF (0x0 << 10)
1160#define RT5659_I2S_I_CP_U_LAW (0x1 << 10)
1161#define RT5659_I2S_I_CP_A_LAW (0x2 << 10)
1162#define RT5659_I2S_BP_MASK (0x1 << 8)
1163#define RT5659_I2S_BP_SFT 8
1164#define RT5659_I2S_BP_NOR (0x0 << 8)
1165#define RT5659_I2S_BP_INV (0x1 << 8)
1166#define RT5659_I2S_DL_MASK (0x3 << 4)
1167#define RT5659_I2S_DL_SFT 4
1168#define RT5659_I2S_DL_16 (0x0 << 4)
1169#define RT5659_I2S_DL_20 (0x1 << 4)
1170#define RT5659_I2S_DL_24 (0x2 << 4)
1171#define RT5659_I2S_DL_8 (0x3 << 4)
1172#define RT5659_I2S_DF_MASK (0x7)
1173#define RT5659_I2S_DF_SFT 0
1174#define RT5659_I2S_DF_I2S (0x0)
1175#define RT5659_I2S_DF_LEFT (0x1)
1176#define RT5659_I2S_DF_PCM_A (0x2)
1177#define RT5659_I2S_DF_PCM_B (0x3)
1178#define RT5659_I2S_DF_PCM_A_N (0x6)
1179#define RT5659_I2S_DF_PCM_B_N (0x7)
1180
1181/* ADC/DAC Clock Control 1 (0x0073) */
1182#define RT5659_I2S_PD1_MASK (0x7 << 12)
1183#define RT5659_I2S_PD1_SFT 12
1184#define RT5659_I2S_PD1_1 (0x0 << 12)
1185#define RT5659_I2S_PD1_2 (0x1 << 12)
1186#define RT5659_I2S_PD1_3 (0x2 << 12)
1187#define RT5659_I2S_PD1_4 (0x3 << 12)
1188#define RT5659_I2S_PD1_6 (0x4 << 12)
1189#define RT5659_I2S_PD1_8 (0x5 << 12)
1190#define RT5659_I2S_PD1_12 (0x6 << 12)
1191#define RT5659_I2S_PD1_16 (0x7 << 12)
1192#define RT5659_I2S_BCLK_MS2_MASK (0x1 << 11)
1193#define RT5659_I2S_BCLK_MS2_SFT 11
1194#define RT5659_I2S_BCLK_MS2_32 (0x0 << 11)
1195#define RT5659_I2S_BCLK_MS2_64 (0x1 << 11)
1196#define RT5659_I2S_PD2_MASK (0x7 << 8)
1197#define RT5659_I2S_PD2_SFT 8
1198#define RT5659_I2S_PD2_1 (0x0 << 8)
1199#define RT5659_I2S_PD2_2 (0x1 << 8)
1200#define RT5659_I2S_PD2_3 (0x2 << 8)
1201#define RT5659_I2S_PD2_4 (0x3 << 8)
1202#define RT5659_I2S_PD2_6 (0x4 << 8)
1203#define RT5659_I2S_PD2_8 (0x5 << 8)
1204#define RT5659_I2S_PD2_12 (0x6 << 8)
1205#define RT5659_I2S_PD2_16 (0x7 << 8)
1206#define RT5659_I2S_BCLK_MS3_MASK (0x1 << 7)
1207#define RT5659_I2S_BCLK_MS3_SFT 7
1208#define RT5659_I2S_BCLK_MS3_32 (0x0 << 7)
1209#define RT5659_I2S_BCLK_MS3_64 (0x1 << 7)
1210#define RT5659_I2S_PD3_MASK (0x7 << 4)
1211#define RT5659_I2S_PD3_SFT 4
1212#define RT5659_I2S_PD3_1 (0x0 << 4)
1213#define RT5659_I2S_PD3_2 (0x1 << 4)
1214#define RT5659_I2S_PD3_3 (0x2 << 4)
1215#define RT5659_I2S_PD3_4 (0x3 << 4)
1216#define RT5659_I2S_PD3_6 (0x4 << 4)
1217#define RT5659_I2S_PD3_8 (0x5 << 4)
1218#define RT5659_I2S_PD3_12 (0x6 << 4)
1219#define RT5659_I2S_PD3_16 (0x7 << 4)
1220#define RT5659_DAC_OSR_MASK (0x3 << 2)
1221#define RT5659_DAC_OSR_SFT 2
1222#define RT5659_DAC_OSR_128 (0x0 << 2)
1223#define RT5659_DAC_OSR_64 (0x1 << 2)
1224#define RT5659_DAC_OSR_32 (0x2 << 2)
1225#define RT5659_DAC_OSR_16 (0x3 << 2)
1226#define RT5659_ADC_OSR_MASK (0x3)
1227#define RT5659_ADC_OSR_SFT 0
1228#define RT5659_ADC_OSR_128 (0x0)
1229#define RT5659_ADC_OSR_64 (0x1)
1230#define RT5659_ADC_OSR_32 (0x2)
1231#define RT5659_ADC_OSR_16 (0x3)
1232
1233/* Digital Microphone Control (0x0075) */
1234#define RT5659_DMIC_1_EN_MASK (0x1 << 15)
1235#define RT5659_DMIC_1_EN_SFT 15
1236#define RT5659_DMIC_1_DIS (0x0 << 15)
1237#define RT5659_DMIC_1_EN (0x1 << 15)
1238#define RT5659_DMIC_2_EN_MASK (0x1 << 14)
1239#define RT5659_DMIC_2_EN_SFT 14
1240#define RT5659_DMIC_2_DIS (0x0 << 14)
1241#define RT5659_DMIC_2_EN (0x1 << 14)
1242#define RT5659_DMIC_1L_LH_MASK (0x1 << 13)
1243#define RT5659_DMIC_1L_LH_SFT 13
1244#define RT5659_DMIC_1L_LH_RISING (0x0 << 13)
1245#define RT5659_DMIC_1L_LH_FALLING (0x1 << 13)
1246#define RT5659_DMIC_1R_LH_MASK (0x1 << 12)
1247#define RT5659_DMIC_1R_LH_SFT 12
1248#define RT5659_DMIC_1R_LH_RISING (0x0 << 12)
1249#define RT5659_DMIC_1R_LH_FALLING (0x1 << 12)
1250#define RT5659_DMIC_2_DP_MASK (0x3 << 10)
1251#define RT5659_DMIC_2_DP_SFT 10
1252#define RT5659_DMIC_2_DP_GPIO6 (0x0 << 10)
1253#define RT5659_DMIC_2_DP_GPIO10 (0x1 << 10)
1254#define RT5659_DMIC_2_DP_GPIO12 (0x2 << 10)
1255#define RT5659_DMIC_2_DP_IN2P (0x3 << 10)
1256#define RT5659_DMIC_CLK_MASK (0x7 << 5)
1257#define RT5659_DMIC_CLK_SFT 5
1258#define RT5659_DMIC_1_DP_MASK (0x3 << 0)
1259#define RT5659_DMIC_1_DP_SFT 0
1260#define RT5659_DMIC_1_DP_GPIO5 (0x0 << 0)
1261#define RT5659_DMIC_1_DP_GPIO9 (0x1 << 0)
1262#define RT5659_DMIC_1_DP_GPIO11 (0x2 << 0)
1263#define RT5659_DMIC_1_DP_IN2N (0x3 << 0)
1264
1265/* TDM control 1 (0x0078)*/
1266#define RT5659_DS_ADC_SLOT01_SFT 14
1267#define RT5659_DS_ADC_SLOT23_SFT 12
1268#define RT5659_DS_ADC_SLOT45_SFT 10
1269#define RT5659_DS_ADC_SLOT67_SFT 8
1270#define RT5659_ADCDAT_SRC_MASK 0x1f
1271#define RT5659_ADCDAT_SRC_SFT 0
1272
1273/* Global Clock Control (0x0080) */
1274#define RT5659_SCLK_SRC_MASK (0x3 << 14)
1275#define RT5659_SCLK_SRC_SFT 14
1276#define RT5659_SCLK_SRC_MCLK (0x0 << 14)
1277#define RT5659_SCLK_SRC_PLL1 (0x1 << 14)
1278#define RT5659_SCLK_SRC_RCCLK (0x2 << 14)
1279#define RT5659_PLL1_SRC_MASK (0x7 << 11)
1280#define RT5659_PLL1_SRC_SFT 11
1281#define RT5659_PLL1_SRC_MCLK (0x0 << 11)
1282#define RT5659_PLL1_SRC_BCLK1 (0x1 << 11)
1283#define RT5659_PLL1_SRC_BCLK2 (0x2 << 11)
1284#define RT5659_PLL1_SRC_BCLK3 (0x3 << 11)
1285#define RT5659_PLL1_PD_MASK (0x1 << 3)
1286#define RT5659_PLL1_PD_SFT 3
1287#define RT5659_PLL1_PD_1 (0x0 << 3)
1288#define RT5659_PLL1_PD_2 (0x1 << 3)
1289
1290#define RT5659_PLL_INP_MAX 40000000
1291#define RT5659_PLL_INP_MIN 256000
1292/* PLL M/N/K Code Control 1 (0x0081) */
1293#define RT5659_PLL_N_MAX 0x001ff
1294#define RT5659_PLL_N_MASK (RT5659_PLL_N_MAX << 7)
1295#define RT5659_PLL_N_SFT 7
1296#define RT5659_PLL_K_MAX 0x001f
1297#define RT5659_PLL_K_MASK (RT5659_PLL_K_MAX)
1298#define RT5659_PLL_K_SFT 0
1299
1300/* PLL M/N/K Code Control 2 (0x0082) */
1301#define RT5659_PLL_M_MAX 0x00f
1302#define RT5659_PLL_M_MASK (RT5659_PLL_M_MAX << 12)
1303#define RT5659_PLL_M_SFT 12
1304#define RT5659_PLL_M_BP (0x1 << 11)
1305#define RT5659_PLL_M_BP_SFT 11
1306
1307/* PLL tracking mode 1 (0x0083) */
1308#define RT5659_I2S3_ASRC_MASK (0x1 << 13)
1309#define RT5659_I2S3_ASRC_SFT 13
1310#define RT5659_I2S2_ASRC_MASK (0x1 << 12)
1311#define RT5659_I2S2_ASRC_SFT 12
1312#define RT5659_I2S1_ASRC_MASK (0x1 << 11)
1313#define RT5659_I2S1_ASRC_SFT 11
1314#define RT5659_DAC_STO_ASRC_MASK (0x1 << 10)
1315#define RT5659_DAC_STO_ASRC_SFT 10
1316#define RT5659_DAC_MONO_L_ASRC_MASK (0x1 << 9)
1317#define RT5659_DAC_MONO_L_ASRC_SFT 9
1318#define RT5659_DAC_MONO_R_ASRC_MASK (0x1 << 8)
1319#define RT5659_DAC_MONO_R_ASRC_SFT 8
1320#define RT5659_DMIC_STO1_ASRC_MASK (0x1 << 7)
1321#define RT5659_DMIC_STO1_ASRC_SFT 7
1322#define RT5659_DMIC_MONO_L_ASRC_MASK (0x1 << 5)
1323#define RT5659_DMIC_MONO_L_ASRC_SFT 5
1324#define RT5659_DMIC_MONO_R_ASRC_MASK (0x1 << 4)
1325#define RT5659_DMIC_MONO_R_ASRC_SFT 4
1326#define RT5659_ADC_STO1_ASRC_MASK (0x1 << 3)
1327#define RT5659_ADC_STO1_ASRC_SFT 3
1328#define RT5659_ADC_MONO_L_ASRC_MASK (0x1 << 1)
1329#define RT5659_ADC_MONO_L_ASRC_SFT 1
1330#define RT5659_ADC_MONO_R_ASRC_MASK (0x1)
1331#define RT5659_ADC_MONO_R_ASRC_SFT 0
1332
1333/* PLL tracking mode 2 (0x0084)*/
1334#define RT5659_DA_STO_T_MASK (0x7 << 12)
1335#define RT5659_DA_STO_T_SFT 12
1336#define RT5659_DA_MONO_L_T_MASK (0x7 << 8)
1337#define RT5659_DA_MONO_L_T_SFT 8
1338#define RT5659_DA_MONO_R_T_MASK (0x7 << 4)
1339#define RT5659_DA_MONO_R_T_SFT 4
1340#define RT5659_AD_STO1_T_MASK (0x7)
1341#define RT5659_AD_STO1_T_SFT 0
1342
1343/* PLL tracking mode 3 (0x0085)*/
1344#define RT5659_AD_STO2_T_MASK (0x7 << 8)
1345#define RT5659_AD_STO2_T_SFT 8
1346#define RT5659_AD_MONO_L_T_MASK (0x7 << 4)
1347#define RT5659_AD_MONO_L_T_SFT 4
1348#define RT5659_AD_MONO_R_T_MASK (0x7)
1349#define RT5659_AD_MONO_R_T_SFT 0
1350
1351/* ASRC Control 4 (0x0086) */
1352#define RT5659_I2S1_RATE_MASK (0xf << 12)
1353#define RT5659_I2S1_RATE_SFT 12
1354#define RT5659_I2S2_RATE_MASK (0xf << 8)
1355#define RT5659_I2S2_RATE_SFT 8
1356#define RT5659_I2S3_RATE_MASK (0xf << 4)
1357#define RT5659_I2S3_RATE_SFT 4
1358
1359/* Depop Mode Control 1 (0x8e) */
1360#define RT5659_SMT_TRIG_MASK (0x1 << 15)
1361#define RT5659_SMT_TRIG_SFT 15
1362#define RT5659_SMT_TRIG_DIS (0x0 << 15)
1363#define RT5659_SMT_TRIG_EN (0x1 << 15)
1364#define RT5659_HP_L_SMT_MASK (0x1 << 9)
1365#define RT5659_HP_L_SMT_SFT 9
1366#define RT5659_HP_L_SMT_DIS (0x0 << 9)
1367#define RT5659_HP_L_SMT_EN (0x1 << 9)
1368#define RT5659_HP_R_SMT_MASK (0x1 << 8)
1369#define RT5659_HP_R_SMT_SFT 8
1370#define RT5659_HP_R_SMT_DIS (0x0 << 8)
1371#define RT5659_HP_R_SMT_EN (0x1 << 8)
1372#define RT5659_HP_CD_PD_MASK (0x1 << 7)
1373#define RT5659_HP_CD_PD_SFT 7
1374#define RT5659_HP_CD_PD_DIS (0x0 << 7)
1375#define RT5659_HP_CD_PD_EN (0x1 << 7)
1376#define RT5659_RSTN_MASK (0x1 << 6)
1377#define RT5659_RSTN_SFT 6
1378#define RT5659_RSTN_DIS (0x0 << 6)
1379#define RT5659_RSTN_EN (0x1 << 6)
1380#define RT5659_RSTP_MASK (0x1 << 5)
1381#define RT5659_RSTP_SFT 5
1382#define RT5659_RSTP_DIS (0x0 << 5)
1383#define RT5659_RSTP_EN (0x1 << 5)
1384#define RT5659_HP_CO_MASK (0x1 << 4)
1385#define RT5659_HP_CO_SFT 4
1386#define RT5659_HP_CO_DIS (0x0 << 4)
1387#define RT5659_HP_CO_EN (0x1 << 4)
1388#define RT5659_HP_CP_MASK (0x1 << 3)
1389#define RT5659_HP_CP_SFT 3
1390#define RT5659_HP_CP_PD (0x0 << 3)
1391#define RT5659_HP_CP_PU (0x1 << 3)
1392#define RT5659_HP_SG_MASK (0x1 << 2)
1393#define RT5659_HP_SG_SFT 2
1394#define RT5659_HP_SG_DIS (0x0 << 2)
1395#define RT5659_HP_SG_EN (0x1 << 2)
1396#define RT5659_HP_DP_MASK (0x1 << 1)
1397#define RT5659_HP_DP_SFT 1
1398#define RT5659_HP_DP_PD (0x0 << 1)
1399#define RT5659_HP_DP_PU (0x1 << 1)
1400#define RT5659_HP_CB_MASK (0x1)
1401#define RT5659_HP_CB_SFT 0
1402#define RT5659_HP_CB_PD (0x0)
1403#define RT5659_HP_CB_PU (0x1)
1404
1405/* Depop Mode Control 2 (0x8f) */
1406#define RT5659_DEPOP_MASK (0x1 << 13)
1407#define RT5659_DEPOP_SFT 13
1408#define RT5659_DEPOP_AUTO (0x0 << 13)
1409#define RT5659_DEPOP_MAN (0x1 << 13)
1410#define RT5659_RAMP_MASK (0x1 << 12)
1411#define RT5659_RAMP_SFT 12
1412#define RT5659_RAMP_DIS (0x0 << 12)
1413#define RT5659_RAMP_EN (0x1 << 12)
1414#define RT5659_BPS_MASK (0x1 << 11)
1415#define RT5659_BPS_SFT 11
1416#define RT5659_BPS_DIS (0x0 << 11)
1417#define RT5659_BPS_EN (0x1 << 11)
1418#define RT5659_FAST_UPDN_MASK (0x1 << 10)
1419#define RT5659_FAST_UPDN_SFT 10
1420#define RT5659_FAST_UPDN_DIS (0x0 << 10)
1421#define RT5659_FAST_UPDN_EN (0x1 << 10)
1422#define RT5659_MRES_MASK (0x3 << 8)
1423#define RT5659_MRES_SFT 8
1424#define RT5659_MRES_15MO (0x0 << 8)
1425#define RT5659_MRES_25MO (0x1 << 8)
1426#define RT5659_MRES_35MO (0x2 << 8)
1427#define RT5659_MRES_45MO (0x3 << 8)
1428#define RT5659_VLO_MASK (0x1 << 7)
1429#define RT5659_VLO_SFT 7
1430#define RT5659_VLO_3V (0x0 << 7)
1431#define RT5659_VLO_32V (0x1 << 7)
1432#define RT5659_DIG_DP_MASK (0x1 << 6)
1433#define RT5659_DIG_DP_SFT 6
1434#define RT5659_DIG_DP_DIS (0x0 << 6)
1435#define RT5659_DIG_DP_EN (0x1 << 6)
1436#define RT5659_DP_TH_MASK (0x3 << 4)
1437#define RT5659_DP_TH_SFT 4
1438
1439/* Depop Mode Control 3 (0x90) */
1440#define RT5659_CP_SYS_MASK (0x7 << 12)
1441#define RT5659_CP_SYS_SFT 12
1442#define RT5659_CP_FQ1_MASK (0x7 << 8)
1443#define RT5659_CP_FQ1_SFT 8
1444#define RT5659_CP_FQ2_MASK (0x7 << 4)
1445#define RT5659_CP_FQ2_SFT 4
1446#define RT5659_CP_FQ3_MASK (0x7)
1447#define RT5659_CP_FQ3_SFT 0
1448#define RT5659_CP_FQ_1_5_KHZ 0
1449#define RT5659_CP_FQ_3_KHZ 1
1450#define RT5659_CP_FQ_6_KHZ 2
1451#define RT5659_CP_FQ_12_KHZ 3
1452#define RT5659_CP_FQ_24_KHZ 4
1453#define RT5659_CP_FQ_48_KHZ 5
1454#define RT5659_CP_FQ_96_KHZ 6
1455#define RT5659_CP_FQ_192_KHZ 7
1456
1457/* HPOUT charge pump 1 (0x0091) */
1458#define RT5659_OSW_L_MASK (0x1 << 11)
1459#define RT5659_OSW_L_SFT 11
1460#define RT5659_OSW_L_DIS (0x0 << 11)
1461#define RT5659_OSW_L_EN (0x1 << 11)
1462#define RT5659_OSW_R_MASK (0x1 << 10)
1463#define RT5659_OSW_R_SFT 10
1464#define RT5659_OSW_R_DIS (0x0 << 10)
1465#define RT5659_OSW_R_EN (0x1 << 10)
1466#define RT5659_PM_HP_MASK (0x3 << 8)
1467#define RT5659_PM_HP_SFT 8
1468#define RT5659_PM_HP_LV (0x0 << 8)
1469#define RT5659_PM_HP_MV (0x1 << 8)
1470#define RT5659_PM_HP_HV (0x2 << 8)
1471#define RT5659_IB_HP_MASK (0x3 << 6)
1472#define RT5659_IB_HP_SFT 6
1473#define RT5659_IB_HP_125IL (0x0 << 6)
1474#define RT5659_IB_HP_25IL (0x1 << 6)
1475#define RT5659_IB_HP_5IL (0x2 << 6)
1476#define RT5659_IB_HP_1IL (0x3 << 6)
1477
1478/* PV detection and SPK gain control (0x92) */
1479#define RT5659_PVDD_DET_MASK (0x1 << 15)
1480#define RT5659_PVDD_DET_SFT 15
1481#define RT5659_PVDD_DET_DIS (0x0 << 15)
1482#define RT5659_PVDD_DET_EN (0x1 << 15)
1483#define RT5659_SPK_AG_MASK (0x1 << 14)
1484#define RT5659_SPK_AG_SFT 14
1485#define RT5659_SPK_AG_DIS (0x0 << 14)
1486#define RT5659_SPK_AG_EN (0x1 << 14)
1487
1488/* Micbias Control (0x93) */
1489#define RT5659_MIC1_BS_MASK (0x1 << 15)
1490#define RT5659_MIC1_BS_SFT 15
1491#define RT5659_MIC1_BS_9AV (0x0 << 15)
1492#define RT5659_MIC1_BS_75AV (0x1 << 15)
1493#define RT5659_MIC2_BS_MASK (0x1 << 14)
1494#define RT5659_MIC2_BS_SFT 14
1495#define RT5659_MIC2_BS_9AV (0x0 << 14)
1496#define RT5659_MIC2_BS_75AV (0x1 << 14)
1497#define RT5659_MIC1_CLK_MASK (0x1 << 13)
1498#define RT5659_MIC1_CLK_SFT 13
1499#define RT5659_MIC1_CLK_DIS (0x0 << 13)
1500#define RT5659_MIC1_CLK_EN (0x1 << 13)
1501#define RT5659_MIC2_CLK_MASK (0x1 << 12)
1502#define RT5659_MIC2_CLK_SFT 12
1503#define RT5659_MIC2_CLK_DIS (0x0 << 12)
1504#define RT5659_MIC2_CLK_EN (0x1 << 12)
1505#define RT5659_MIC1_OVCD_MASK (0x1 << 11)
1506#define RT5659_MIC1_OVCD_SFT 11
1507#define RT5659_MIC1_OVCD_DIS (0x0 << 11)
1508#define RT5659_MIC1_OVCD_EN (0x1 << 11)
1509#define RT5659_MIC1_OVTH_MASK (0x3 << 9)
1510#define RT5659_MIC1_OVTH_SFT 9
1511#define RT5659_MIC1_OVTH_600UA (0x0 << 9)
1512#define RT5659_MIC1_OVTH_1500UA (0x1 << 9)
1513#define RT5659_MIC1_OVTH_2000UA (0x2 << 9)
1514#define RT5659_MIC2_OVCD_MASK (0x1 << 8)
1515#define RT5659_MIC2_OVCD_SFT 8
1516#define RT5659_MIC2_OVCD_DIS (0x0 << 8)
1517#define RT5659_MIC2_OVCD_EN (0x1 << 8)
1518#define RT5659_MIC2_OVTH_MASK (0x3 << 6)
1519#define RT5659_MIC2_OVTH_SFT 6
1520#define RT5659_MIC2_OVTH_600UA (0x0 << 6)
1521#define RT5659_MIC2_OVTH_1500UA (0x1 << 6)
1522#define RT5659_MIC2_OVTH_2000UA (0x2 << 6)
1523#define RT5659_PWR_MB_MASK (0x1 << 5)
1524#define RT5659_PWR_MB_SFT 5
1525#define RT5659_PWR_MB_PD (0x0 << 5)
1526#define RT5659_PWR_MB_PU (0x1 << 5)
1527#define RT5659_PWR_CLK25M_MASK (0x1 << 4)
1528#define RT5659_PWR_CLK25M_SFT 4
1529#define RT5659_PWR_CLK25M_PD (0x0 << 4)
1530#define RT5659_PWR_CLK25M_PU (0x1 << 4)
1531
1532/* REC Mixer 2 Left Control 2 (0x009c) */
1533#define RT5659_M_BST1_RM2_L (0x1 << 5)
1534#define RT5659_M_BST1_RM2_L_SFT 5
1535#define RT5659_M_BST2_RM2_L (0x1 << 4)
1536#define RT5659_M_BST2_RM2_L_SFT 4
1537#define RT5659_M_BST3_RM2_L (0x1 << 3)
1538#define RT5659_M_BST3_RM2_L_SFT 3
1539#define RT5659_M_BST4_RM2_L (0x1 << 2)
1540#define RT5659_M_BST4_RM2_L_SFT 2
1541#define RT5659_M_OUTVOLL_RM2_L (0x1 << 1)
1542#define RT5659_M_OUTVOLL_RM2_L_SFT 1
1543#define RT5659_M_SPKVOL_RM2_L (0x1)
1544#define RT5659_M_SPKVOL_RM2_L_SFT 0
1545
1546/* REC Mixer 2 Right Control 2 (0x009e) */
1547#define RT5659_M_BST1_RM2_R (0x1 << 5)
1548#define RT5659_M_BST1_RM2_R_SFT 5
1549#define RT5659_M_BST2_RM2_R (0x1 << 4)
1550#define RT5659_M_BST2_RM2_R_SFT 4
1551#define RT5659_M_BST3_RM2_R (0x1 << 3)
1552#define RT5659_M_BST3_RM2_R_SFT 3
1553#define RT5659_M_BST4_RM2_R (0x1 << 2)
1554#define RT5659_M_BST4_RM2_R_SFT 2
1555#define RT5659_M_OUTVOLR_RM2_R (0x1 << 1)
1556#define RT5659_M_OUTVOLR_RM2_R_SFT 1
1557#define RT5659_M_MONOVOL_RM2_R (0x1)
1558#define RT5659_M_MONOVOL_RM2_R_SFT 0
1559
1560/* Class D Output Control (0x00a0) */
1561#define RT5659_POW_CLSD_DB_MASK (0x1 << 9)
1562#define RT5659_POW_CLSD_DB_EN (0x1 << 9)
1563#define RT5659_POW_CLSD_DB_DIS (0x0 << 9)
1564
1565/* EQ Control 1 (0x00b0) */
1566#define RT5659_EQ_SRC_DAC (0x0 << 15)
1567#define RT5659_EQ_SRC_ADC (0x1 << 15)
1568#define RT5659_EQ_UPD (0x1 << 14)
1569#define RT5659_EQ_UPD_BIT 14
1570#define RT5659_EQ_CD_MASK (0x1 << 13)
1571#define RT5659_EQ_CD_SFT 13
1572#define RT5659_EQ_CD_DIS (0x0 << 13)
1573#define RT5659_EQ_CD_EN (0x1 << 13)
1574#define RT5659_EQ_DITH_MASK (0x3 << 8)
1575#define RT5659_EQ_DITH_SFT 8
1576#define RT5659_EQ_DITH_NOR (0x0 << 8)
1577#define RT5659_EQ_DITH_LSB (0x1 << 8)
1578#define RT5659_EQ_DITH_LSB_1 (0x2 << 8)
1579#define RT5659_EQ_DITH_LSB_2 (0x3 << 8)
1580
1581/* IRQ Control 1 (0x00b7) */
1582#define RT5659_JD1_1_EN_MASK (0x1 << 15)
1583#define RT5659_JD1_1_EN_SFT 15
1584#define RT5659_JD1_1_DIS (0x0 << 15)
1585#define RT5659_JD1_1_EN (0x1 << 15)
1586#define RT5659_JD1_2_EN_MASK (0x1 << 12)
1587#define RT5659_JD1_2_EN_SFT 12
1588#define RT5659_JD1_2_DIS (0x0 << 12)
1589#define RT5659_JD1_2_EN (0x1 << 12)
1590#define RT5659_IL_IRQ_MASK (0x1 << 3)
1591#define RT5659_IL_IRQ_DIS (0x0 << 3)
1592#define RT5659_IL_IRQ_EN (0x1 << 3)
1593
1594/* IRQ Control 5 (0x00ba) */
1595#define RT5659_IRQ_JD_EN (0x1 << 3)
1596#define RT5659_IRQ_JD_EN_SFT 3
1597
1598/* GPIO Control 1 (0x00c0) */
1599#define RT5659_GP1_PIN_MASK (0x1 << 15)
1600#define RT5659_GP1_PIN_SFT 15
1601#define RT5659_GP1_PIN_GPIO1 (0x0 << 15)
1602#define RT5659_GP1_PIN_IRQ (0x1 << 15)
1603#define RT5659_GP2_PIN_MASK (0x1 << 14)
1604#define RT5659_GP2_PIN_SFT 14
1605#define RT5659_GP2_PIN_GPIO2 (0x0 << 14)
1606#define RT5659_GP2_PIN_DMIC1_SCL (0x1 << 14)
1607#define RT5659_GP3_PIN_MASK (0x1 << 13)
1608#define RT5659_GP3_PIN_SFT 13
1609#define RT5659_GP3_PIN_GPIO3 (0x0 << 13)
1610#define RT5659_GP3_PIN_PDM_SCL (0x1 << 13)
1611#define RT5659_GP4_PIN_MASK (0x1 << 12)
1612#define RT5659_GP4_PIN_SFT 12
1613#define RT5659_GP4_PIN_GPIO4 (0x0 << 12)
1614#define RT5659_GP4_PIN_PDM_SDA (0x1 << 12)
1615#define RT5659_GP5_PIN_MASK (0x1 << 11)
1616#define RT5659_GP5_PIN_SFT 11
1617#define RT5659_GP5_PIN_GPIO5 (0x0 << 11)
1618#define RT5659_GP5_PIN_DMIC1_SDA (0x1 << 11)
1619#define RT5659_GP6_PIN_MASK (0x1 << 10)
1620#define RT5659_GP6_PIN_SFT 10
1621#define RT5659_GP6_PIN_GPIO6 (0x0 << 10)
1622#define RT5659_GP6_PIN_DMIC2_SDA (0x1 << 10)
1623#define RT5659_GP7_PIN_MASK (0x1 << 9)
1624#define RT5659_GP7_PIN_SFT 9
1625#define RT5659_GP7_PIN_GPIO7 (0x0 << 9)
1626#define RT5659_GP7_PIN_PDM_SCL (0x1 << 9)
1627#define RT5659_GP8_PIN_MASK (0x1 << 8)
1628#define RT5659_GP8_PIN_SFT 8
1629#define RT5659_GP8_PIN_GPIO8 (0x0 << 8)
1630#define RT5659_GP8_PIN_PDM_SDA (0x1 << 8)
1631#define RT5659_GP9_PIN_MASK (0x1 << 7)
1632#define RT5659_GP9_PIN_SFT 7
1633#define RT5659_GP9_PIN_GPIO9 (0x0 << 7)
1634#define RT5659_GP9_PIN_DMIC1_SDA (0x1 << 7)
1635#define RT5659_GP10_PIN_MASK (0x1 << 6)
1636#define RT5659_GP10_PIN_SFT 6
1637#define RT5659_GP10_PIN_GPIO10 (0x0 << 6)
1638#define RT5659_GP10_PIN_DMIC2_SDA (0x1 << 6)
1639#define RT5659_GP11_PIN_MASK (0x1 << 5)
1640#define RT5659_GP11_PIN_SFT 5
1641#define RT5659_GP11_PIN_GPIO11 (0x0 << 5)
1642#define RT5659_GP11_PIN_DMIC1_SDA (0x1 << 5)
1643#define RT5659_GP12_PIN_MASK (0x1 << 4)
1644#define RT5659_GP12_PIN_SFT 4
1645#define RT5659_GP12_PIN_GPIO12 (0x0 << 4)
1646#define RT5659_GP12_PIN_DMIC2_SDA (0x1 << 4)
1647#define RT5659_GP13_PIN_MASK (0x3 << 2)
1648#define RT5659_GP13_PIN_SFT 2
1649#define RT5659_GP13_PIN_GPIO13 (0x0 << 2)
1650#define RT5659_GP13_PIN_SPDIF_SDA (0x1 << 2)
1651#define RT5659_GP13_PIN_DMIC2_SCL (0x2 << 2)
1652#define RT5659_GP13_PIN_PDM_SCL (0x3 << 2)
1653#define RT5659_GP15_PIN_MASK (0x3)
1654#define RT5659_GP15_PIN_SFT 0
1655#define RT5659_GP15_PIN_GPIO15 (0x0)
1656#define RT5659_GP15_PIN_DMIC3_SCL (0x1)
1657#define RT5659_GP15_PIN_PDM_SDA (0x2)
1658
1659/* GPIO Control 2 (0x00c1)*/
1660#define RT5659_GP1_PF_IN (0x0 << 2)
1661#define RT5659_GP1_PF_OUT (0x1 << 2)
1662#define RT5659_GP1_PF_MASK (0x1 << 2)
1663#define RT5659_GP1_PF_SFT 2
1664
1665/* GPIO Control 3 (0x00c2) */
1666#define RT5659_I2S2_PIN_MASK (0x1 << 15)
1667#define RT5659_I2S2_PIN_SFT 15
1668#define RT5659_I2S2_PIN_I2S (0x0 << 15)
1669#define RT5659_I2S2_PIN_GPIO (0x1 << 15)
1670
1671/* Soft volume and zero cross control 1 (0x00d9) */
1672#define RT5659_SV_MASK (0x1 << 15)
1673#define RT5659_SV_SFT 15
1674#define RT5659_SV_DIS (0x0 << 15)
1675#define RT5659_SV_EN (0x1 << 15)
1676#define RT5659_OUT_SV_MASK (0x1 << 13)
1677#define RT5659_OUT_SV_SFT 13
1678#define RT5659_OUT_SV_DIS (0x0 << 13)
1679#define RT5659_OUT_SV_EN (0x1 << 13)
1680#define RT5659_HP_SV_MASK (0x1 << 12)
1681#define RT5659_HP_SV_SFT 12
1682#define RT5659_HP_SV_DIS (0x0 << 12)
1683#define RT5659_HP_SV_EN (0x1 << 12)
1684#define RT5659_ZCD_DIG_MASK (0x1 << 11)
1685#define RT5659_ZCD_DIG_SFT 11
1686#define RT5659_ZCD_DIG_DIS (0x0 << 11)
1687#define RT5659_ZCD_DIG_EN (0x1 << 11)
1688#define RT5659_ZCD_MASK (0x1 << 10)
1689#define RT5659_ZCD_SFT 10
1690#define RT5659_ZCD_PD (0x0 << 10)
1691#define RT5659_ZCD_PU (0x1 << 10)
1692#define RT5659_SV_DLY_MASK (0xf)
1693#define RT5659_SV_DLY_SFT 0
1694
1695/* Soft volume and zero cross control 2 (0x00da) */
1696#define RT5659_ZCD_HP_MASK (0x1 << 15)
1697#define RT5659_ZCD_HP_SFT 15
1698#define RT5659_ZCD_HP_DIS (0x0 << 15)
1699#define RT5659_ZCD_HP_EN (0x1 << 15)
1700
1701/* 4 Button Inline Command Control 2 (0x00e0) */
1702#define RT5659_4BTN_IL_MASK (0x1 << 15)
1703#define RT5659_4BTN_IL_EN (0x1 << 15)
1704#define RT5659_4BTN_IL_DIS (0x0 << 15)
1705
1706/* Analog JD Control 1 (0x00f0) */
1707#define RT5659_JD1_MODE_MASK (0x3 << 0)
1708#define RT5659_JD1_MODE_0 (0x0 << 0)
1709#define RT5659_JD1_MODE_1 (0x1 << 0)
1710#define RT5659_JD1_MODE_2 (0x2 << 0)
1711
1712/* Jack Detect Control 3 (0x00f8) */
1713#define RT5659_JD_TRI_HPO_SEL_MASK (0x7)
1714#define RT5659_JD_TRI_HPO_SEL_SFT (0)
1715#define RT5659_JD_HPO_GPIO_JD1 (0x0)
1716#define RT5659_JD_HPO_JD1_1 (0x1)
1717#define RT5659_JD_HPO_JD1_2 (0x2)
1718#define RT5659_JD_HPO_JD2 (0x3)
1719#define RT5659_JD_HPO_GPIO_JD2 (0x4)
1720#define RT5659_JD_HPO_JD3 (0x5)
1721#define RT5659_JD_HPO_JD_D (0x6)
1722
1723/* Digital Misc Control (0x00fa) */
1724#define RT5659_AM_MASK (0x1 << 7)
1725#define RT5659_AM_EN (0x1 << 7)
1726#define RT5659_AM_DIS (0x1 << 7)
1727#define RT5659_DIG_GATE_CTRL 0x1
1728#define RT5659_DIG_GATE_CTRL_SFT (0)
1729
1730/* Chopper and Clock control for ADC (0x011c)*/
1731#define RT5659_M_RF_DIG_MASK (0x1 << 12)
1732#define RT5659_M_RF_DIG_SFT 12
1733#define RT5659_M_RI_DIG (0x1 << 11)
1734
1735/* Chopper and Clock control for DAC (0x013a)*/
1736#define RT5659_CKXEN_DAC1_MASK (0x1 << 13)
1737#define RT5659_CKXEN_DAC1_SFT 13
1738#define RT5659_CKGEN_DAC1_MASK (0x1 << 12)
1739#define RT5659_CKGEN_DAC1_SFT 12
1740#define RT5659_CKXEN_DAC2_MASK (0x1 << 5)
1741#define RT5659_CKXEN_DAC2_SFT 5
1742#define RT5659_CKGEN_DAC2_MASK (0x1 << 4)
1743#define RT5659_CKGEN_DAC2_SFT 4
1744
1745/* Chopper and Clock control for ADC (0x013b)*/
1746#define RT5659_CKXEN_ADCC_MASK (0x1 << 13)
1747#define RT5659_CKXEN_ADCC_SFT 13
1748#define RT5659_CKGEN_ADCC_MASK (0x1 << 12)
1749#define RT5659_CKGEN_ADCC_SFT 12
1750
1751/* Test Mode Control 1 (0x0145) */
1752#define RT5659_AD2DA_LB_MASK (0x1 << 9)
1753#define RT5659_AD2DA_LB_SFT 9
1754
1755/* Stereo Noise Gate Control 1 (0x0160) */
1756#define RT5659_NG2_EN_MASK (0x1 << 15)
1757#define RT5659_NG2_EN (0x1 << 15)
1758#define RT5659_NG2_DIS (0x0 << 15)
1759
1760/* System Clock Source */
1761enum {
1762 RT5659_SCLK_S_MCLK,
1763 RT5659_SCLK_S_PLL1,
1764 RT5659_SCLK_S_RCCLK,
1765};
1766
1767/* PLL1 Source */
1768enum {
1769 RT5659_PLL1_S_MCLK,
1770 RT5659_PLL1_S_BCLK1,
1771 RT5659_PLL1_S_BCLK2,
1772 RT5659_PLL1_S_BCLK3,
1773 RT5659_PLL1_S_BCLK4,
1774};
1775
1776enum {
1777 RT5659_AIF1,
1778 RT5659_AIF2,
1779 RT5659_AIF3,
1780 RT5659_AIF4,
1781 RT5659_AIFS,
1782};
1783
1784struct rt5659_pll_code {
1785 bool m_bp;
1786 int m_code;
1787 int n_code;
1788 int k_code;
1789};
1790
1791struct rt5659_priv {
1792 struct snd_soc_codec *codec;
1793 struct rt5659_platform_data pdata;
1794 struct regmap *regmap;
Bard Liaod3cb2de2015-11-09 14:47:34 +08001795 struct gpio_desc *gpiod_ldo1_en;
1796 struct gpio_desc *gpiod_reset;
1797 struct snd_soc_jack *hs_jack;
1798 struct delayed_work jack_detect_work;
Nicolin Chenc6f87692016-07-28 14:57:16 -07001799 struct clk *mclk;
Bard Liaod3cb2de2015-11-09 14:47:34 +08001800
1801 int sysclk;
1802 int sysclk_src;
1803 int lrck[RT5659_AIFS];
1804 int bclk[RT5659_AIFS];
1805 int master[RT5659_AIFS];
1806 int v_id;
1807
1808 int pll_src;
1809 int pll_in;
1810 int pll_out;
1811
1812 int jack_type;
1813
1814};
1815
1816int rt5659_set_jack_detect(struct snd_soc_codec *codec,
1817 struct snd_soc_jack *hs_jack);
1818
1819#endif /* __RT5659_H__ */