Blame - drivers/gpu/msm/a6xx_reg.h - kernel/msm-4.9

2016-06-01 11:11:27 -0700

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*

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* This program is free software; you can redistribute it and/or modify

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* it under the terms of the GNU General Public License version 2 and

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* only version 2 as published by the Free Software Foundation.

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*

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* This program is distributed in the hope that it will be useful,

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* GNU General Public License for more details.

*

*/

#ifndef _A6XX_REG_H

#define _A6XX_REG_H

/* A6XX interrupt bits */

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#define A6XX_INT_RBBM_GPU_IDLE 0

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#define A6XX_INT_CP_AHB_ERROR 1

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#define A6XX_INT_ATB_ASYNCFIFO_OVERFLOW 6

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#define A6XX_INT_RBBM_GPC_ERROR 7

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#define A6XX_INT_CP_SW 8

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#define A6XX_INT_CP_HW_ERROR 9

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#define A6XX_INT_CP_CCU_FLUSH_DEPTH_TS 10

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#define A6XX_INT_CP_CCU_FLUSH_COLOR_TS 11

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#define A6XX_INT_CP_CCU_RESOLVE_TS 12

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#define A6XX_INT_CP_IB2 13

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#define A6XX_INT_CP_IB1 14

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#define A6XX_INT_CP_RB 15

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#define A6XX_INT_CP_RB_DONE_TS 17

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#define A6XX_INT_CP_WT_DONE_TS 18

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#define A6XX_INT_CP_CACHE_FLUSH_TS 20

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#define A6XX_INT_RBBM_ATB_BUS_OVERFLOW 22

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#define A6XX_INT_RBBM_HANG_DETECT 23

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#define A6XX_INT_UCHE_OOB_ACCESS 24

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#define A6XX_INT_UCHE_TRAP_INTR 25

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#define A6XX_INT_DEBBUS_INTR_0 26

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#define A6XX_INT_DEBBUS_INTR_1 27

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#define A6XX_INT_ISDB_CPU_IRQ 30

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#define A6XX_INT_ISDB_UNDER_DEBUG 31

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/* CP Interrupt bits */

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#define A6XX_CP_OPCODE_ERROR 0

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#define A6XX_CP_UCODE_ERROR 1

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#define A6XX_CP_HW_FAULT_ERROR 2

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#define A6XX_CP_REGISTER_PROTECTION_ERROR 4

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#define A6XX_CP_AHB_ERROR 5

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#define A6XX_CP_VSD_PARITY_ERROR 6

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#define A6XX_CP_ILLEGAL_INSTR_ERROR 7

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/* CP registers */

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#define A6XX_CP_RB_BASE 0x800

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#define A6XX_CP_RB_BASE_HI 0x801

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#define A6XX_CP_RB_CNTL 0x802

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#define A6XX_CP_RB_RPTR_ADDR_LO 0x804

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#define A6XX_CP_RB_RPTR_ADDR_HI 0x805

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#define A6XX_CP_RB_RPTR 0x806

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#define A6XX_CP_RB_WPTR 0x807

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#define A6XX_CP_SQE_CNTL 0x808

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#define A6XX_CP_HW_FAULT 0x821

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#define A6XX_CP_INTERRUPT_STATUS 0x823

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#define A6XX_CP_PROTECT_STATUS 0X824

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#define A6XX_CP_SQE_INSTR_BASE_LO 0x830

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#define A6XX_CP_SQE_INSTR_BASE_HI 0x831

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#define A6XX_CP_MISC_CNTL 0x840

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#define A6XX_CP_ROQ_THRESHOLDS_1 0x8C1

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#define A6XX_CP_ROQ_THRESHOLDS_2 0x8C2

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#define A6XX_CP_MEM_POOL_SIZE 0x8C3

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#define A6XX_CP_CHICKEN_DBG 0x841

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#define A6XX_CP_ADDR_MODE_CNTL 0x842

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#define A6XX_CP_DBG_ECO_CNTL 0x843

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#define A6XX_CP_PROTECT_CNTL 0x84F

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#define A6XX_CP_PROTECT_REG 0x850

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#define A6XX_CP_CONTEXT_SWITCH_CNTL 0x8A0

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#define A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x8A1

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#define A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x8A2

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#define A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO 0x8A3

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#define A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI 0x8A4

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#define A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO 0x8A5

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#define A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI 0x8A6

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#define A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO 0x8A7

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#define A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x8A8

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#define A6XX_CP_CONTEXT_SWITCH_LEVEL_STATUS 0x8AB

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#define A6XX_CP_PERFCTR_CP_SEL_0 0x8D0

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#define A6XX_CP_PERFCTR_CP_SEL_1 0x8D1

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#define A6XX_CP_PERFCTR_CP_SEL_2 0x8D2

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#define A6XX_CP_PERFCTR_CP_SEL_3 0x8D3

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#define A6XX_CP_PERFCTR_CP_SEL_4 0x8D4

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#define A6XX_CP_PERFCTR_CP_SEL_5 0x8D5

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#define A6XX_CP_PERFCTR_CP_SEL_6 0x8D6

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#define A6XX_CP_PERFCTR_CP_SEL_7 0x8D7

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#define A6XX_CP_PERFCTR_CP_SEL_8 0x8D8

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#define A6XX_CP_PERFCTR_CP_SEL_9 0x8D9

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#define A6XX_CP_PERFCTR_CP_SEL_10 0x8DA

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#define A6XX_CP_PERFCTR_CP_SEL_11 0x8DB

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#define A6XX_CP_PERFCTR_CP_SEL_12 0x8DC

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#define A6XX_CP_PERFCTR_CP_SEL_13 0x8DD

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#define A6XX_CP_CRASH_SCRIPT_BASE_LO 0x900

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#define A6XX_CP_CRASH_SCRIPT_BASE_HI 0x901

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#define A6XX_CP_CRASH_DUMP_CNTL 0x902

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#define A6XX_CP_CRASH_DUMP_STATUS 0x903

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#define A6XX_CP_SQE_STAT_ADDR 0x908

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#define A6XX_CP_SQE_STAT_DATA 0x909

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#define A6XX_CP_DRAW_STATE_ADDR 0x90A

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#define A6XX_CP_DRAW_STATE_DATA 0x90B

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#define A6XX_CP_ROQ_DBG_ADDR 0x90C

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#define A6XX_CP_ROQ_DBG_DATA 0x90D

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#define A6XX_CP_MEM_POOL_DBG_ADDR 0x90E

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#define A6XX_CP_MEM_POOL_DBG_DATA 0x90F

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#define A6XX_CP_SQE_UCODE_DBG_ADDR 0x910

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#define A6XX_CP_SQE_UCODE_DBG_DATA 0x911

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#define A6XX_CP_IB1_BASE 0x928

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#define A6XX_CP_IB1_BASE_HI 0x929

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#define A6XX_CP_IB1_REM_SIZE 0x92A

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#define A6XX_CP_IB2_BASE 0x92B

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#define A6XX_CP_IB2_BASE_HI 0x92C

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#define A6XX_CP_IB2_REM_SIZE 0x92D

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#define A6XX_CP_ALWAYS_ON_COUNTER_LO 0x980

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#define A6XX_CP_ALWAYS_ON_COUNTER_HI 0x981

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#define A6XX_CP_AHB_CNTL 0x98D

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#define A6XX_CP_APERTURE_CNTL_HOST 0xA00

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#define A6XX_CP_APERTURE_CNTL_CD 0xA03

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#define A6XX_VSC_ADDR_MODE_CNTL 0xC01

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/* RBBM registers */

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#define A6XX_RBBM_INT_0_STATUS 0x201

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#define A6XX_RBBM_STATUS 0x210

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#define A6XX_RBBM_STATUS3 0x213

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#define A6XX_RBBM_VBIF_GX_RESET_STATUS 0x215

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#define A6XX_RBBM_PERFCTR_CP_0_LO 0x400

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#define A6XX_RBBM_PERFCTR_CP_0_HI 0x401

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#define A6XX_RBBM_PERFCTR_CP_1_LO 0x402

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#define A6XX_RBBM_PERFCTR_CP_1_HI 0x403

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#define A6XX_RBBM_PERFCTR_CP_2_LO 0x404

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#define A6XX_RBBM_PERFCTR_CP_2_HI 0x405

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#define A6XX_RBBM_PERFCTR_CP_3_LO 0x406

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#define A6XX_RBBM_PERFCTR_CP_3_HI 0x407

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#define A6XX_RBBM_PERFCTR_CP_4_LO 0x408

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#define A6XX_RBBM_PERFCTR_CP_4_HI 0x409

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#define A6XX_RBBM_PERFCTR_CP_5_LO 0x40a

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#define A6XX_RBBM_PERFCTR_CP_5_HI 0x40b

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#define A6XX_RBBM_PERFCTR_CP_6_LO 0x40c

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#define A6XX_RBBM_PERFCTR_CP_6_HI 0x40d

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#define A6XX_RBBM_PERFCTR_CP_7_LO 0x40e

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#define A6XX_RBBM_PERFCTR_CP_7_HI 0x40f

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#define A6XX_RBBM_PERFCTR_CP_8_LO 0x410

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#define A6XX_RBBM_PERFCTR_CP_8_HI 0x411

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#define A6XX_RBBM_PERFCTR_CP_9_LO 0x412

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#define A6XX_RBBM_PERFCTR_CP_9_HI 0x413

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#define A6XX_RBBM_PERFCTR_CP_10_LO 0x414

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#define A6XX_RBBM_PERFCTR_CP_10_HI 0x415

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#define A6XX_RBBM_PERFCTR_CP_11_LO 0x416

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#define A6XX_RBBM_PERFCTR_CP_11_HI 0x417

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#define A6XX_RBBM_PERFCTR_CP_12_LO 0x418

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#define A6XX_RBBM_PERFCTR_CP_12_HI 0x419

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#define A6XX_RBBM_PERFCTR_CP_13_LO 0x41a

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#define A6XX_RBBM_PERFCTR_CP_13_HI 0x41b

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#define A6XX_RBBM_PERFCTR_RBBM_0_LO 0x41c

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#define A6XX_RBBM_PERFCTR_RBBM_0_HI 0x41d

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#define A6XX_RBBM_PERFCTR_RBBM_1_LO 0x41e

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#define A6XX_RBBM_PERFCTR_RBBM_1_HI 0x41f

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#define A6XX_RBBM_PERFCTR_RBBM_2_LO 0x420

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#define A6XX_RBBM_PERFCTR_RBBM_2_HI 0x421

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#define A6XX_RBBM_PERFCTR_RBBM_3_LO 0x422

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#define A6XX_RBBM_PERFCTR_RBBM_3_HI 0x423

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#define A6XX_RBBM_PERFCTR_PC_0_LO 0x424

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#define A6XX_RBBM_PERFCTR_PC_0_HI 0x425

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#define A6XX_RBBM_PERFCTR_PC_1_LO 0x426

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#define A6XX_RBBM_PERFCTR_PC_1_HI 0x427

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#define A6XX_RBBM_PERFCTR_PC_2_LO 0x428

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#define A6XX_RBBM_PERFCTR_PC_2_HI 0x429

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#define A6XX_RBBM_PERFCTR_PC_3_LO 0x42a

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#define A6XX_RBBM_PERFCTR_PC_3_HI 0x42b

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#define A6XX_RBBM_PERFCTR_PC_4_LO 0x42c

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#define A6XX_RBBM_PERFCTR_PC_4_HI 0x42d

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#define A6XX_RBBM_PERFCTR_PC_5_LO 0x42e

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#define A6XX_RBBM_PERFCTR_PC_5_HI 0x42f

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#define A6XX_RBBM_PERFCTR_PC_6_LO 0x430

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#define A6XX_RBBM_PERFCTR_PC_6_HI 0x431

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#define A6XX_RBBM_PERFCTR_PC_7_LO 0x432

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#define A6XX_RBBM_PERFCTR_PC_7_HI 0x433

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#define A6XX_RBBM_PERFCTR_VFD_0_LO 0x434

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#define A6XX_RBBM_PERFCTR_VFD_0_HI 0x435

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#define A6XX_RBBM_PERFCTR_VFD_1_LO 0x436

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#define A6XX_RBBM_PERFCTR_VFD_1_HI 0x437

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#define A6XX_RBBM_PERFCTR_VFD_2_LO 0x438

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#define A6XX_RBBM_PERFCTR_VFD_2_HI 0x439

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#define A6XX_RBBM_PERFCTR_VFD_3_LO 0x43a

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#define A6XX_RBBM_PERFCTR_VFD_3_HI 0x43b

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#define A6XX_RBBM_PERFCTR_VFD_4_LO 0x43c

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#define A6XX_RBBM_PERFCTR_VFD_4_HI 0x43d

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#define A6XX_RBBM_PERFCTR_VFD_5_LO 0x43e

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#define A6XX_RBBM_PERFCTR_VFD_5_HI 0x43f

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#define A6XX_RBBM_PERFCTR_VFD_6_LO 0x440

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#define A6XX_RBBM_PERFCTR_VFD_6_HI 0x441

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#define A6XX_RBBM_PERFCTR_VFD_7_LO 0x442

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#define A6XX_RBBM_PERFCTR_VFD_7_HI 0x443

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#define A6XX_RBBM_PERFCTR_HLSQ_0_LO 0x444

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#define A6XX_RBBM_PERFCTR_HLSQ_0_HI 0x445

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#define A6XX_RBBM_PERFCTR_HLSQ_1_LO 0x446

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#define A6XX_RBBM_PERFCTR_HLSQ_1_HI 0x447

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#define A6XX_RBBM_PERFCTR_HLSQ_2_LO 0x448

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#define A6XX_RBBM_PERFCTR_HLSQ_2_HI 0x449

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#define A6XX_RBBM_PERFCTR_HLSQ_3_LO 0x44a

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#define A6XX_RBBM_PERFCTR_HLSQ_3_HI 0x44b

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#define A6XX_RBBM_PERFCTR_HLSQ_4_LO 0x44c

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#define A6XX_RBBM_PERFCTR_HLSQ_4_HI 0x44d

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#define A6XX_RBBM_PERFCTR_HLSQ_5_LO 0x44e

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#define A6XX_RBBM_PERFCTR_HLSQ_5_HI 0x44f

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#define A6XX_RBBM_PERFCTR_VPC_0_LO 0x450

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#define A6XX_RBBM_PERFCTR_VPC_0_HI 0x451

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#define A6XX_RBBM_PERFCTR_VPC_1_LO 0x452

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#define A6XX_RBBM_PERFCTR_VPC_1_HI 0x453

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#define A6XX_RBBM_PERFCTR_VPC_2_LO 0x454

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#define A6XX_RBBM_PERFCTR_VPC_2_HI 0x455

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#define A6XX_RBBM_PERFCTR_VPC_3_LO 0x456

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#define A6XX_RBBM_PERFCTR_VPC_3_HI 0x457

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#define A6XX_RBBM_PERFCTR_VPC_4_LO 0x458

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#define A6XX_RBBM_PERFCTR_VPC_4_HI 0x459

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#define A6XX_RBBM_PERFCTR_VPC_5_LO 0x45a

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#define A6XX_RBBM_PERFCTR_VPC_5_HI 0x45b

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#define A6XX_RBBM_PERFCTR_CCU_0_LO 0x45c

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#define A6XX_RBBM_PERFCTR_CCU_0_HI 0x45d

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#define A6XX_RBBM_PERFCTR_CCU_1_LO 0x45e

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#define A6XX_RBBM_PERFCTR_CCU_1_HI 0x45f

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#define A6XX_RBBM_PERFCTR_CCU_2_LO 0x460

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#define A6XX_RBBM_PERFCTR_CCU_2_HI 0x461

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#define A6XX_RBBM_PERFCTR_CCU_3_LO 0x462

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#define A6XX_RBBM_PERFCTR_CCU_3_HI 0x463

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#define A6XX_RBBM_PERFCTR_CCU_4_LO 0x464

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#define A6XX_RBBM_PERFCTR_CCU_4_HI 0x465

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#define A6XX_RBBM_PERFCTR_TSE_0_LO 0x466

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#define A6XX_RBBM_PERFCTR_TSE_0_HI 0x467

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#define A6XX_RBBM_PERFCTR_TSE_1_LO 0x468

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#define A6XX_RBBM_PERFCTR_TSE_1_HI 0x469

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#define A6XX_RBBM_PERFCTR_TSE_2_LO 0x46a

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#define A6XX_RBBM_PERFCTR_CCU_4_HI 0x465

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#define A6XX_RBBM_PERFCTR_TSE_0_LO 0x466

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#define A6XX_RBBM_PERFCTR_TSE_0_HI 0x467

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#define A6XX_RBBM_PERFCTR_TSE_1_LO 0x468

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#define A6XX_RBBM_PERFCTR_TSE_1_HI 0x469

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#define A6XX_RBBM_PERFCTR_TSE_2_LO 0x46a

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#define A6XX_RBBM_PERFCTR_TSE_2_HI 0x46b

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#define A6XX_RBBM_PERFCTR_TSE_3_LO 0x46c

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#define A6XX_RBBM_PERFCTR_TSE_3_HI 0x46d

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#define A6XX_RBBM_PERFCTR_RAS_0_LO 0x46e

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#define A6XX_RBBM_PERFCTR_RAS_0_HI 0x46f

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#define A6XX_RBBM_PERFCTR_RAS_1_LO 0x470

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#define A6XX_RBBM_PERFCTR_RAS_1_HI 0x471

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#define A6XX_RBBM_PERFCTR_RAS_2_LO 0x472

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#define A6XX_RBBM_PERFCTR_RAS_2_HI 0x473

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#define A6XX_RBBM_PERFCTR_RAS_3_LO 0x474

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#define A6XX_RBBM_PERFCTR_RAS_3_HI 0x475

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#define A6XX_RBBM_PERFCTR_UCHE_0_LO 0x476

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#define A6XX_RBBM_PERFCTR_UCHE_0_HI 0x477

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#define A6XX_RBBM_PERFCTR_UCHE_1_LO 0x478

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#define A6XX_RBBM_PERFCTR_UCHE_1_HI 0x479

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#define A6XX_RBBM_PERFCTR_UCHE_2_LO 0x47a

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#define A6XX_RBBM_PERFCTR_UCHE_2_HI 0x47b

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#define A6XX_RBBM_PERFCTR_UCHE_3_LO 0x47c

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#define A6XX_RBBM_PERFCTR_UCHE_3_HI 0x47d

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#define A6XX_RBBM_PERFCTR_UCHE_4_LO 0x47e

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#define A6XX_RBBM_PERFCTR_UCHE_4_HI 0x47f

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#define A6XX_RBBM_PERFCTR_UCHE_5_LO 0x480

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#define A6XX_RBBM_PERFCTR_UCHE_5_HI 0x481

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#define A6XX_RBBM_PERFCTR_UCHE_6_LO 0x482

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#define A6XX_RBBM_PERFCTR_UCHE_6_HI 0x483

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#define A6XX_RBBM_PERFCTR_UCHE_7_LO 0x484

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#define A6XX_RBBM_PERFCTR_UCHE_7_HI 0x485

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#define A6XX_RBBM_PERFCTR_UCHE_8_LO 0x486

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#define A6XX_RBBM_PERFCTR_UCHE_8_HI 0x487

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#define A6XX_RBBM_PERFCTR_UCHE_9_LO 0x488

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#define A6XX_RBBM_PERFCTR_UCHE_9_HI 0x489

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#define A6XX_RBBM_PERFCTR_UCHE_10_LO 0x48a

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#define A6XX_RBBM_PERFCTR_UCHE_10_HI 0x48b

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#define A6XX_RBBM_PERFCTR_UCHE_11_LO 0x48c

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#define A6XX_RBBM_PERFCTR_UCHE_11_HI 0x48d

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#define A6XX_RBBM_PERFCTR_TP_0_LO 0x48e

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#define A6XX_RBBM_PERFCTR_TP_0_HI 0x48f

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#define A6XX_RBBM_PERFCTR_TP_1_LO 0x490

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#define A6XX_RBBM_PERFCTR_TP_1_HI 0x491

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#define A6XX_RBBM_PERFCTR_TP_2_LO 0x492

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#define A6XX_RBBM_PERFCTR_TP_2_HI 0x493

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#define A6XX_RBBM_PERFCTR_TP_3_LO 0x494

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#define A6XX_RBBM_PERFCTR_TP_3_HI 0x495

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#define A6XX_RBBM_PERFCTR_TP_4_LO 0x496

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#define A6XX_RBBM_PERFCTR_TP_4_HI 0x497

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#define A6XX_RBBM_PERFCTR_TP_5_LO 0x498

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#define A6XX_RBBM_PERFCTR_TP_5_HI 0x499

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#define A6XX_RBBM_PERFCTR_TP_6_LO 0x49a

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#define A6XX_RBBM_PERFCTR_TP_6_HI 0x49b

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#define A6XX_RBBM_PERFCTR_TP_7_LO 0x49c

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#define A6XX_RBBM_PERFCTR_TP_7_HI 0x49d

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#define A6XX_RBBM_PERFCTR_TP_8_LO 0x49e

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#define A6XX_RBBM_PERFCTR_TP_8_HI 0x49f

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#define A6XX_RBBM_PERFCTR_TP_9_LO 0x4a0

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#define A6XX_RBBM_PERFCTR_TP_9_HI 0x4a1

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#define A6XX_RBBM_PERFCTR_TP_10_LO 0x4a2

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#define A6XX_RBBM_PERFCTR_TP_10_HI 0x4a3

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#define A6XX_RBBM_PERFCTR_TP_11_LO 0x4a4

301

#define A6XX_RBBM_PERFCTR_TP_11_HI 0x4a5

302

#define A6XX_RBBM_PERFCTR_SP_0_LO 0x4a6

303

#define A6XX_RBBM_PERFCTR_SP_0_HI 0x4a7

304

#define A6XX_RBBM_PERFCTR_SP_1_LO 0x4a8

305

#define A6XX_RBBM_PERFCTR_SP_1_HI 0x4a9

306

#define A6XX_RBBM_PERFCTR_SP_2_LO 0x4aa

307

#define A6XX_RBBM_PERFCTR_SP_2_HI 0x4ab

308

#define A6XX_RBBM_PERFCTR_SP_3_LO 0x4ac

309

#define A6XX_RBBM_PERFCTR_SP_3_HI 0x4ad

310

#define A6XX_RBBM_PERFCTR_SP_4_LO 0x4ae

311

#define A6XX_RBBM_PERFCTR_SP_4_HI 0x4af

312

#define A6XX_RBBM_PERFCTR_SP_5_LO 0x4b0

313

#define A6XX_RBBM_PERFCTR_SP_5_HI 0x4b1

314

#define A6XX_RBBM_PERFCTR_SP_6_LO 0x4b2

315

#define A6XX_RBBM_PERFCTR_SP_6_HI 0x4b3

316

#define A6XX_RBBM_PERFCTR_SP_7_LO 0x4b4

317

#define A6XX_RBBM_PERFCTR_SP_7_HI 0x4b5

318

#define A6XX_RBBM_PERFCTR_SP_8_LO 0x4b6

319

#define A6XX_RBBM_PERFCTR_SP_8_HI 0x4b7

320

#define A6XX_RBBM_PERFCTR_SP_9_LO 0x4b8

321

#define A6XX_RBBM_PERFCTR_SP_9_HI 0x4b9

322

#define A6XX_RBBM_PERFCTR_SP_10_LO 0x4ba

323

#define A6XX_RBBM_PERFCTR_SP_10_HI 0x4bb

324

#define A6XX_RBBM_PERFCTR_SP_11_LO 0x4bc

325

#define A6XX_RBBM_PERFCTR_SP_11_HI 0x4bd

326

#define A6XX_RBBM_PERFCTR_SP_12_LO 0x4be

327

#define A6XX_RBBM_PERFCTR_SP_12_HI 0x4bf

328

#define A6XX_RBBM_PERFCTR_SP_13_LO 0x4c0

329

#define A6XX_RBBM_PERFCTR_SP_13_HI 0x4c1

330

#define A6XX_RBBM_PERFCTR_SP_14_LO 0x4c2

331

#define A6XX_RBBM_PERFCTR_SP_14_HI 0x4c3

332

#define A6XX_RBBM_PERFCTR_SP_15_LO 0x4c4

333

#define A6XX_RBBM_PERFCTR_SP_15_HI 0x4c5

334

#define A6XX_RBBM_PERFCTR_SP_16_LO 0x4c6

335

#define A6XX_RBBM_PERFCTR_SP_16_HI 0x4c7

336

#define A6XX_RBBM_PERFCTR_SP_17_LO 0x4c8

337

#define A6XX_RBBM_PERFCTR_SP_17_HI 0x4c9

338

#define A6XX_RBBM_PERFCTR_SP_18_LO 0x4ca

339

#define A6XX_RBBM_PERFCTR_SP_18_HI 0x4cb

340

#define A6XX_RBBM_PERFCTR_SP_19_LO 0x4cc

341

#define A6XX_RBBM_PERFCTR_SP_19_HI 0x4cd

342

#define A6XX_RBBM_PERFCTR_SP_20_LO 0x4ce

343

#define A6XX_RBBM_PERFCTR_SP_20_HI 0x4cf

344

#define A6XX_RBBM_PERFCTR_SP_21_LO 0x4d0

345

#define A6XX_RBBM_PERFCTR_SP_21_HI 0x4d1

346

#define A6XX_RBBM_PERFCTR_SP_22_LO 0x4d2

347

#define A6XX_RBBM_PERFCTR_SP_22_HI 0x4d3

348

#define A6XX_RBBM_PERFCTR_SP_23_LO 0x4d4

349

#define A6XX_RBBM_PERFCTR_SP_23_HI 0x4d5

350

#define A6XX_RBBM_PERFCTR_RB_0_LO 0x4d6

351

#define A6XX_RBBM_PERFCTR_RB_0_HI 0x4d7

352

#define A6XX_RBBM_PERFCTR_RB_1_LO 0x4d8

353

#define A6XX_RBBM_PERFCTR_RB_1_HI 0x4d9

354

#define A6XX_RBBM_PERFCTR_RB_2_LO 0x4da

355

#define A6XX_RBBM_PERFCTR_RB_2_HI 0x4db

356

#define A6XX_RBBM_PERFCTR_RB_3_LO 0x4dc

357

#define A6XX_RBBM_PERFCTR_RB_3_HI 0x4dd

358

#define A6XX_RBBM_PERFCTR_RB_4_LO 0x4de

359

#define A6XX_RBBM_PERFCTR_RB_4_HI 0x4df

360

#define A6XX_RBBM_PERFCTR_RB_5_LO 0x4e0

361

#define A6XX_RBBM_PERFCTR_RB_5_HI 0x4e1

362

#define A6XX_RBBM_PERFCTR_RB_6_LO 0x4e2

363

#define A6XX_RBBM_PERFCTR_RB_6_HI 0x4e3

364

#define A6XX_RBBM_PERFCTR_RB_7_LO 0x4e4

365

#define A6XX_RBBM_PERFCTR_RB_7_HI 0x4e5

366

#define A6XX_RBBM_PERFCTR_VSC_0_LO 0x4e6

367

#define A6XX_RBBM_PERFCTR_VSC_0_HI 0x4e7

368

#define A6XX_RBBM_PERFCTR_VSC_1_LO 0x4e8

369

#define A6XX_RBBM_PERFCTR_VSC_1_HI 0x4e9

370

#define A6XX_RBBM_PERFCTR_LRZ_0_LO 0x4ea

371

#define A6XX_RBBM_PERFCTR_LRZ_0_HI 0x4eb

372

#define A6XX_RBBM_PERFCTR_LRZ_1_LO 0x4ec

373

#define A6XX_RBBM_PERFCTR_LRZ_1_HI 0x4ed

374

#define A6XX_RBBM_PERFCTR_LRZ_2_LO 0x4ee

375

#define A6XX_RBBM_PERFCTR_LRZ_2_HI 0x4ef

376

#define A6XX_RBBM_PERFCTR_LRZ_3_LO 0x4f0

377

#define A6XX_RBBM_PERFCTR_LRZ_3_HI 0x4f1

378

#define A6XX_RBBM_PERFCTR_CMP_0_LO 0x4f2

379

#define A6XX_RBBM_PERFCTR_CMP_0_HI 0x4f3

380

#define A6XX_RBBM_PERFCTR_CMP_1_LO 0x4f4

381

#define A6XX_RBBM_PERFCTR_CMP_1_HI 0x4f5

382

#define A6XX_RBBM_PERFCTR_CMP_2_LO 0x4f6

383

#define A6XX_RBBM_PERFCTR_CMP_2_HI 0x4f7

384

#define A6XX_RBBM_PERFCTR_CMP_3_LO 0x4f8

385

#define A6XX_RBBM_PERFCTR_CMP_3_HI 0x4f9

386

#define A6XX_RBBM_PERFCTR_CNTL 0x500

387

#define A6XX_RBBM_PERFCTR_LOAD_CMD0 0x501

388

#define A6XX_RBBM_PERFCTR_LOAD_CMD1 0x502

389

#define A6XX_RBBM_PERFCTR_LOAD_CMD2 0x503

390

#define A6XX_RBBM_PERFCTR_LOAD_CMD3 0x504

391

#define A6XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x505

392

#define A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x506

393

#define A6XX_RBBM_PERFCTR_RBBM_SEL_0 0x507

394

#define A6XX_RBBM_PERFCTR_RBBM_SEL_1 0x508

395

#define A6XX_RBBM_PERFCTR_RBBM_SEL_2 0x509

396

#define A6XX_RBBM_PERFCTR_RBBM_SEL_3 0x50A

Harshdeep Dhatt

75dbd41

2017-05-16 17:12:27 -0600

[diff] [blame]

397

#define A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x50B

Lynus Vaz

2017-03-01 13:48:06 +0530

[diff] [blame]

398

Oleg Perelet

2017-03-16 15:38:43 -0700

[diff] [blame]

399

#define A6XX_RBBM_ISDB_CNT 0x533

400

Shrenuj Bansal

2016-06-01 11:11:27 -0700

[diff] [blame]

401

#define A6XX_RBBM_SECVID_TRUST_CNTL 0xF400

Carter Cooper

4a313ae

2017-02-23 11:11:56 -0700

[diff] [blame]

402

#define A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0xF800

403

#define A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0xF801

404

#define A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0xF802

405

#define A6XX_RBBM_SECVID_TSB_CNTL 0xF803

Shrenuj Bansal

2016-06-01 11:11:27 -0700

[diff] [blame]

406

#define A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0xF810

407

Oleg Perelet

2017-03-16 15:38:43 -0700

[diff] [blame]

408

#define A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00010

Rajesh Kemisetti

d1ca954

2017-10-18 15:35:41 +0530

[diff] [blame]

409

#define A6XX_RBBM_GPR0_CNTL 0x00018

Oleg Perelet

2017-03-16 15:38:43 -0700

[diff] [blame]

410

#define A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0001f

411

#define A6XX_RBBM_INT_CLEAR_CMD 0x00037

412

#define A6XX_RBBM_INT_0_MASK 0x00038

413

#define A6XX_RBBM_SP_HYST_CNT 0x00042

414

#define A6XX_RBBM_SW_RESET_CMD 0x00043

415

#define A6XX_RBBM_RAC_THRESHOLD_CNT 0x00044

416

#define A6XX_RBBM_BLOCK_SW_RESET_CMD 0x00045

417

#define A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00046

418

#define A6XX_RBBM_CLOCK_CNTL 0x000ae

419

#define A6XX_RBBM_CLOCK_CNTL_SP0 0x000b0

420

#define A6XX_RBBM_CLOCK_CNTL_SP1 0x000b1

421

#define A6XX_RBBM_CLOCK_CNTL_SP2 0x000b2

422

#define A6XX_RBBM_CLOCK_CNTL_SP3 0x000b3

423

#define A6XX_RBBM_CLOCK_CNTL2_SP0 0x000b4

424

#define A6XX_RBBM_CLOCK_CNTL2_SP1 0x000b5

425

#define A6XX_RBBM_CLOCK_CNTL2_SP2 0x000b6

426

#define A6XX_RBBM_CLOCK_CNTL2_SP3 0x000b7

427

#define A6XX_RBBM_CLOCK_DELAY_SP0 0x000b8

428

#define A6XX_RBBM_CLOCK_DELAY_SP1 0x000b9

429

#define A6XX_RBBM_CLOCK_DELAY_SP2 0x000ba

430

#define A6XX_RBBM_CLOCK_DELAY_SP3 0x000bb

431

#define A6XX_RBBM_CLOCK_HYST_SP0 0x000bc

432

#define A6XX_RBBM_CLOCK_HYST_SP1 0x000bd

433

#define A6XX_RBBM_CLOCK_HYST_SP2 0x000be

434

#define A6XX_RBBM_CLOCK_HYST_SP3 0x000bf

435

#define A6XX_RBBM_CLOCK_CNTL_TP0 0x000c0

436

#define A6XX_RBBM_CLOCK_CNTL_TP1 0x000c1

437

#define A6XX_RBBM_CLOCK_CNTL_TP2 0x000c2

438

#define A6XX_RBBM_CLOCK_CNTL_TP3 0x000c3

439

#define A6XX_RBBM_CLOCK_CNTL2_TP0 0x000c4

440

#define A6XX_RBBM_CLOCK_CNTL2_TP1 0x000c5

441

#define A6XX_RBBM_CLOCK_CNTL2_TP2 0x000c6

442

#define A6XX_RBBM_CLOCK_CNTL2_TP3 0x000c7

443

#define A6XX_RBBM_CLOCK_CNTL3_TP0 0x000c8

444

#define A6XX_RBBM_CLOCK_CNTL3_TP1 0x000c9

445

#define A6XX_RBBM_CLOCK_CNTL3_TP2 0x000ca

446

#define A6XX_RBBM_CLOCK_CNTL3_TP3 0x000cb

447

#define A6XX_RBBM_CLOCK_CNTL4_TP0 0x000cc

448

#define A6XX_RBBM_CLOCK_CNTL4_TP1 0x000cd

449

#define A6XX_RBBM_CLOCK_CNTL4_TP2 0x000ce

450

#define A6XX_RBBM_CLOCK_CNTL4_TP3 0x000cf

451

#define A6XX_RBBM_CLOCK_DELAY_TP0 0x000d0

452

#define A6XX_RBBM_CLOCK_DELAY_TP1 0x000d1

453

#define A6XX_RBBM_CLOCK_DELAY_TP2 0x000d2

454

#define A6XX_RBBM_CLOCK_DELAY_TP3 0x000d3

455

#define A6XX_RBBM_CLOCK_DELAY2_TP0 0x000d4

456

#define A6XX_RBBM_CLOCK_DELAY2_TP1 0x000d5

457

#define A6XX_RBBM_CLOCK_DELAY2_TP2 0x000d6

458

#define A6XX_RBBM_CLOCK_DELAY2_TP3 0x000d7

459

#define A6XX_RBBM_CLOCK_DELAY3_TP0 0x000d8

460

#define A6XX_RBBM_CLOCK_DELAY3_TP1 0x000d9

461

#define A6XX_RBBM_CLOCK_DELAY3_TP2 0x000da

462

#define A6XX_RBBM_CLOCK_DELAY3_TP3 0x000db

463

#define A6XX_RBBM_CLOCK_DELAY4_TP0 0x000dc

464

#define A6XX_RBBM_CLOCK_DELAY4_TP1 0x000dd

465

#define A6XX_RBBM_CLOCK_DELAY4_TP2 0x000de

466

#define A6XX_RBBM_CLOCK_DELAY4_TP3 0x000df

467

#define A6XX_RBBM_CLOCK_HYST_TP0 0x000e0

468

#define A6XX_RBBM_CLOCK_HYST_TP1 0x000e1

469

#define A6XX_RBBM_CLOCK_HYST_TP2 0x000e2

470

#define A6XX_RBBM_CLOCK_HYST_TP3 0x000e3

471

#define A6XX_RBBM_CLOCK_HYST2_TP0 0x000e4

472

#define A6XX_RBBM_CLOCK_HYST2_TP1 0x000e5

473

#define A6XX_RBBM_CLOCK_HYST2_TP2 0x000e6

474

#define A6XX_RBBM_CLOCK_HYST2_TP3 0x000e7

475

#define A6XX_RBBM_CLOCK_HYST3_TP0 0x000e8

476

#define A6XX_RBBM_CLOCK_HYST3_TP1 0x000e9

477

#define A6XX_RBBM_CLOCK_HYST3_TP2 0x000ea

478

#define A6XX_RBBM_CLOCK_HYST3_TP3 0x000eb

479

#define A6XX_RBBM_CLOCK_HYST4_TP0 0x000ec

480

#define A6XX_RBBM_CLOCK_HYST4_TP1 0x000ed

481

#define A6XX_RBBM_CLOCK_HYST4_TP2 0x000ee

482

#define A6XX_RBBM_CLOCK_HYST4_TP3 0x000ef

483

#define A6XX_RBBM_CLOCK_CNTL_RB0 0x000f0

484

#define A6XX_RBBM_CLOCK_CNTL_RB1 0x000f1

485

#define A6XX_RBBM_CLOCK_CNTL_RB2 0x000f2

486

#define A6XX_RBBM_CLOCK_CNTL_RB3 0x000f3

487

#define A6XX_RBBM_CLOCK_CNTL2_RB0 0x000f4

488

#define A6XX_RBBM_CLOCK_CNTL2_RB1 0x000f5

489

#define A6XX_RBBM_CLOCK_CNTL2_RB2 0x000f6

490

#define A6XX_RBBM_CLOCK_CNTL2_RB3 0x000f7

491

#define A6XX_RBBM_CLOCK_CNTL_CCU0 0x000f8

492

#define A6XX_RBBM_CLOCK_CNTL_CCU1 0x000f9

493

#define A6XX_RBBM_CLOCK_CNTL_CCU2 0x000fa

494

#define A6XX_RBBM_CLOCK_CNTL_CCU3 0x000fb

495

#define A6XX_RBBM_CLOCK_HYST_RB_CCU0 0x00100

496

#define A6XX_RBBM_CLOCK_HYST_RB_CCU1 0x00101

497

#define A6XX_RBBM_CLOCK_HYST_RB_CCU2 0x00102

498

#define A6XX_RBBM_CLOCK_HYST_RB_CCU3 0x00103

499

#define A6XX_RBBM_CLOCK_CNTL_RAC 0x00104

500

#define A6XX_RBBM_CLOCK_CNTL2_RAC 0x00105

501

#define A6XX_RBBM_CLOCK_DELAY_RAC 0x00106

502

#define A6XX_RBBM_CLOCK_HYST_RAC 0x00107

503

#define A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00108

504

#define A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00109

505

#define A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0010a

506

#define A6XX_RBBM_CLOCK_CNTL_UCHE 0x0010b

507

#define A6XX_RBBM_CLOCK_CNTL2_UCHE 0x0010c

508

#define A6XX_RBBM_CLOCK_CNTL3_UCHE 0x0010d

509

#define A6XX_RBBM_CLOCK_CNTL4_UCHE 0x0010e

510

#define A6XX_RBBM_CLOCK_DELAY_UCHE 0x0010f

511

#define A6XX_RBBM_CLOCK_HYST_UCHE 0x00110

512

#define A6XX_RBBM_CLOCK_MODE_VFD 0x00111

513

#define A6XX_RBBM_CLOCK_DELAY_VFD 0x00112

514

#define A6XX_RBBM_CLOCK_HYST_VFD 0x00113

515

#define A6XX_RBBM_CLOCK_MODE_GPC 0x00114

516

#define A6XX_RBBM_CLOCK_DELAY_GPC 0x00115

517

#define A6XX_RBBM_CLOCK_HYST_GPC 0x00116

518

#define A6XX_RBBM_CLOCK_DELAY_HLSQ_2 0x00117

519

#define A6XX_RBBM_CLOCK_CNTL_GMU_GX 0x00118

520

#define A6XX_RBBM_CLOCK_DELAY_GMU_GX 0x00119

521

#define A6XX_RBBM_CLOCK_HYST_GMU_GX 0x0011a

522

#define A6XX_RBBM_CLOCK_MODE_HLSQ 0x0011b

523

#define A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0011c

524

Lynus Vaz

2017-02-10 16:22:12 +0530

[diff] [blame]

525

/* DBGC_CFG registers */

526

#define A6XX_DBGC_CFG_DBGBUS_SEL_A 0x600

527

#define A6XX_DBGC_CFG_DBGBUS_SEL_B 0x601

528

#define A6XX_DBGC_CFG_DBGBUS_SEL_C 0x602

529

#define A6XX_DBGC_CFG_DBGBUS_SEL_D 0x603

530

#define A6XX_DBGC_CFG_DBGBUS_SEL_PING_INDEX_SHIFT 0x0

531

#define A6XX_DBGC_CFG_DBGBUS_SEL_PING_BLK_SEL_SHIFT 0x8

532

#define A6XX_DBGC_CFG_DBGBUS_CNTLT 0x604

533

#define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN_SHIFT 0x0

534

#define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU_SHIFT 0xC

535

#define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT_SHIFT 0x1C

536

#define A6XX_DBGC_CFG_DBGBUS_CNTLM 0x605

537

#define A6XX_DBGC_CFG_DBGBUS_CTLTM_ENABLE_SHIFT 0x18

Lokesh Batra

2017-05-25 11:17:40 -0700

[diff] [blame]

538

#define A6XX_DBGC_CFG_DBGBUS_OPL 0x606

539

#define A6XX_DBGC_CFG_DBGBUS_OPE 0x607

Lynus Vaz

2017-02-10 16:22:12 +0530

[diff] [blame]

540

#define A6XX_DBGC_CFG_DBGBUS_IVTL_0 0x608

541

#define A6XX_DBGC_CFG_DBGBUS_IVTL_1 0x609

542

#define A6XX_DBGC_CFG_DBGBUS_IVTL_2 0x60a

543

#define A6XX_DBGC_CFG_DBGBUS_IVTL_3 0x60b

544

#define A6XX_DBGC_CFG_DBGBUS_MASKL_0 0x60c

545

#define A6XX_DBGC_CFG_DBGBUS_MASKL_1 0x60d

546

#define A6XX_DBGC_CFG_DBGBUS_MASKL_2 0x60e

547

#define A6XX_DBGC_CFG_DBGBUS_MASKL_3 0x60f

548

#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0 0x610

549

#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1 0x611

550

#define A6XX_DBGC_CFG_DBGBUS_BYTEL0_SHIFT 0x0

551

#define A6XX_DBGC_CFG_DBGBUS_BYTEL1_SHIFT 0x4

552

#define A6XX_DBGC_CFG_DBGBUS_BYTEL2_SHIFT 0x8

553

#define A6XX_DBGC_CFG_DBGBUS_BYTEL3_SHIFT 0xC

554

#define A6XX_DBGC_CFG_DBGBUS_BYTEL4_SHIFT 0x10

555

#define A6XX_DBGC_CFG_DBGBUS_BYTEL5_SHIFT 0x14

556

#define A6XX_DBGC_CFG_DBGBUS_BYTEL6_SHIFT 0x18

557

#define A6XX_DBGC_CFG_DBGBUS_BYTEL7_SHIFT 0x1C

558

#define A6XX_DBGC_CFG_DBGBUS_BYTEL8_SHIFT 0x0

559

#define A6XX_DBGC_CFG_DBGBUS_BYTEL9_SHIFT 0x4

560

#define A6XX_DBGC_CFG_DBGBUS_BYTEL10_SHIFT 0x8

561

#define A6XX_DBGC_CFG_DBGBUS_BYTEL11_SHIFT 0xC

562

#define A6XX_DBGC_CFG_DBGBUS_BYTEL12_SHIFT 0x10

563

#define A6XX_DBGC_CFG_DBGBUS_BYTEL13_SHIFT 0x14

564

#define A6XX_DBGC_CFG_DBGBUS_BYTEL14_SHIFT 0x18

565

#define A6XX_DBGC_CFG_DBGBUS_BYTEL15_SHIFT 0x1C

Lokesh Batra

2017-05-25 11:17:40 -0700

[diff] [blame]

566

#define A6XX_DBGC_CFG_DBGBUS_IVTE_0 0x612

567

#define A6XX_DBGC_CFG_DBGBUS_IVTE_1 0x613

568

#define A6XX_DBGC_CFG_DBGBUS_IVTE_2 0x614

569

#define A6XX_DBGC_CFG_DBGBUS_IVTE_3 0x615

570

#define A6XX_DBGC_CFG_DBGBUS_MASKE_0 0x616

571

#define A6XX_DBGC_CFG_DBGBUS_MASKE_1 0x617

572

#define A6XX_DBGC_CFG_DBGBUS_MASKE_2 0x618

573

#define A6XX_DBGC_CFG_DBGBUS_MASKE_3 0x619

574

#define A6XX_DBGC_CFG_DBGBUS_NIBBLEE 0x61a

575

#define A6XX_DBGC_CFG_DBGBUS_PTRC0 0x61b

576

#define A6XX_DBGC_CFG_DBGBUS_PTRC1 0x61c

577

#define A6XX_DBGC_CFG_DBGBUS_LOADREG 0x61d

578

#define A6XX_DBGC_CFG_DBGBUS_IDX 0x61e

579

#define A6XX_DBGC_CFG_DBGBUS_CLRC 0x61f

580

#define A6XX_DBGC_CFG_DBGBUS_LOADIVT 0x620

581

#define A6XX_DBGC_VBIF_DBG_CNTL 0x621

582

#define A6XX_DBGC_DBG_LO_HI_GPIO 0x622

583

#define A6XX_DBGC_EXT_TRACE_BUS_CNTL 0x623

584

#define A6XX_DBGC_READ_AHB_THROUGH_DBG 0x624

Lynus Vaz

2017-02-10 16:22:12 +0530

[diff] [blame]

585

#define A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x62f

586

#define A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x630

Lokesh Batra

2017-05-25 11:17:40 -0700

[diff] [blame]

587

#define A6XX_DBGC_EVT_CFG 0x640

588

#define A6XX_DBGC_EVT_INTF_SEL_0 0x641

589

#define A6XX_DBGC_EVT_INTF_SEL_1 0x642

590

#define A6XX_DBGC_PERF_ATB_CFG 0x643

591

#define A6XX_DBGC_PERF_ATB_COUNTER_SEL_0 0x644

592

#define A6XX_DBGC_PERF_ATB_COUNTER_SEL_1 0x645

593

#define A6XX_DBGC_PERF_ATB_COUNTER_SEL_2 0x646

594

#define A6XX_DBGC_PERF_ATB_COUNTER_SEL_3 0x647

595

#define A6XX_DBGC_PERF_ATB_TRIG_INTF_SEL_0 0x648

596

#define A6XX_DBGC_PERF_ATB_TRIG_INTF_SEL_1 0x649

597

#define A6XX_DBGC_PERF_ATB_DRAIN_CMD 0x64a

598

#define A6XX_DBGC_ECO_CNTL 0x650

599

#define A6XX_DBGC_AHB_DBG_CNTL 0x651

Lynus Vaz

2017-02-10 16:22:12 +0530

[diff] [blame]

600

Shrenuj Bansal

2016-06-01 11:11:27 -0700

[diff] [blame]

601

/* VSC registers */

Lynus Vaz

2017-03-01 13:48:06 +0530

[diff] [blame]

602

#define A6XX_VSC_PERFCTR_VSC_SEL_0 0xCD8

603

#define A6XX_VSC_PERFCTR_VSC_SEL_1 0xCD9

604

605

/* GRAS registers */

Shrenuj Bansal

2016-06-01 11:11:27 -0700

[diff] [blame]

606

#define A6XX_GRAS_ADDR_MODE_CNTL 0x8601

Lynus Vaz

2017-03-01 13:48:06 +0530

[diff] [blame]

607

#define A6XX_GRAS_PERFCTR_TSE_SEL_0 0x8610

608

#define A6XX_GRAS_PERFCTR_TSE_SEL_1 0x8611

609

#define A6XX_GRAS_PERFCTR_TSE_SEL_2 0x8612

610

#define A6XX_GRAS_PERFCTR_TSE_SEL_3 0x8613

611

#define A6XX_GRAS_PERFCTR_RAS_SEL_0 0x8614

612

#define A6XX_GRAS_PERFCTR_RAS_SEL_1 0x8615

613

#define A6XX_GRAS_PERFCTR_RAS_SEL_2 0x8616

614

#define A6XX_GRAS_PERFCTR_RAS_SEL_3 0x8617

615

#define A6XX_GRAS_PERFCTR_LRZ_SEL_0 0x8618

616

#define A6XX_GRAS_PERFCTR_LRZ_SEL_1 0x8619

617

#define A6XX_GRAS_PERFCTR_LRZ_SEL_2 0x861A

618

#define A6XX_GRAS_PERFCTR_LRZ_SEL_3 0x861B

Shrenuj Bansal

2016-06-01 11:11:27 -0700

[diff] [blame]

619

620

/* RB registers */

621

#define A6XX_RB_ADDR_MODE_CNTL 0x8E05

622

#define A6XX_RB_NC_MODE_CNTL 0x8E08

Lynus Vaz

2017-03-01 13:48:06 +0530

[diff] [blame]

623

#define A6XX_RB_PERFCTR_RB_SEL_0 0x8E10

624

#define A6XX_RB_PERFCTR_RB_SEL_1 0x8E11

625

#define A6XX_RB_PERFCTR_RB_SEL_2 0x8E12

626

#define A6XX_RB_PERFCTR_RB_SEL_3 0x8E13

627

#define A6XX_RB_PERFCTR_RB_SEL_4 0x8E14

628

#define A6XX_RB_PERFCTR_RB_SEL_5 0x8E15

629

#define A6XX_RB_PERFCTR_RB_SEL_6 0x8E16

630

#define A6XX_RB_PERFCTR_RB_SEL_7 0x8E17

631

#define A6XX_RB_PERFCTR_CCU_SEL_0 0x8E18

632

#define A6XX_RB_PERFCTR_CCU_SEL_1 0x8E19

633

#define A6XX_RB_PERFCTR_CCU_SEL_2 0x8E1A

634

#define A6XX_RB_PERFCTR_CCU_SEL_3 0x8E1B

635

#define A6XX_RB_PERFCTR_CCU_SEL_4 0x8E1C

636

#define A6XX_RB_PERFCTR_CMP_SEL_0 0x8E2C

637

#define A6XX_RB_PERFCTR_CMP_SEL_1 0x8E2D

638

#define A6XX_RB_PERFCTR_CMP_SEL_2 0x8E2E

639

#define A6XX_RB_PERFCTR_CMP_SEL_3 0x8E2F

Harshdeep Dhatt

a0cf241

2017-06-22 11:53:31 -0600

[diff] [blame]

640

#define A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST 0x8E3B

641

#define A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD 0x8E3D

Harshdeep Dhatt

0cdc899

2017-05-31 15:44:05 -0600

[diff] [blame]

642

#define A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x8E50

Shrenuj Bansal

2016-06-01 11:11:27 -0700

[diff] [blame]

643

644

/* PC registers */

645

#define A6XX_PC_DBG_ECO_CNTL 0x9E00

646

#define A6XX_PC_ADDR_MODE_CNTL 0x9E01

Lynus Vaz

2017-03-01 13:48:06 +0530

[diff] [blame]

647

#define A6XX_PC_PERFCTR_PC_SEL_0 0x9E34

648

#define A6XX_PC_PERFCTR_PC_SEL_1 0x9E35

649

#define A6XX_PC_PERFCTR_PC_SEL_2 0x9E36

650

#define A6XX_PC_PERFCTR_PC_SEL_3 0x9E37

651

#define A6XX_PC_PERFCTR_PC_SEL_4 0x9E38

652

#define A6XX_PC_PERFCTR_PC_SEL_5 0x9E39

653

#define A6XX_PC_PERFCTR_PC_SEL_6 0x9E3A

654

#define A6XX_PC_PERFCTR_PC_SEL_7 0x9E3B

Shrenuj Bansal

2016-06-01 11:11:27 -0700

[diff] [blame]

655

656

/* HLSQ registers */

657

#define A6XX_HLSQ_ADDR_MODE_CNTL 0xBE05

Lynus Vaz

2017-03-01 13:48:06 +0530

[diff] [blame]

658

#define A6XX_HLSQ_PERFCTR_HLSQ_SEL_0 0xBE10

659

#define A6XX_HLSQ_PERFCTR_HLSQ_SEL_1 0xBE11

660

#define A6XX_HLSQ_PERFCTR_HLSQ_SEL_2 0xBE12

661

#define A6XX_HLSQ_PERFCTR_HLSQ_SEL_3 0xBE13

662

#define A6XX_HLSQ_PERFCTR_HLSQ_SEL_4 0xBE14

663

#define A6XX_HLSQ_PERFCTR_HLSQ_SEL_5 0xBE15

Lynus Vaz

461e238

2017-01-16 19:35:41 +0530

[diff] [blame]

664

#define A6XX_HLSQ_DBG_AHB_READ_APERTURE 0xC800

665

#define A6XX_HLSQ_DBG_READ_SEL 0xD000

Shrenuj Bansal

2016-06-01 11:11:27 -0700

[diff] [blame]

666

667

/* VFD registers */

668

#define A6XX_VFD_ADDR_MODE_CNTL 0xA601

Lynus Vaz

2017-03-01 13:48:06 +0530

[diff] [blame]

669

#define A6XX_VFD_PERFCTR_VFD_SEL_0 0xA610

670

#define A6XX_VFD_PERFCTR_VFD_SEL_1 0xA611

671

#define A6XX_VFD_PERFCTR_VFD_SEL_2 0xA612

672

#define A6XX_VFD_PERFCTR_VFD_SEL_3 0xA613

673

#define A6XX_VFD_PERFCTR_VFD_SEL_4 0xA614

674

#define A6XX_VFD_PERFCTR_VFD_SEL_5 0xA615

675

#define A6XX_VFD_PERFCTR_VFD_SEL_6 0xA616

676

#define A6XX_VFD_PERFCTR_VFD_SEL_7 0xA617

Shrenuj Bansal

2016-06-01 11:11:27 -0700

[diff] [blame]

677

678

/* VPC registers */

679

#define A6XX_VPC_ADDR_MODE_CNTL 0x9601

Lynus Vaz

2017-03-01 13:48:06 +0530

[diff] [blame]

680

#define A6XX_VPC_PERFCTR_VPC_SEL_0 0x9604

681

#define A6XX_VPC_PERFCTR_VPC_SEL_1 0x9605

682

#define A6XX_VPC_PERFCTR_VPC_SEL_2 0x9606

683

#define A6XX_VPC_PERFCTR_VPC_SEL_3 0x9607

684

#define A6XX_VPC_PERFCTR_VPC_SEL_4 0x9608

685

#define A6XX_VPC_PERFCTR_VPC_SEL_5 0x9609

Shrenuj Bansal

2016-06-01 11:11:27 -0700

[diff] [blame]

686

687

/* UCHE registers */

688

#define A6XX_UCHE_ADDR_MODE_CNTL 0xE00

689

#define A6XX_UCHE_MODE_CNTL 0xE01

690

#define A6XX_UCHE_WRITE_RANGE_MAX_LO 0xE05

691

#define A6XX_UCHE_WRITE_RANGE_MAX_HI 0xE06

692

#define A6XX_UCHE_WRITE_THRU_BASE_LO 0xE07

693

#define A6XX_UCHE_WRITE_THRU_BASE_HI 0xE08

694

#define A6XX_UCHE_TRAP_BASE_LO 0xE09

695

#define A6XX_UCHE_TRAP_BASE_HI 0xE0A

696

#define A6XX_UCHE_GMEM_RANGE_MIN_LO 0xE0B

697

#define A6XX_UCHE_GMEM_RANGE_MIN_HI 0xE0C

698

#define A6XX_UCHE_GMEM_RANGE_MAX_LO 0xE0D

699

#define A6XX_UCHE_GMEM_RANGE_MAX_HI 0xE0E

700

#define A6XX_UCHE_CACHE_WAYS 0xE17

701

#define A6XX_UCHE_FILTER_CNTL 0xE18

Lynus Vaz

1fde74d

2017-03-20 18:02:47 +0530

[diff] [blame]

702

#define A6XX_UCHE_CLIENT_PF 0xE19

703

#define A6XX_UCHE_CLIENT_PF_CLIENT_ID_MASK 0x7

Lynus Vaz

2017-03-01 13:48:06 +0530

[diff] [blame]

704

#define A6XX_UCHE_PERFCTR_UCHE_SEL_0 0xE1C

705

#define A6XX_UCHE_PERFCTR_UCHE_SEL_1 0xE1D

706

#define A6XX_UCHE_PERFCTR_UCHE_SEL_2 0xE1E

707

#define A6XX_UCHE_PERFCTR_UCHE_SEL_3 0xE1F

708

#define A6XX_UCHE_PERFCTR_UCHE_SEL_4 0xE20

709

#define A6XX_UCHE_PERFCTR_UCHE_SEL_5 0xE21

710

#define A6XX_UCHE_PERFCTR_UCHE_SEL_6 0xE22

711

#define A6XX_UCHE_PERFCTR_UCHE_SEL_7 0xE23

712

#define A6XX_UCHE_PERFCTR_UCHE_SEL_8 0xE24

713

#define A6XX_UCHE_PERFCTR_UCHE_SEL_9 0xE25

714

#define A6XX_UCHE_PERFCTR_UCHE_SEL_10 0xE26

715

#define A6XX_UCHE_PERFCTR_UCHE_SEL_11 0xE27

Rajesh Kemisetti

1d4a697

2017-11-16 17:56:52 +0530

[diff] [blame]

716

#define A6XX_UCHE_GBIF_GX_CONFIG 0xE3A

Shrenuj Bansal

2016-06-01 11:11:27 -0700

[diff] [blame]

717

718

/* SP registers */

719

#define A6XX_SP_ADDR_MODE_CNTL 0xAE01

720

#define A6XX_SP_NC_MODE_CNTL 0xAE02

Lynus Vaz

2017-03-01 13:48:06 +0530

[diff] [blame]

721

#define A6XX_SP_PERFCTR_SP_SEL_0 0xAE10

722

#define A6XX_SP_PERFCTR_SP_SEL_1 0xAE11

723

#define A6XX_SP_PERFCTR_SP_SEL_2 0xAE12

724

#define A6XX_SP_PERFCTR_SP_SEL_3 0xAE13

725

#define A6XX_SP_PERFCTR_SP_SEL_4 0xAE14

726

#define A6XX_SP_PERFCTR_SP_SEL_5 0xAE15

727

#define A6XX_SP_PERFCTR_SP_SEL_6 0xAE16

728

#define A6XX_SP_PERFCTR_SP_SEL_7 0xAE17

729

#define A6XX_SP_PERFCTR_SP_SEL_8 0xAE18

730

#define A6XX_SP_PERFCTR_SP_SEL_9 0xAE19

731

#define A6XX_SP_PERFCTR_SP_SEL_10 0xAE1A

732

#define A6XX_SP_PERFCTR_SP_SEL_11 0xAE1B

733

#define A6XX_SP_PERFCTR_SP_SEL_12 0xAE1C

734

#define A6XX_SP_PERFCTR_SP_SEL_13 0xAE1D

735

#define A6XX_SP_PERFCTR_SP_SEL_14 0xAE1E

736

#define A6XX_SP_PERFCTR_SP_SEL_15 0xAE1F

737

#define A6XX_SP_PERFCTR_SP_SEL_16 0xAE20

738

#define A6XX_SP_PERFCTR_SP_SEL_17 0xAE21

739

#define A6XX_SP_PERFCTR_SP_SEL_18 0xAE22

740

#define A6XX_SP_PERFCTR_SP_SEL_19 0xAE23

741

#define A6XX_SP_PERFCTR_SP_SEL_20 0xAE24

742

#define A6XX_SP_PERFCTR_SP_SEL_21 0xAE25

743

#define A6XX_SP_PERFCTR_SP_SEL_22 0xAE26

744

#define A6XX_SP_PERFCTR_SP_SEL_23 0xAE27

Shrenuj Bansal

2016-06-01 11:11:27 -0700

[diff] [blame]

745

746

/* TP registers */

747

#define A6XX_TPL1_ADDR_MODE_CNTL 0xB601

748

#define A6XX_TPL1_NC_MODE_CNTL 0xB604

Lynus Vaz

2017-03-01 13:48:06 +0530

[diff] [blame]

749

#define A6XX_TPL1_PERFCTR_TP_SEL_0 0xB610

750

#define A6XX_TPL1_PERFCTR_TP_SEL_1 0xB611

751

#define A6XX_TPL1_PERFCTR_TP_SEL_2 0xB612

752

#define A6XX_TPL1_PERFCTR_TP_SEL_3 0xB613

753

#define A6XX_TPL1_PERFCTR_TP_SEL_4 0xB614

754

#define A6XX_TPL1_PERFCTR_TP_SEL_5 0xB615

755

#define A6XX_TPL1_PERFCTR_TP_SEL_6 0xB616

756

#define A6XX_TPL1_PERFCTR_TP_SEL_7 0xB617

757

#define A6XX_TPL1_PERFCTR_TP_SEL_8 0xB618

758

#define A6XX_TPL1_PERFCTR_TP_SEL_9 0xB619

759

#define A6XX_TPL1_PERFCTR_TP_SEL_10 0xB61A

760

#define A6XX_TPL1_PERFCTR_TP_SEL_11 0xB61B

Shrenuj Bansal

2016-06-01 11:11:27 -0700

[diff] [blame]

761

762

/* VBIF registers */

763

#define A6XX_VBIF_VERSION 0x3000

Lynus Vaz

daac54073

2017-07-27 14:23:35 +0530

[diff] [blame]

764

#define A6XX_VBIF_CLKON 0x3001

765

#define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS_MASK 0x1

766

#define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS_SHIFT 0x1

Shrenuj Bansal

2016-06-01 11:11:27 -0700

[diff] [blame]

767

#define A6XX_VBIF_GATE_OFF_WRREQ_EN 0x302A

768

#define A6XX_VBIF_XIN_HALT_CTRL0 0x3080

Carter Cooper

afc8591

2017-03-20 09:39:18 -0600

[diff] [blame]

769

#define A6XX_VBIF_XIN_HALT_CTRL0_MASK 0xF

Shrenuj Bansal

2016-06-01 11:11:27 -0700

[diff] [blame]

770

#define A6XX_VBIF_XIN_HALT_CTRL1 0x3081

Lynus Vaz

daac54073

2017-07-27 14:23:35 +0530

[diff] [blame]

771

#define A6XX_VBIF_TEST_BUS_OUT_CTRL 0x3084

772

#define A6XX_VBIF_TEST_BUS_OUT_CTRL_EN_MASK 0x1

773

#define A6XX_VBIF_TEST_BUS_OUT_CTRL_EN_SHIFT 0x0

774

#define A6XX_VBIF_TEST_BUS1_CTRL0 0x3085

775

#define A6XX_VBIF_TEST_BUS1_CTRL1 0x3086

776

#define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL_MASK 0xF

777

#define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL_SHIFT 0x0

778

#define A6XX_VBIF_TEST_BUS2_CTRL0 0x3087

779

#define A6XX_VBIF_TEST_BUS2_CTRL1 0x3088

780

#define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL_MASK 0x1FF

781

#define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL_SHIFT 0x0

782

#define A6XX_VBIF_TEST_BUS_OUT 0x308C

Lynus Vaz

2017-03-01 13:48:06 +0530

[diff] [blame]

783

#define A6XX_VBIF_PERF_CNT_SEL0 0x30d0

784

#define A6XX_VBIF_PERF_CNT_SEL1 0x30d1

785

#define A6XX_VBIF_PERF_CNT_SEL2 0x30d2

786

#define A6XX_VBIF_PERF_CNT_SEL3 0x30d3

787

#define A6XX_VBIF_PERF_CNT_LOW0 0x30d8

788

#define A6XX_VBIF_PERF_CNT_LOW1 0x30d9

789

#define A6XX_VBIF_PERF_CNT_LOW2 0x30da

790

#define A6XX_VBIF_PERF_CNT_LOW3 0x30db

791

#define A6XX_VBIF_PERF_CNT_HIGH0 0x30e0

792

#define A6XX_VBIF_PERF_CNT_HIGH1 0x30e1

793

#define A6XX_VBIF_PERF_CNT_HIGH2 0x30e2

794

#define A6XX_VBIF_PERF_CNT_HIGH3 0x30e3

795

#define A6XX_VBIF_PERF_PWR_CNT_EN0 0x3100

796

#define A6XX_VBIF_PERF_PWR_CNT_EN1 0x3101

797

#define A6XX_VBIF_PERF_PWR_CNT_EN2 0x3102

798

#define A6XX_VBIF_PERF_PWR_CNT_LOW0 0x3110

799

#define A6XX_VBIF_PERF_PWR_CNT_LOW1 0x3111

800

#define A6XX_VBIF_PERF_PWR_CNT_LOW2 0x3112

801

#define A6XX_VBIF_PERF_PWR_CNT_HIGH0 0x3118

802

#define A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x3119

803

#define A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x311a

Shrenuj Bansal

2016-06-01 11:11:27 -0700

[diff] [blame]

804

Deepak Kumar

84b9e03

2017-11-08 13:08:50 +0530

[diff] [blame]

805

/* GBIF countables */

806

#define GBIF_AXI0_READ_DATA_TOTAL_BEATS 34

807

#define GBIF_AXI1_READ_DATA_TOTAL_BEATS 35

808

#define GBIF_AXI0_WRITE_DATA_TOTAL_BEATS 46

809

#define GBIF_AXI1_WRITE_DATA_TOTAL_BEATS 47

810

Rajesh Kemisetti

77b82ed

2017-09-24 20:42:41 +0530

[diff] [blame]

811

/* GBIF registers */

812

#define A6XX_GBIF_HALT 0x3c45

813

#define A6XX_GBIF_HALT_ACK 0x3c46

Rajesh Kemisetti

d1ca954

2017-10-18 15:35:41 +0530

[diff] [blame]

814

#define A6XX_GBIF_HALT_MASK 0x2

Rajesh Kemisetti

77b82ed

2017-09-24 20:42:41 +0530

[diff] [blame]

815

816

#define A6XX_GBIF_PERF_PWR_CNT_EN 0x3cc0

817

#define A6XX_GBIF_PERF_CNT_SEL 0x3cc2

818

#define A6XX_GBIF_PERF_CNT_LOW0 0x3cc4

819

#define A6XX_GBIF_PERF_CNT_LOW1 0x3cc5

820

#define A6XX_GBIF_PERF_CNT_LOW2 0x3cc6

821

#define A6XX_GBIF_PERF_CNT_LOW3 0x3cc7

822

#define A6XX_GBIF_PERF_CNT_HIGH0 0x3cc8

823

#define A6XX_GBIF_PERF_CNT_HIGH1 0x3cc9

824

#define A6XX_GBIF_PERF_CNT_HIGH2 0x3cca

825

#define A6XX_GBIF_PERF_CNT_HIGH3 0x3ccb

826

#define A6XX_GBIF_PWR_CNT_LOW0 0x3ccc

827

#define A6XX_GBIF_PWR_CNT_LOW1 0x3ccd

828

#define A6XX_GBIF_PWR_CNT_LOW2 0x3cce

829

#define A6XX_GBIF_PWR_CNT_HIGH0 0x3ccf

830

#define A6XX_GBIF_PWR_CNT_HIGH1 0x3cd0

831

#define A6XX_GBIF_PWR_CNT_HIGH2 0x3cd1

832

833

Lynus Vaz

2017-03-07 19:27:46 +0530

[diff] [blame]

834

/* CX_DBGC_CFG registers */

835

#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x18400

836

#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x18401

837

#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x18402

838

#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x18403

Lokesh Batra

2017-05-25 11:17:40 -0700

[diff] [blame]

839

#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_PING_INDEX_SHIFT 0x0

840

#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_PING_BLK_SEL_SHIFT 0x8

Lynus Vaz

2017-03-07 19:27:46 +0530

[diff] [blame]

841

#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x18404

842

#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN_SHIFT 0x0

843

#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU_SHIFT 0xC

844

#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT_SHIFT 0x1C

845

#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x18405

846

#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE_SHIFT 0x18

Lokesh Batra

2017-05-25 11:17:40 -0700

[diff] [blame]

847

#define A6XX_CX_DBGC_CFG_DBGBUS_OPL 0x18406

848

#define A6XX_CX_DBGC_CFG_DBGBUS_OPE 0x18407

Lynus Vaz

2017-03-07 19:27:46 +0530

[diff] [blame]

849

#define A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x18408

850

#define A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x18409

851

#define A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x1840A

852

#define A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x1840B

853

#define A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x1840C

854

#define A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x1840D

855

#define A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x1840E

856

#define A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x1840F

857

#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x18410

858

#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x18411

859

#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL0_SHIFT 0x0

860

#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL1_SHIFT 0x4

861

#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL2_SHIFT 0x8

862

#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL3_SHIFT 0xC

863

#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL4_SHIFT 0x10

864

#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL5_SHIFT 0x14

865

#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL6_SHIFT 0x18

866

#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL7_SHIFT 0x1C

867

#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL8_SHIFT 0x0

868

#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL9_SHIFT 0x4

869

#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL10_SHIFT 0x8

870

#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL11_SHIFT 0xC

871

#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL12_SHIFT 0x10

872

#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL13_SHIFT 0x14

873

#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL14_SHIFT 0x18

874

#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL15_SHIFT 0x1C

Lokesh Batra

2017-05-25 11:17:40 -0700

[diff] [blame]

875

#define A6XX_CX_DBGC_CFG_DBGBUS_IVTE_0 0x18412

876

#define A6XX_CX_DBGC_CFG_DBGBUS_IVTE_1 0x18413

877

#define A6XX_CX_DBGC_CFG_DBGBUS_IVTE_2 0x18414

878

#define A6XX_CX_DBGC_CFG_DBGBUS_IVTE_3 0x18415

879

#define A6XX_CX_DBGC_CFG_DBGBUS_MASKE_0 0x18416

880

#define A6XX_CX_DBGC_CFG_DBGBUS_MASKE_1 0x18417

881

#define A6XX_CX_DBGC_CFG_DBGBUS_MASKE_2 0x18418

882

#define A6XX_CX_DBGC_CFG_DBGBUS_MASKE_3 0x18419

883

#define A6XX_CX_DBGC_CFG_DBGBUS_NIBBLEE 0x1841A

884

#define A6XX_CX_DBGC_CFG_DBGBUS_PTRC0 0x1841B

885

#define A6XX_CX_DBGC_CFG_DBGBUS_PTRC1 0x1841C

886

#define A6XX_CX_DBGC_CFG_DBGBUS_LOADREG 0x1841D

887

#define A6XX_CX_DBGC_CFG_DBGBUS_IDX 0x1841E

888

#define A6XX_CX_DBGC_CFG_DBGBUS_CLRC 0x1841F

889

#define A6XX_CX_DBGC_CFG_DBGBUS_LOADIVT 0x18420

890

#define A6XX_CX_DBGC_VBIF_DBG_CNTL 0x18421

891

#define A6XX_CX_DBGC_DBG_LO_HI_GPIO 0x18422

892

#define A6XX_CX_DBGC_EXT_TRACE_BUS_CNTL 0x18423

893

#define A6XX_CX_DBGC_READ_AHB_THROUGH_DBG 0x18424

Lynus Vaz

2017-03-07 19:27:46 +0530

[diff] [blame]

894

#define A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x1842F

895

#define A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x18430

Lokesh Batra

2017-05-25 11:17:40 -0700

[diff] [blame]

896

#define A6XX_CX_DBGC_EVT_CFG 0x18440

897

#define A6XX_CX_DBGC_EVT_INTF_SEL_0 0x18441

898

#define A6XX_CX_DBGC_EVT_INTF_SEL_1 0x18442

899

#define A6XX_CX_DBGC_PERF_ATB_CFG 0x18443

900

#define A6XX_CX_DBGC_PERF_ATB_COUNTER_SEL_0 0x18444

901

#define A6XX_CX_DBGC_PERF_ATB_COUNTER_SEL_1 0x18445

902

#define A6XX_CX_DBGC_PERF_ATB_COUNTER_SEL_2 0x18446

903

#define A6XX_CX_DBGC_PERF_ATB_COUNTER_SEL_3 0x18447

904

#define A6XX_CX_DBGC_PERF_ATB_TRIG_INTF_SEL_0 0x18448

905

#define A6XX_CX_DBGC_PERF_ATB_TRIG_INTF_SEL_1 0x18449

906

#define A6XX_CX_DBGC_PERF_ATB_DRAIN_CMD 0x1844A

907

#define A6XX_CX_DBGC_ECO_CNTL 0x18450

908

#define A6XX_CX_DBGC_AHB_DBG_CNTL 0x18451

Lynus Vaz

2017-03-07 19:27:46 +0530

[diff] [blame]

909

Kyle Piefer

2017-02-10 13:58:58 -0800

[diff] [blame]

910

/* GMU control registers */

Oleg Perelet

2017-03-16 15:38:43 -0700

[diff] [blame]

911

#define A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL 0x1A880

Kyle Piefer

2017-02-10 13:58:58 -0800

[diff] [blame]

912

#define A6XX_GMU_GX_SPTPRAC_POWER_CONTROL 0x1A881

913

#define A6XX_GMU_CM3_ITCM_START 0x1B400

914

#define A6XX_GMU_CM3_DTCM_START 0x1C400

Shrenuj Bansal

d0fe746

2017-05-08 16:11:19 -0700

[diff] [blame]

915

#define A6XX_GMU_NMI_CONTROL_STATUS 0x1CBF0

Kyle Piefer

2017-02-10 13:58:58 -0800

[diff] [blame]

916

#define A6XX_GMU_BOOT_SLUMBER_OPTION 0x1CBF8

917

#define A6XX_GMU_GX_VOTE_IDX 0x1CBF9

918

#define A6XX_GMU_MX_VOTE_IDX 0x1CBFA

919

#define A6XX_GMU_DCVS_ACK_OPTION 0x1CBFC

920

#define A6XX_GMU_DCVS_PERF_SETTING 0x1CBFD

921

#define A6XX_GMU_DCVS_BW_SETTING 0x1CBFE

922

#define A6XX_GMU_DCVS_RETURN 0x1CBFF

George Shen

1f312ab

2017-08-01 10:53:50 -0700

[diff] [blame]

923

#define A6XX_GMU_SYS_BUS_CONFIG 0x1F40F

Kyle Piefer

2017-02-10 13:58:58 -0800

[diff] [blame]

924

#define A6XX_GMU_CM3_SYSRESET 0x1F800

925

#define A6XX_GMU_CM3_BOOT_CONFIG 0x1F801

Oleg Perelet

5d2d28f

2018-03-06 17:03:20 -0800

[diff] [blame]

926

#define A6XX_GMU_CX_GMU_WFI_CONFIG 0x1F802

Kyle Piefer

5c9478c

2017-04-20 15:12:05 -0700

[diff] [blame]

927

#define A6XX_GMU_CM3_FW_BUSY 0x1F81A

Kyle Piefer

2017-02-10 13:58:58 -0800

[diff] [blame]

928

#define A6XX_GMU_CM3_FW_INIT_RESULT 0x1F81C

Shrenuj Bansal

d0fe746

2017-05-08 16:11:19 -0700

[diff] [blame]

929

#define A6XX_GMU_CM3_CFG 0x1F82D

Lynus Vaz

856ca60

2017-05-24 16:56:36 +0530

[diff] [blame]

930

#define A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE 0x1F840

931

#define A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0 0x1F841

Lynus Vaz

4fc97e2

2017-06-01 20:03:35 +0530

[diff] [blame]

932

#define A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1 0x1F842

Lynus Vaz

856ca60

2017-05-24 16:56:36 +0530

[diff] [blame]

933

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L 0x1F844

934

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H 0x1F845

Lynus Vaz

4fc97e2

2017-06-01 20:03:35 +0530

[diff] [blame]

935

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L 0x1F846

936

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H 0x1F847

937

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L 0x1F848

938

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H 0x1F849

939

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L 0x1F84A

940

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H 0x1F84B

941

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L 0x1F84C

942

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H 0x1F84D

943

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L 0x1F84E

944

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H 0x1F84F

Oleg Perelet

39fead2

2018-01-08 14:46:17 -0800

[diff] [blame]

945

#define A6XX_GMU_CX_GMU_ALWAYS_ON_COUNTER_L 0x1F888

946

#define A6XX_GMU_CX_GMU_ALWAYS_ON_COUNTER_H 0x1F889

Kyle Piefer

2017-02-10 13:58:58 -0800

[diff] [blame]

947

#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL 0x1F8C0

948

#define A6XX_GMU_PWR_COL_INTER_FRAME_HYST 0x1F8C1

949

#define A6XX_GMU_PWR_COL_SPTPRAC_HYST 0x1F8C2

950

#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS 0x1F8D0

951

#define A6XX_GMU_GPU_NAP_CTRL 0x1F8E4

952

#define A6XX_GMU_RPMH_CTRL 0x1F8E8

953

#define A6XX_GMU_RPMH_HYST_CTRL 0x1F8E9

George Shen

f2d4e05

2017-05-11 16:28:23 -0700

[diff] [blame]

954

#define A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE 0x1F8EC

Kyle Piefer

3a5ac09

2017-04-06 16:05:30 -0700

[diff] [blame]

955

#define A6XX_GMU_BOOT_KMD_LM_HANDSHAKE 0x1F9F0

Kyle Piefer

2017-03-28 17:31:48 -0700

[diff] [blame]

956

#define A6XX_GMU_LLM_GLM_SLEEP_CTRL 0x1F957

957

#define A6XX_GMU_LLM_GLM_SLEEP_STATUS 0x1F958

Kyle Piefer

2017-02-10 13:58:58 -0800

[diff] [blame]

958

959

/* HFI registers*/

960

#define A6XX_GMU_ALWAYS_ON_COUNTER_L 0x1F888

961

#define A6XX_GMU_ALWAYS_ON_COUNTER_H 0x1F889

962

#define A6XX_GMU_GMU_PWR_COL_KEEPALIVE 0x1F8C3

963

#define A6XX_GMU_HFI_CTRL_STATUS 0x1F980

964

#define A6XX_GMU_HFI_VERSION_INFO 0x1F981

965

#define A6XX_GMU_HFI_SFR_ADDR 0x1F982

966

#define A6XX_GMU_HFI_MMAP_ADDR 0x1F983

967

#define A6XX_GMU_HFI_QTBL_INFO 0x1F984

968

#define A6XX_GMU_HFI_QTBL_ADDR 0x1F985

969

#define A6XX_GMU_HFI_CTRL_INIT 0x1F986

970

#define A6XX_GMU_GMU2HOST_INTR_SET 0x1F990

971

#define A6XX_GMU_GMU2HOST_INTR_CLR 0x1F991

972

#define A6XX_GMU_GMU2HOST_INTR_INFO 0x1F992

973

#define A6XX_GMU_GMU2HOST_INTR_MASK 0x1F993

974

#define A6XX_GMU_HOST2GMU_INTR_SET 0x1F994

975

#define A6XX_GMU_HOST2GMU_INTR_CLR 0x1F995

976

#define A6XX_GMU_HOST2GMU_INTR_RAW_INFO 0x1F996

977

#define A6XX_GMU_HOST2GMU_INTR_EN_0 0x1F997

978

#define A6XX_GMU_HOST2GMU_INTR_EN_1 0x1F998

979

#define A6XX_GMU_HOST2GMU_INTR_EN_2 0x1F999

980

#define A6XX_GMU_HOST2GMU_INTR_EN_3 0x1F99A

981

#define A6XX_GMU_HOST2GMU_INTR_INFO_0 0x1F99B

982

#define A6XX_GMU_HOST2GMU_INTR_INFO_1 0x1F99C

983

#define A6XX_GMU_HOST2GMU_INTR_INFO_2 0x1F99D

984

#define A6XX_GMU_HOST2GMU_INTR_INFO_3 0x1F99E

Oleg Perelet

c2ab7f7

2017-06-22 16:45:57 -0700

[diff] [blame]

985

#define A6XX_GMU_GENERAL_1 0x1F9C6

Kyle Piefer

2017-02-10 13:58:58 -0800

[diff] [blame]

986

#define A6XX_GMU_GENERAL_7 0x1F9CC

987

Kyle Piefer

2017-03-28 17:31:48 -0700

[diff] [blame]

988

/* ISENSE registers */

989

#define A6XX_GMU_ISENSE_CTRL 0x1F95D

Oleg Perelet

c2ab7f7

2017-06-22 16:45:57 -0700

[diff] [blame]

990

#define A6XX_GPU_GMU_CX_GMU_ISENSE_CTRL 0x1f95d

Harshdeep Dhatt

167ef88

2017-09-13 14:49:45 -0600

[diff] [blame]

991

#define A6XX_GPU_CS_ENABLE_REG 0x23120

Oleg Perelet

c2ab7f7

2017-06-22 16:45:57 -0700

[diff] [blame]

992

993

/* LM registers */

994

#define A6XX_GPU_GMU_CX_GMU_PWR_THRESHOLD 0x1F94D

995

Kyle Piefer

2017-03-28 17:31:48 -0700

[diff] [blame]

996

Kyle Piefer

2017-02-10 13:58:58 -0800

[diff] [blame]

997

#define A6XX_GMU_AO_INTERRUPT_EN 0x23B03

Kyle Piefer

e7b06b4

2017-04-06 13:53:01 -0700

[diff] [blame]

998

#define A6XX_GMU_AO_HOST_INTERRUPT_CLR 0x23B04

999

#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS 0x23B05

1000

#define A6XX_GMU_AO_HOST_INTERRUPT_MASK 0x23B06

Oleg Perelet

2017-03-16 15:38:43 -0700

[diff] [blame]

1001

#define A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL 0x23B09

1002

#define A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL 0x23B0A

1003

#define A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL 0x23B0B

Oleg Perelet

62d5cec

2017-03-27 16:14:52 -0700

[diff] [blame]

1004

#define A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS 0x23B0C

Kyle Piefer

247e35c

2017-06-08 11:13:11 -0700

[diff] [blame]

1005

#define A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2 0x23B0D

Lynus Vaz

856ca60

2017-05-24 16:56:36 +0530

[diff] [blame]

1006

#define A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK 0x23B0E

Shrenuj Bansal

d197bf6

2017-04-07 11:00:09 -0700

[diff] [blame]

1007

#define A6XX_GMU_AO_AHB_FENCE_CTRL 0x23B10

Kyle Piefer

2017-02-10 13:58:58 -0800

[diff] [blame]

1008

#define A6XX_GMU_AHB_FENCE_STATUS 0x23B13

1009

#define A6XX_GMU_RBBM_INT_UNMASKED_STATUS 0x23B15

1010

#define A6XX_GMU_AO_SPARE_CNTL 0x23B16

1011

1012

/* GMU RSC control registers */

Kyle Piefer

3e1f6bc

2017-08-10 11:16:19 -0700

[diff] [blame]

1013

#define A6XX_GPU_RSCC_RSC_STATUS0_DRV0 0x23404

Kyle Piefer

2017-02-10 13:58:58 -0800

[diff] [blame]

1014

#define A6XX_GMU_RSCC_CONTROL_REQ 0x23B07

1015

#define A6XX_GMU_RSCC_CONTROL_ACK 0x23B08

1016

1017

/* FENCE control registers */

1018

#define A6XX_GMU_AHB_FENCE_RANGE_0 0x23B11

1019

#define A6XX_GMU_AHB_FENCE_RANGE_1 0x23B12

1020

Kyle Piefer

fa50d3e

2017-05-24 12:35:24 -0700

[diff] [blame]

1021

/* GPUCC registers */

1022

#define A6XX_GPU_CC_GX_GDSCR 0x24403

George Shen

6927d8f

2017-07-19 11:38:10 -0700

[diff] [blame]

1023

#define A6XX_GPU_CC_GX_DOMAIN_MISC 0x24542

Kyle Piefer

fa50d3e

2017-05-24 12:35:24 -0700

[diff] [blame]

1024

Kyle Piefer

2017-02-10 13:58:58 -0800

[diff] [blame]

1025

/* GPU RSC sequencer registers */

1026

#define A6XX_RSCC_PDC_SEQ_START_ADDR 0x23408

1027

#define A6XX_RSCC_PDC_MATCH_VALUE_LO 0x23409

1028

#define A6XX_RSCC_PDC_MATCH_VALUE_HI 0x2340A

1029

#define A6XX_RSCC_PDC_SLAVE_ID_DRV0 0x2340B

1030

#define A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR 0x2340D

1031

#define A6XX_RSCC_HIDDEN_TCS_CMD0_DATA 0x2340E

1032

#define A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0 0x23482

1033

#define A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0 0x23483

1034

#define A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0 0x23489

1035

#define A6XX_RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0 0x2348C

1036

#define A6XX_RSCC_OVERRIDE_START_ADDR 0x23500

1037

#define A6XX_RSCC_SEQ_BUSY_DRV0 0x23501

1038

#define A6XX_RSCC_SEQ_MEM_0_DRV0 0x23580

Kyle Piefer

2017-03-28 17:31:48 -0700

[diff] [blame]

1039

#define A6XX_RSCC_TCS0_DRV0_STATUS 0x23746

1040

#define A6XX_RSCC_TCS1_DRV0_STATUS 0x238AE

1041

#define A6XX_RSCC_TCS2_DRV0_STATUS 0x23A16

1042

#define A6XX_RSCC_TCS3_DRV0_STATUS 0x23B7E

Kyle Piefer

2017-02-10 13:58:58 -0800

[diff] [blame]

1043

1044

/* GPU PDC sequencer registers in AOSS.RPMh domain */

1045

#define PDC_GPU_ENABLE_PDC 0x21140

1046

#define PDC_GPU_SEQ_START_ADDR 0x21148

1047

#define PDC_GPU_TCS0_CONTROL 0x21540

1048

#define PDC_GPU_TCS0_CMD_ENABLE_BANK 0x21541

1049

#define PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x21542

1050

#define PDC_GPU_TCS0_CMD0_MSGID 0x21543

1051

#define PDC_GPU_TCS0_CMD0_ADDR 0x21544

1052

#define PDC_GPU_TCS0_CMD0_DATA 0x21545

1053

#define PDC_GPU_TCS1_CONTROL 0x21572

1054

#define PDC_GPU_TCS1_CMD_ENABLE_BANK 0x21573

1055

#define PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x21574

1056

#define PDC_GPU_TCS1_CMD0_MSGID 0x21575

1057

#define PDC_GPU_TCS1_CMD0_ADDR 0x21576

1058

#define PDC_GPU_TCS1_CMD0_DATA 0x21577

Kyle Piefer

8714918

2017-10-05 15:01:33 -0700

[diff] [blame]

1059

#define PDC_GPU_TCS2_CONTROL 0x215A4

1060

#define PDC_GPU_TCS2_CMD_ENABLE_BANK 0x215A5

1061

#define PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x215A6

1062

#define PDC_GPU_TCS2_CMD0_MSGID 0x215A7

1063

#define PDC_GPU_TCS2_CMD0_ADDR 0x215A8

1064

#define PDC_GPU_TCS2_CMD0_DATA 0x215A9

1065

#define PDC_GPU_TCS3_CONTROL 0x215D6

1066

#define PDC_GPU_TCS3_CMD_ENABLE_BANK 0x215D7

1067

#define PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x215D8

1068

#define PDC_GPU_TCS3_CMD0_MSGID 0x215D9

1069

#define PDC_GPU_TCS3_CMD0_ADDR 0x215DA

1070

#define PDC_GPU_TCS3_CMD0_DATA 0x215DB

Kyle Piefer

2017-02-10 13:58:58 -0800

[diff] [blame]

1071

#define PDC_GPU_SEQ_MEM_0 0xA0000

Shrenuj Bansal

2016-06-01 11:11:27 -0700

[diff] [blame]

1072

Lynus Vaz

0925b4a

2018-10-03 12:55:21 +0530

[diff] [blame]

1073

/* GPU CX_MISC registers */

1074

#define A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_0 0x1

1075

#define A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1 0x2

1076

#define A6XX_LLC_NUM_GPU_SCIDS 5

1077

#define A6XX_GPU_LLC_SCID_NUM_BITS 5

1078

#define A6XX_GPU_LLC_SCID_MASK \

1079

((1 << (A6XX_LLC_NUM_GPU_SCIDS * A6XX_GPU_LLC_SCID_NUM_BITS)) - 1)

1080

#define A6XX_GPUHTW_LLC_SCID_SHIFT 25

1081

#define A6XX_GPUHTW_LLC_SCID_MASK \

1082

(((1 << A6XX_GPU_LLC_SCID_NUM_BITS) - 1) << A6XX_GPUHTW_LLC_SCID_SHIFT)

1083

Shrenuj Bansal