| Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | #ifndef __A3XX_H |
| 14 | #define __A3XX_H |
| 15 | |
| 16 | #include "a3xx_reg.h" |
| 17 | |
| 18 | #define A3XX_IRQ_FLAGS \ |
| 19 | { BIT(A3XX_INT_RBBM_GPU_IDLE), "RBBM_GPU_IDLE" }, \ |
| 20 | { BIT(A3XX_INT_RBBM_AHB_ERROR), "RBBM_AHB_ERR" }, \ |
| 21 | { BIT(A3XX_INT_RBBM_REG_TIMEOUT), "RBBM_REG_TIMEOUT" }, \ |
| 22 | { BIT(A3XX_INT_RBBM_ME_MS_TIMEOUT), "RBBM_ME_MS_TIMEOUT" }, \ |
| 23 | { BIT(A3XX_INT_RBBM_PFP_MS_TIMEOUT), "RBBM_PFP_MS_TIMEOUT" }, \ |
| 24 | { BIT(A3XX_INT_RBBM_ATB_BUS_OVERFLOW), "RBBM_ATB_BUS_OVERFLOW" }, \ |
| 25 | { BIT(A3XX_INT_VFD_ERROR), "RBBM_VFD_ERROR" }, \ |
| 26 | { BIT(A3XX_INT_CP_SW_INT), "CP_SW" }, \ |
| 27 | { BIT(A3XX_INT_CP_T0_PACKET_IN_IB), "CP_T0_PACKET_IN_IB" }, \ |
| 28 | { BIT(A3XX_INT_CP_OPCODE_ERROR), "CP_OPCODE_ERROR" }, \ |
| 29 | { BIT(A3XX_INT_CP_RESERVED_BIT_ERROR), "CP_RESERVED_BIT_ERROR" }, \ |
| 30 | { BIT(A3XX_INT_CP_HW_FAULT), "CP_HW_FAULT" }, \ |
| 31 | { BIT(A3XX_INT_CP_DMA), "CP_DMA" }, \ |
| 32 | { BIT(A3XX_INT_CP_IB2_INT), "CP_IB2_INT" }, \ |
| 33 | { BIT(A3XX_INT_CP_IB1_INT), "CP_IB1_INT" }, \ |
| 34 | { BIT(A3XX_INT_CP_RB_INT), "CP_RB_INT" }, \ |
| 35 | { BIT(A3XX_INT_CP_REG_PROTECT_FAULT), "CP_REG_PROTECT_FAULT" }, \ |
| 36 | { BIT(A3XX_INT_CP_RB_DONE_TS), "CP_RB_DONE_TS" }, \ |
| 37 | { BIT(A3XX_INT_CP_VS_DONE_TS), "CP_VS_DONE_TS" }, \ |
| 38 | { BIT(A3XX_INT_CP_PS_DONE_TS), "CP_PS_DONE_TS" }, \ |
| 39 | { BIT(A3XX_INT_CACHE_FLUSH_TS), "CACHE_FLUSH_TS" }, \ |
| 40 | { BIT(A3XX_INT_CP_AHB_ERROR_HALT), "CP_AHB_ERROR_HALT" }, \ |
| 41 | { BIT(A3XX_INT_MISC_HANG_DETECT), "MISC_HANG_DETECT" }, \ |
| 42 | { BIT(A3XX_INT_UCHE_OOB_ACCESS), "UCHE_OOB_ACCESS" } |
| 43 | |
| 44 | unsigned int a3xx_irq_pending(struct adreno_device *adreno_dev); |
| 45 | |
| 46 | int a3xx_microcode_read(struct adreno_device *adreno_dev); |
| 47 | int a3xx_microcode_load(struct adreno_device *adreno_dev, |
| 48 | unsigned int start_type); |
| 49 | int a3xx_perfcounter_enable(struct adreno_device *adreno_dev, |
| 50 | unsigned int group, unsigned int counter, unsigned int countable); |
| 51 | uint64_t a3xx_perfcounter_read(struct adreno_device *adreno_dev, |
| 52 | unsigned int group, unsigned int counter); |
| 53 | |
| 54 | void a3xx_a4xx_err_callback(struct adreno_device *adreno_dev, int bit); |
| 55 | |
| 56 | void a3xx_snapshot(struct adreno_device *adreno_dev, |
| 57 | struct kgsl_snapshot *snapshot); |
| 58 | #endif /*__A3XX_H */ |