Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-5.4 / 0071f56e46dadb88dc3ad1f8d9cf9c3ae014735d / . / include / linux / qed / eth_common.h
blob: 320b3373ac1dd834d03102ba79405ede2bce8197 [file] [log] [blame]
Yuval Mintz25c089d2015-10-26 11:02:26 +0200[diff] [blame]1/* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
3 *
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
6 * this source tree.
7 */
8
9#ifndef __ETH_COMMON__
10#define __ETH_COMMON__
11
12/********************/
13/* ETH FW CONSTANTS */
14/********************/
15#define ETH_CACHE_LINE_SIZE 64
16
17#define ETH_MAX_RAMROD_PER_CON 8
18#define ETH_TX_BD_PAGE_SIZE_BYTES 4096
19#define ETH_RX_BD_PAGE_SIZE_BYTES 4096
20#define ETH_RX_SGE_PAGE_SIZE_BYTES 4096
21#define ETH_RX_CQE_PAGE_SIZE_BYTES 4096
22#define ETH_RX_NUM_NEXT_PAGE_BDS 2
23#define ETH_RX_NUM_NEXT_PAGE_SGES 2
24
25#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1
26#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18
27#define ETH_TX_MAX_LSO_HDR_NBD 4
28#define ETH_TX_MIN_BDS_PER_LSO_PKT 3
29#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3
30#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2
31#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2
32#define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 12 + 8))
33#define ETH_TX_MAX_LSO_HDR_BYTES 510
34
35#define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
36
37#define ETH_REG_CQE_PBL_SIZE 3
38
39/* num of MAC/VLAN filters */
40#define ETH_NUM_MAC_FILTERS 512
41#define ETH_NUM_VLAN_FILTERS 512
42
43/* approx. multicast constants */
44#define ETH_MULTICAST_BIN_FROM_MAC_SEED 0
45#define ETH_MULTICAST_MAC_BINS 256
46#define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32)
47
48/* ethernet vport update constants */
49#define ETH_FILTER_RULES_COUNT 10
50#define ETH_RSS_IND_TABLE_ENTRIES_NUM 128
51#define ETH_RSS_KEY_SIZE_REGS 10
52#define ETH_RSS_ENGINE_NUM_K2 207
53#define ETH_RSS_ENGINE_NUM_BB 127
54
55/* TPA constants */
56#define ETH_TPA_MAX_AGGS_NUM 64
57#define ETH_TPA_CQE_START_SGL_SIZE 3
58#define ETH_TPA_CQE_CONT_SGL_SIZE 6
59#define ETH_TPA_CQE_END_SGL_SIZE 4
60
61/* Queue Zone sizes */
62#define TSTORM_QZONE_SIZE 0
63#define MSTORM_QZONE_SIZE sizeof(struct mstorm_eth_queue_zone)
64#define USTORM_QZONE_SIZE sizeof(struct ustorm_eth_queue_zone)
65#define XSTORM_QZONE_SIZE 0
66#define YSTORM_QZONE_SIZE sizeof(struct ystorm_eth_queue_zone)
67#define PSTORM_QZONE_SIZE 0
68
69/* Interrupt coalescing TimeSet */
70struct coalescing_timeset {
71 u8 timeset;
72 u8 valid;
73};
74
75struct eth_tx_1st_bd_flags {
76 u8 bitfields;
77#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1
78#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 0
79#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1
80#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 1
81#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1
82#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 2
83#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1
84#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 3
85#define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1
86#define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 4
87#define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1
88#define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 5
89#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1
90#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6
91#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1
92#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7
93};
94
95/* The parsing information data fo rthe first tx bd of a given packet. */
96struct eth_tx_data_1st_bd {
97 __le16 vlan;
98 u8 nbds;
99 struct eth_tx_1st_bd_flags bd_flags;
100 __le16 fw_use_only;
101};
102
103/* The parsing information data for the second tx bd of a given packet. */
104struct eth_tx_data_2nd_bd {
105 __le16 tunn_ip_size;
106 __le16 bitfields;
107#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF
108#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0
109#define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7
110#define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13
111 __le16 bitfields2;
112#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF
113#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
114#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3
115#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4
116#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK 0x3
117#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT 6
118#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3
119#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 8
120#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1
121#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 10
122#define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1
123#define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 11
124#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1
125#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 12
126#define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1
127#define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 13
128#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1
129#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 14
130#define ETH_TX_DATA_2ND_BD_RESERVED1_MASK 0x1
131#define ETH_TX_DATA_2ND_BD_RESERVED1_SHIFT 15
132};
133
134/* Regular ETH Rx FP CQE. */
135struct eth_fast_path_rx_reg_cqe {
136 u8 type;
137 u8 bitfields;
138#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7
139#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0
140#define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF
141#define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3
142#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1
143#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7
144 __le16 pkt_len;
145 struct parsing_and_err_flags pars_flags;
146 __le16 vlan_tag;
147 __le32 rss_hash;
148 __le16 len_on_bd;
149 u8 placement_offset;
150 u8 reserved;
151 __le16 pbl[ETH_REG_CQE_PBL_SIZE];
152 u8 reserved1[10];
153};
154
155/* The L4 pseudo checksum mode for Ethernet */
156enum eth_l4_pseudo_checksum_mode {
157 ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH,
158 ETH_L4_PSEUDO_CSUM_ZERO_LENGTH,
159 MAX_ETH_L4_PSEUDO_CHECKSUM_MODE
160};
161
162struct eth_rx_bd {
163 struct regpair addr;
164};
165
166/* regular ETH Rx SP CQE */
167struct eth_slow_path_rx_cqe {
168 u8 type;
169 u8 ramrod_cmd_id;
170 u8 error_flag;
171 u8 reserved[27];
172 __le16 echo;
173};
174
175/* union for all ETH Rx CQE types */
176union eth_rx_cqe {
177 struct eth_fast_path_rx_reg_cqe fast_path_regular;
178 struct eth_slow_path_rx_cqe slow_path;
179};
180
181/* ETH Rx CQE type */
182enum eth_rx_cqe_type {
183 ETH_RX_CQE_TYPE_UNUSED,
184 ETH_RX_CQE_TYPE_REGULAR,
185 ETH_RX_CQE_TYPE_SLOW_PATH,
186 MAX_ETH_RX_CQE_TYPE
187};
188
189/* ETH Rx producers data */
190struct eth_rx_prod_data {
191 __le16 bd_prod;
192 __le16 sge_prod;
193 __le16 cqe_prod;
194 __le16 reserved;
195};
196
197/* The first tx bd of a given packet */
198struct eth_tx_1st_bd {
199 struct regpair addr;
200 __le16 nbytes;
201 struct eth_tx_data_1st_bd data;
202};
203
204/* The second tx bd of a given packet */
205struct eth_tx_2nd_bd {
206 struct regpair addr;
207 __le16 nbytes;
208 struct eth_tx_data_2nd_bd data;
209};
210
211/* The parsing information data for the third tx bd of a given packet. */
212struct eth_tx_data_3rd_bd {
213 __le16 lso_mss;
214 u8 bitfields;
215#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF
216#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
217#define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF
218#define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4
219 u8 resereved0[3];
220};
221
222/* The third tx bd of a given packet */
223struct eth_tx_3rd_bd {
224 struct regpair addr;
225 __le16 nbytes;
226 struct eth_tx_data_3rd_bd data;
227};
228
229/* The common non-special TX BD ring element */
230struct eth_tx_bd {
231 struct regpair addr;
232 __le16 nbytes;
233 __le16 reserved0;
234 __le32 reserved1;
235};
236
237union eth_tx_bd_types {
238 struct eth_tx_1st_bd first_bd;
239 struct eth_tx_2nd_bd second_bd;
240 struct eth_tx_3rd_bd third_bd;
241 struct eth_tx_bd reg_bd;
242};
243
244/* Mstorm Queue Zone */
245struct mstorm_eth_queue_zone {
246 struct eth_rx_prod_data rx_producers;
247 __le32 reserved[2];
248};
249
250/* Ustorm Queue Zone */
251struct ustorm_eth_queue_zone {
252 struct coalescing_timeset int_coalescing_timeset;
253 __le16 reserved[3];
254};
255
256/* Ystorm Queue Zone */
257struct ystorm_eth_queue_zone {
258 struct coalescing_timeset int_coalescing_timeset;
259 __le16 reserved[3];
260};
261
262/* ETH doorbell data */
263struct eth_db_data {
264 u8 params;
265#define ETH_DB_DATA_DEST_MASK 0x3
266#define ETH_DB_DATA_DEST_SHIFT 0
267#define ETH_DB_DATA_AGG_CMD_MASK 0x3
268#define ETH_DB_DATA_AGG_CMD_SHIFT 2
269#define ETH_DB_DATA_BYPASS_EN_MASK 0x1
270#define ETH_DB_DATA_BYPASS_EN_SHIFT 4
271#define ETH_DB_DATA_RESERVED_MASK 0x1
272#define ETH_DB_DATA_RESERVED_SHIFT 5
273#define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3
274#define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
275 u8 agg_flags;
276 __le16 bd_prod;
277};
278
279#endif /* __ETH_COMMON__ */