blob: 7856e5241b52d1fe4931c796c302467ccc2a7d9f [file] [log] [blame]
Yuval Mintz0a7fb112016-10-01 21:59:55 +03001/* QLogic qed NIC Driver
2 *
3 * Copyright (c) 2015 QLogic Corporation
4 *
5 * This software is available under the terms of the GNU General Public License
6 * (GPL) Version 2, available from the file COPYING in the main directory of
7 * this source tree.
8 */
9
10#include <linux/types.h>
11#include <asm/byteorder.h>
12#include <linux/dma-mapping.h>
13#include <linux/if_vlan.h>
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/slab.h>
17#include <linux/stddef.h>
18#include <linux/version.h>
19#include <linux/workqueue.h>
20#include <net/ipv6.h>
21#include <linux/bitops.h>
22#include <linux/delay.h>
23#include <linux/errno.h>
24#include <linux/etherdevice.h>
25#include <linux/io.h>
26#include <linux/list.h>
27#include <linux/mutex.h>
28#include <linux/spinlock.h>
29#include <linux/string.h>
30#include <linux/qed/qed_ll2_if.h>
31#include "qed.h"
32#include "qed_cxt.h"
33#include "qed_dev_api.h"
34#include "qed_hsi.h"
35#include "qed_hw.h"
36#include "qed_int.h"
37#include "qed_ll2.h"
38#include "qed_mcp.h"
39#include "qed_reg_addr.h"
40#include "qed_sp.h"
Yuval Mintz0189efb2016-10-13 22:57:02 +030041#include "qed_roce.h"
Yuval Mintz0a7fb112016-10-01 21:59:55 +030042
43#define QED_LL2_RX_REGISTERED(ll2) ((ll2)->rx_queue.b_cb_registred)
44#define QED_LL2_TX_REGISTERED(ll2) ((ll2)->tx_queue.b_cb_registred)
45
46#define QED_LL2_TX_SIZE (256)
47#define QED_LL2_RX_SIZE (4096)
48
49struct qed_cb_ll2_info {
50 int rx_cnt;
51 u32 rx_size;
52 u8 handle;
53 bool frags_mapped;
54
55 /* Lock protecting LL2 buffer lists in sleepless context */
56 spinlock_t lock;
57 struct list_head list;
58
59 const struct qed_ll2_cb_ops *cbs;
60 void *cb_cookie;
61};
62
63struct qed_ll2_buffer {
64 struct list_head list;
65 void *data;
66 dma_addr_t phys_addr;
67};
68
69static void qed_ll2b_complete_tx_packet(struct qed_hwfn *p_hwfn,
70 u8 connection_handle,
71 void *cookie,
72 dma_addr_t first_frag_addr,
73 bool b_last_fragment,
74 bool b_last_packet)
75{
76 struct qed_dev *cdev = p_hwfn->cdev;
77 struct sk_buff *skb = cookie;
78
79 /* All we need to do is release the mapping */
80 dma_unmap_single(&p_hwfn->cdev->pdev->dev, first_frag_addr,
81 skb_headlen(skb), DMA_TO_DEVICE);
82
83 if (cdev->ll2->cbs && cdev->ll2->cbs->tx_cb)
84 cdev->ll2->cbs->tx_cb(cdev->ll2->cb_cookie, skb,
85 b_last_fragment);
86
87 if (cdev->ll2->frags_mapped)
88 /* Case where mapped frags were received, need to
89 * free skb with nr_frags marked as 0
90 */
91 skb_shinfo(skb)->nr_frags = 0;
92
93 dev_kfree_skb_any(skb);
94}
95
96static int qed_ll2_alloc_buffer(struct qed_dev *cdev,
97 u8 **data, dma_addr_t *phys_addr)
98{
99 *data = kmalloc(cdev->ll2->rx_size, GFP_ATOMIC);
100 if (!(*data)) {
101 DP_INFO(cdev, "Failed to allocate LL2 buffer data\n");
102 return -ENOMEM;
103 }
104
105 *phys_addr = dma_map_single(&cdev->pdev->dev,
106 ((*data) + NET_SKB_PAD),
107 cdev->ll2->rx_size, DMA_FROM_DEVICE);
108 if (dma_mapping_error(&cdev->pdev->dev, *phys_addr)) {
109 DP_INFO(cdev, "Failed to map LL2 buffer data\n");
110 kfree((*data));
111 return -ENOMEM;
112 }
113
114 return 0;
115}
116
117static int qed_ll2_dealloc_buffer(struct qed_dev *cdev,
118 struct qed_ll2_buffer *buffer)
119{
120 spin_lock_bh(&cdev->ll2->lock);
121
122 dma_unmap_single(&cdev->pdev->dev, buffer->phys_addr,
123 cdev->ll2->rx_size, DMA_FROM_DEVICE);
124 kfree(buffer->data);
125 list_del(&buffer->list);
126
127 cdev->ll2->rx_cnt--;
128 if (!cdev->ll2->rx_cnt)
129 DP_INFO(cdev, "All LL2 entries were removed\n");
130
131 spin_unlock_bh(&cdev->ll2->lock);
132
133 return 0;
134}
135
136static void qed_ll2_kill_buffers(struct qed_dev *cdev)
137{
138 struct qed_ll2_buffer *buffer, *tmp_buffer;
139
140 list_for_each_entry_safe(buffer, tmp_buffer, &cdev->ll2->list, list)
141 qed_ll2_dealloc_buffer(cdev, buffer);
142}
143
144void qed_ll2b_complete_rx_packet(struct qed_hwfn *p_hwfn,
145 u8 connection_handle,
146 struct qed_ll2_rx_packet *p_pkt,
147 struct core_rx_fast_path_cqe *p_cqe,
148 bool b_last_packet)
149{
150 u16 packet_length = le16_to_cpu(p_cqe->packet_length);
151 struct qed_ll2_buffer *buffer = p_pkt->cookie;
152 struct qed_dev *cdev = p_hwfn->cdev;
153 u16 vlan = le16_to_cpu(p_cqe->vlan);
154 u32 opaque_data_0, opaque_data_1;
155 u8 pad = p_cqe->placement_offset;
156 dma_addr_t new_phys_addr;
157 struct sk_buff *skb;
158 bool reuse = false;
159 int rc = -EINVAL;
160 u8 *new_data;
161
162 opaque_data_0 = le32_to_cpu(p_cqe->opaque_data.data[0]);
163 opaque_data_1 = le32_to_cpu(p_cqe->opaque_data.data[1]);
164
165 DP_VERBOSE(p_hwfn,
166 (NETIF_MSG_RX_STATUS | QED_MSG_STORAGE | NETIF_MSG_PKTDATA),
167 "Got an LL2 Rx completion: [Buffer at phys 0x%llx, offset 0x%02x] Length 0x%04x Parse_flags 0x%04x vlan 0x%04x Opaque data [0x%08x:0x%08x]\n",
168 (u64)p_pkt->rx_buf_addr, pad, packet_length,
169 le16_to_cpu(p_cqe->parse_flags.flags), vlan,
170 opaque_data_0, opaque_data_1);
171
172 if ((cdev->dp_module & NETIF_MSG_PKTDATA) && buffer->data) {
173 print_hex_dump(KERN_INFO, "",
174 DUMP_PREFIX_OFFSET, 16, 1,
175 buffer->data, packet_length, false);
176 }
177
178 /* Determine if data is valid */
179 if (packet_length < ETH_HLEN)
180 reuse = true;
181
182 /* Allocate a replacement for buffer; Reuse upon failure */
183 if (!reuse)
184 rc = qed_ll2_alloc_buffer(p_hwfn->cdev, &new_data,
185 &new_phys_addr);
186
187 /* If need to reuse or there's no replacement buffer, repost this */
188 if (rc)
189 goto out_post;
190
191 skb = build_skb(buffer->data, 0);
192 if (!skb) {
193 rc = -ENOMEM;
194 goto out_post;
195 }
196
197 pad += NET_SKB_PAD;
198 skb_reserve(skb, pad);
199 skb_put(skb, packet_length);
200 skb_checksum_none_assert(skb);
201
202 /* Get parital ethernet information instead of eth_type_trans(),
203 * Since we don't have an associated net_device.
204 */
205 skb_reset_mac_header(skb);
206 skb->protocol = eth_hdr(skb)->h_proto;
207
208 /* Pass SKB onward */
209 if (cdev->ll2->cbs && cdev->ll2->cbs->rx_cb) {
210 if (vlan)
211 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan);
212 cdev->ll2->cbs->rx_cb(cdev->ll2->cb_cookie, skb,
213 opaque_data_0, opaque_data_1);
214 }
215
216 /* Update Buffer information and update FW producer */
217 buffer->data = new_data;
218 buffer->phys_addr = new_phys_addr;
219
220out_post:
221 rc = qed_ll2_post_rx_buffer(QED_LEADING_HWFN(cdev), cdev->ll2->handle,
222 buffer->phys_addr, 0, buffer, 1);
223
224 if (rc)
225 qed_ll2_dealloc_buffer(cdev, buffer);
226}
227
228static struct qed_ll2_info *__qed_ll2_handle_sanity(struct qed_hwfn *p_hwfn,
229 u8 connection_handle,
230 bool b_lock,
231 bool b_only_active)
232{
233 struct qed_ll2_info *p_ll2_conn, *p_ret = NULL;
234
235 if (connection_handle >= QED_MAX_NUM_OF_LL2_CONNECTIONS)
236 return NULL;
237
238 if (!p_hwfn->p_ll2_info)
239 return NULL;
240
241 p_ll2_conn = &p_hwfn->p_ll2_info[connection_handle];
242
243 if (b_only_active) {
244 if (b_lock)
245 mutex_lock(&p_ll2_conn->mutex);
246 if (p_ll2_conn->b_active)
247 p_ret = p_ll2_conn;
248 if (b_lock)
249 mutex_unlock(&p_ll2_conn->mutex);
250 } else {
251 p_ret = p_ll2_conn;
252 }
253
254 return p_ret;
255}
256
257static struct qed_ll2_info *qed_ll2_handle_sanity(struct qed_hwfn *p_hwfn,
258 u8 connection_handle)
259{
260 return __qed_ll2_handle_sanity(p_hwfn, connection_handle, false, true);
261}
262
263static struct qed_ll2_info *qed_ll2_handle_sanity_lock(struct qed_hwfn *p_hwfn,
264 u8 connection_handle)
265{
266 return __qed_ll2_handle_sanity(p_hwfn, connection_handle, true, true);
267}
268
269static struct qed_ll2_info *qed_ll2_handle_sanity_inactive(struct qed_hwfn
270 *p_hwfn,
271 u8 connection_handle)
272{
273 return __qed_ll2_handle_sanity(p_hwfn, connection_handle, false, false);
274}
275
276static void qed_ll2_txq_flush(struct qed_hwfn *p_hwfn, u8 connection_handle)
277{
278 bool b_last_packet = false, b_last_frag = false;
279 struct qed_ll2_tx_packet *p_pkt = NULL;
280 struct qed_ll2_info *p_ll2_conn;
281 struct qed_ll2_tx_queue *p_tx;
Ram Amraniabd49672016-10-01 22:00:01 +0300282 dma_addr_t tx_frag;
Yuval Mintz0a7fb112016-10-01 21:59:55 +0300283
284 p_ll2_conn = qed_ll2_handle_sanity_inactive(p_hwfn, connection_handle);
285 if (!p_ll2_conn)
286 return;
287
288 p_tx = &p_ll2_conn->tx_queue;
289
290 while (!list_empty(&p_tx->active_descq)) {
291 p_pkt = list_first_entry(&p_tx->active_descq,
292 struct qed_ll2_tx_packet, list_entry);
293 if (!p_pkt)
294 break;
295
296 list_del(&p_pkt->list_entry);
297 b_last_packet = list_empty(&p_tx->active_descq);
298 list_add_tail(&p_pkt->list_entry, &p_tx->free_descq);
299 p_tx->cur_completing_packet = *p_pkt;
300 p_tx->cur_completing_bd_idx = 1;
301 b_last_frag = p_tx->cur_completing_bd_idx == p_pkt->bd_used;
Ram Amraniabd49672016-10-01 22:00:01 +0300302 tx_frag = p_pkt->bds_set[0].tx_frag;
303 if (p_ll2_conn->gsi_enable)
304 qed_ll2b_release_tx_gsi_packet(p_hwfn,
305 p_ll2_conn->my_id,
306 p_pkt->cookie,
307 tx_frag,
308 b_last_frag,
309 b_last_packet);
310 else
311 qed_ll2b_complete_tx_packet(p_hwfn,
312 p_ll2_conn->my_id,
313 p_pkt->cookie,
314 tx_frag,
315 b_last_frag,
316 b_last_packet);
Yuval Mintz0a7fb112016-10-01 21:59:55 +0300317
Yuval Mintz0a7fb112016-10-01 21:59:55 +0300318 }
319}
320
321static int qed_ll2_txq_completion(struct qed_hwfn *p_hwfn, void *p_cookie)
322{
323 struct qed_ll2_info *p_ll2_conn = p_cookie;
324 struct qed_ll2_tx_queue *p_tx = &p_ll2_conn->tx_queue;
325 u16 new_idx = 0, num_bds = 0, num_bds_in_packet = 0;
326 struct qed_ll2_tx_packet *p_pkt;
327 bool b_last_frag = false;
328 unsigned long flags;
Ram Amraniabd49672016-10-01 22:00:01 +0300329 dma_addr_t tx_frag;
Yuval Mintz0a7fb112016-10-01 21:59:55 +0300330 int rc = -EINVAL;
331
332 spin_lock_irqsave(&p_tx->lock, flags);
333 if (p_tx->b_completing_packet) {
334 rc = -EBUSY;
335 goto out;
336 }
337
338 new_idx = le16_to_cpu(*p_tx->p_fw_cons);
339 num_bds = ((s16)new_idx - (s16)p_tx->bds_idx);
340 while (num_bds) {
341 if (list_empty(&p_tx->active_descq))
342 goto out;
343
344 p_pkt = list_first_entry(&p_tx->active_descq,
345 struct qed_ll2_tx_packet, list_entry);
346 if (!p_pkt)
347 goto out;
348
349 p_tx->b_completing_packet = true;
350 p_tx->cur_completing_packet = *p_pkt;
351 num_bds_in_packet = p_pkt->bd_used;
352 list_del(&p_pkt->list_entry);
353
354 if (num_bds < num_bds_in_packet) {
355 DP_NOTICE(p_hwfn,
356 "Rest of BDs does not cover whole packet\n");
357 goto out;
358 }
359
360 num_bds -= num_bds_in_packet;
361 p_tx->bds_idx += num_bds_in_packet;
362 while (num_bds_in_packet--)
363 qed_chain_consume(&p_tx->txq_chain);
364
365 p_tx->cur_completing_bd_idx = 1;
366 b_last_frag = p_tx->cur_completing_bd_idx == p_pkt->bd_used;
367 list_add_tail(&p_pkt->list_entry, &p_tx->free_descq);
368
369 spin_unlock_irqrestore(&p_tx->lock, flags);
Ram Amraniabd49672016-10-01 22:00:01 +0300370 tx_frag = p_pkt->bds_set[0].tx_frag;
371 if (p_ll2_conn->gsi_enable)
372 qed_ll2b_complete_tx_gsi_packet(p_hwfn,
373 p_ll2_conn->my_id,
374 p_pkt->cookie,
375 tx_frag,
376 b_last_frag, !num_bds);
377 else
378 qed_ll2b_complete_tx_packet(p_hwfn,
379 p_ll2_conn->my_id,
380 p_pkt->cookie,
381 tx_frag,
382 b_last_frag, !num_bds);
Yuval Mintz0a7fb112016-10-01 21:59:55 +0300383 spin_lock_irqsave(&p_tx->lock, flags);
384 }
385
386 p_tx->b_completing_packet = false;
387 rc = 0;
388out:
389 spin_unlock_irqrestore(&p_tx->lock, flags);
390 return rc;
391}
392
Ram Amraniabd49672016-10-01 22:00:01 +0300393static int
394qed_ll2_rxq_completion_gsi(struct qed_hwfn *p_hwfn,
395 struct qed_ll2_info *p_ll2_info,
396 union core_rx_cqe_union *p_cqe,
397 unsigned long lock_flags, bool b_last_cqe)
398{
399 struct qed_ll2_rx_queue *p_rx = &p_ll2_info->rx_queue;
400 struct qed_ll2_rx_packet *p_pkt = NULL;
401 u16 packet_length, parse_flags, vlan;
402 u32 src_mac_addrhi;
403 u16 src_mac_addrlo;
404
405 if (!list_empty(&p_rx->active_descq))
406 p_pkt = list_first_entry(&p_rx->active_descq,
407 struct qed_ll2_rx_packet, list_entry);
408 if (!p_pkt) {
409 DP_NOTICE(p_hwfn,
410 "GSI Rx completion but active_descq is empty\n");
411 return -EIO;
412 }
413
414 list_del(&p_pkt->list_entry);
415 parse_flags = le16_to_cpu(p_cqe->rx_cqe_gsi.parse_flags.flags);
416 packet_length = le16_to_cpu(p_cqe->rx_cqe_gsi.data_length);
417 vlan = le16_to_cpu(p_cqe->rx_cqe_gsi.vlan);
418 src_mac_addrhi = le32_to_cpu(p_cqe->rx_cqe_gsi.src_mac_addrhi);
419 src_mac_addrlo = le16_to_cpu(p_cqe->rx_cqe_gsi.src_mac_addrlo);
420 if (qed_chain_consume(&p_rx->rxq_chain) != p_pkt->rxq_bd)
421 DP_NOTICE(p_hwfn,
422 "Mismatch between active_descq and the LL2 Rx chain\n");
423 list_add_tail(&p_pkt->list_entry, &p_rx->free_descq);
424
425 spin_unlock_irqrestore(&p_rx->lock, lock_flags);
426 qed_ll2b_complete_rx_gsi_packet(p_hwfn,
427 p_ll2_info->my_id,
428 p_pkt->cookie,
429 p_pkt->rx_buf_addr,
430 packet_length,
431 p_cqe->rx_cqe_gsi.data_length_error,
432 parse_flags,
433 vlan,
434 src_mac_addrhi,
435 src_mac_addrlo, b_last_cqe);
436 spin_lock_irqsave(&p_rx->lock, lock_flags);
437
438 return 0;
439}
440
Yuval Mintz0a7fb112016-10-01 21:59:55 +0300441static int qed_ll2_rxq_completion_reg(struct qed_hwfn *p_hwfn,
442 struct qed_ll2_info *p_ll2_conn,
443 union core_rx_cqe_union *p_cqe,
444 unsigned long lock_flags,
445 bool b_last_cqe)
446{
447 struct qed_ll2_rx_queue *p_rx = &p_ll2_conn->rx_queue;
448 struct qed_ll2_rx_packet *p_pkt = NULL;
449
450 if (!list_empty(&p_rx->active_descq))
451 p_pkt = list_first_entry(&p_rx->active_descq,
452 struct qed_ll2_rx_packet, list_entry);
453 if (!p_pkt) {
454 DP_NOTICE(p_hwfn,
455 "LL2 Rx completion but active_descq is empty\n");
456 return -EIO;
457 }
458 list_del(&p_pkt->list_entry);
459
460 if (qed_chain_consume(&p_rx->rxq_chain) != p_pkt->rxq_bd)
461 DP_NOTICE(p_hwfn,
462 "Mismatch between active_descq and the LL2 Rx chain\n");
463 list_add_tail(&p_pkt->list_entry, &p_rx->free_descq);
464
465 spin_unlock_irqrestore(&p_rx->lock, lock_flags);
466 qed_ll2b_complete_rx_packet(p_hwfn, p_ll2_conn->my_id,
467 p_pkt, &p_cqe->rx_cqe_fp, b_last_cqe);
468 spin_lock_irqsave(&p_rx->lock, lock_flags);
469
470 return 0;
471}
472
473static int qed_ll2_rxq_completion(struct qed_hwfn *p_hwfn, void *cookie)
474{
475 struct qed_ll2_info *p_ll2_conn = cookie;
476 struct qed_ll2_rx_queue *p_rx = &p_ll2_conn->rx_queue;
477 union core_rx_cqe_union *cqe = NULL;
478 u16 cq_new_idx = 0, cq_old_idx = 0;
479 unsigned long flags = 0;
480 int rc = 0;
481
482 spin_lock_irqsave(&p_rx->lock, flags);
483 cq_new_idx = le16_to_cpu(*p_rx->p_fw_cons);
484 cq_old_idx = qed_chain_get_cons_idx(&p_rx->rcq_chain);
485
486 while (cq_new_idx != cq_old_idx) {
487 bool b_last_cqe = (cq_new_idx == cq_old_idx);
488
489 cqe = qed_chain_consume(&p_rx->rcq_chain);
490 cq_old_idx = qed_chain_get_cons_idx(&p_rx->rcq_chain);
491
492 DP_VERBOSE(p_hwfn,
493 QED_MSG_LL2,
494 "LL2 [sw. cons %04x, fw. at %04x] - Got Packet of type %02x\n",
495 cq_old_idx, cq_new_idx, cqe->rx_cqe_sp.type);
496
497 switch (cqe->rx_cqe_sp.type) {
498 case CORE_RX_CQE_TYPE_SLOW_PATH:
499 DP_NOTICE(p_hwfn, "LL2 - unexpected Rx CQE slowpath\n");
500 rc = -EINVAL;
501 break;
Ram Amraniabd49672016-10-01 22:00:01 +0300502 case CORE_RX_CQE_TYPE_GSI_OFFLOAD:
503 rc = qed_ll2_rxq_completion_gsi(p_hwfn, p_ll2_conn,
504 cqe, flags, b_last_cqe);
505 break;
Yuval Mintz0a7fb112016-10-01 21:59:55 +0300506 case CORE_RX_CQE_TYPE_REGULAR:
507 rc = qed_ll2_rxq_completion_reg(p_hwfn, p_ll2_conn,
508 cqe, flags, b_last_cqe);
509 break;
510 default:
511 rc = -EIO;
512 }
513 }
514
515 spin_unlock_irqrestore(&p_rx->lock, flags);
516 return rc;
517}
518
519void qed_ll2_rxq_flush(struct qed_hwfn *p_hwfn, u8 connection_handle)
520{
521 struct qed_ll2_info *p_ll2_conn = NULL;
522 struct qed_ll2_rx_packet *p_pkt = NULL;
523 struct qed_ll2_rx_queue *p_rx;
524
525 p_ll2_conn = qed_ll2_handle_sanity_inactive(p_hwfn, connection_handle);
526 if (!p_ll2_conn)
527 return;
528
529 p_rx = &p_ll2_conn->rx_queue;
530
531 while (!list_empty(&p_rx->active_descq)) {
532 dma_addr_t rx_buf_addr;
533 void *cookie;
534 bool b_last;
535
536 p_pkt = list_first_entry(&p_rx->active_descq,
537 struct qed_ll2_rx_packet, list_entry);
538 if (!p_pkt)
539 break;
540
541 list_del(&p_pkt->list_entry);
542 list_add_tail(&p_pkt->list_entry, &p_rx->free_descq);
543
544 rx_buf_addr = p_pkt->rx_buf_addr;
545 cookie = p_pkt->cookie;
546
547 b_last = list_empty(&p_rx->active_descq);
548 }
549}
550
551static int qed_sp_ll2_rx_queue_start(struct qed_hwfn *p_hwfn,
552 struct qed_ll2_info *p_ll2_conn,
553 u8 action_on_error)
554{
555 enum qed_ll2_conn_type conn_type = p_ll2_conn->conn_type;
556 struct qed_ll2_rx_queue *p_rx = &p_ll2_conn->rx_queue;
557 struct core_rx_start_ramrod_data *p_ramrod = NULL;
558 struct qed_spq_entry *p_ent = NULL;
559 struct qed_sp_init_data init_data;
560 u16 cqe_pbl_size;
561 int rc = 0;
562
563 /* Get SPQ entry */
564 memset(&init_data, 0, sizeof(init_data));
565 init_data.cid = p_ll2_conn->cid;
566 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
567 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
568
569 rc = qed_sp_init_request(p_hwfn, &p_ent,
570 CORE_RAMROD_RX_QUEUE_START,
571 PROTOCOLID_CORE, &init_data);
572 if (rc)
573 return rc;
574
575 p_ramrod = &p_ent->ramrod.core_rx_queue_start;
576
577 p_ramrod->sb_id = cpu_to_le16(qed_int_get_sp_sb_id(p_hwfn));
578 p_ramrod->sb_index = p_rx->rx_sb_index;
579 p_ramrod->complete_event_flg = 1;
580
581 p_ramrod->mtu = cpu_to_le16(p_ll2_conn->mtu);
582 DMA_REGPAIR_LE(p_ramrod->bd_base,
583 p_rx->rxq_chain.p_phys_addr);
584 cqe_pbl_size = (u16)qed_chain_get_page_cnt(&p_rx->rcq_chain);
585 p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size);
586 DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr,
587 qed_chain_get_pbl_phys(&p_rx->rcq_chain));
588
589 p_ramrod->drop_ttl0_flg = p_ll2_conn->rx_drop_ttl0_flg;
590 p_ramrod->inner_vlan_removal_en = p_ll2_conn->rx_vlan_removal_en;
591 p_ramrod->queue_id = p_ll2_conn->queue_id;
592 p_ramrod->main_func_queue = 1;
593
594 if ((IS_MF_DEFAULT(p_hwfn) || IS_MF_SI(p_hwfn)) &&
595 p_ramrod->main_func_queue && (conn_type != QED_LL2_TYPE_ROCE)) {
596 p_ramrod->mf_si_bcast_accept_all = 1;
597 p_ramrod->mf_si_mcast_accept_all = 1;
598 } else {
599 p_ramrod->mf_si_bcast_accept_all = 0;
600 p_ramrod->mf_si_mcast_accept_all = 0;
601 }
602
603 p_ramrod->action_on_error.error_type = action_on_error;
Ram Amraniabd49672016-10-01 22:00:01 +0300604 p_ramrod->gsi_offload_flag = p_ll2_conn->gsi_enable;
Yuval Mintz0a7fb112016-10-01 21:59:55 +0300605 return qed_spq_post(p_hwfn, p_ent, NULL);
606}
607
608static int qed_sp_ll2_tx_queue_start(struct qed_hwfn *p_hwfn,
609 struct qed_ll2_info *p_ll2_conn)
610{
611 enum qed_ll2_conn_type conn_type = p_ll2_conn->conn_type;
612 struct qed_ll2_tx_queue *p_tx = &p_ll2_conn->tx_queue;
613 struct core_tx_start_ramrod_data *p_ramrod = NULL;
614 struct qed_spq_entry *p_ent = NULL;
615 struct qed_sp_init_data init_data;
616 union qed_qm_pq_params pq_params;
617 u16 pq_id = 0, pbl_size;
618 int rc = -EINVAL;
619
620 if (!QED_LL2_TX_REGISTERED(p_ll2_conn))
621 return 0;
622
623 /* Get SPQ entry */
624 memset(&init_data, 0, sizeof(init_data));
625 init_data.cid = p_ll2_conn->cid;
626 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
627 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
628
629 rc = qed_sp_init_request(p_hwfn, &p_ent,
630 CORE_RAMROD_TX_QUEUE_START,
631 PROTOCOLID_CORE, &init_data);
632 if (rc)
633 return rc;
634
635 p_ramrod = &p_ent->ramrod.core_tx_queue_start;
636
637 p_ramrod->sb_id = cpu_to_le16(qed_int_get_sp_sb_id(p_hwfn));
638 p_ramrod->sb_index = p_tx->tx_sb_index;
639 p_ramrod->mtu = cpu_to_le16(p_ll2_conn->mtu);
640 p_ll2_conn->tx_stats_en = 1;
641 p_ramrod->stats_en = p_ll2_conn->tx_stats_en;
642 p_ramrod->stats_id = p_ll2_conn->tx_stats_id;
643
644 DMA_REGPAIR_LE(p_ramrod->pbl_base_addr,
645 qed_chain_get_pbl_phys(&p_tx->txq_chain));
646 pbl_size = qed_chain_get_page_cnt(&p_tx->txq_chain);
647 p_ramrod->pbl_size = cpu_to_le16(pbl_size);
648
649 memset(&pq_params, 0, sizeof(pq_params));
650 pq_params.core.tc = p_ll2_conn->tx_tc;
651 pq_id = qed_get_qm_pq(p_hwfn, PROTOCOLID_CORE, &pq_params);
652 p_ramrod->qm_pq_id = cpu_to_le16(pq_id);
653
654 switch (conn_type) {
655 case QED_LL2_TYPE_ISCSI:
656 case QED_LL2_TYPE_ISCSI_OOO:
657 p_ramrod->conn_type = PROTOCOLID_ISCSI;
658 break;
659 case QED_LL2_TYPE_ROCE:
660 p_ramrod->conn_type = PROTOCOLID_ROCE;
661 break;
662 default:
663 p_ramrod->conn_type = PROTOCOLID_ETH;
664 DP_NOTICE(p_hwfn, "Unknown connection type: %d\n", conn_type);
665 }
666
Ram Amraniabd49672016-10-01 22:00:01 +0300667 p_ramrod->gsi_offload_flag = p_ll2_conn->gsi_enable;
Yuval Mintz0a7fb112016-10-01 21:59:55 +0300668 return qed_spq_post(p_hwfn, p_ent, NULL);
669}
670
671static int qed_sp_ll2_rx_queue_stop(struct qed_hwfn *p_hwfn,
672 struct qed_ll2_info *p_ll2_conn)
673{
674 struct core_rx_stop_ramrod_data *p_ramrod = NULL;
675 struct qed_spq_entry *p_ent = NULL;
676 struct qed_sp_init_data init_data;
677 int rc = -EINVAL;
678
679 /* Get SPQ entry */
680 memset(&init_data, 0, sizeof(init_data));
681 init_data.cid = p_ll2_conn->cid;
682 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
683 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
684
685 rc = qed_sp_init_request(p_hwfn, &p_ent,
686 CORE_RAMROD_RX_QUEUE_STOP,
687 PROTOCOLID_CORE, &init_data);
688 if (rc)
689 return rc;
690
691 p_ramrod = &p_ent->ramrod.core_rx_queue_stop;
692
693 p_ramrod->complete_event_flg = 1;
694 p_ramrod->queue_id = p_ll2_conn->queue_id;
695
696 return qed_spq_post(p_hwfn, p_ent, NULL);
697}
698
699static int qed_sp_ll2_tx_queue_stop(struct qed_hwfn *p_hwfn,
700 struct qed_ll2_info *p_ll2_conn)
701{
702 struct qed_spq_entry *p_ent = NULL;
703 struct qed_sp_init_data init_data;
704 int rc = -EINVAL;
705
706 /* Get SPQ entry */
707 memset(&init_data, 0, sizeof(init_data));
708 init_data.cid = p_ll2_conn->cid;
709 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
710 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
711
712 rc = qed_sp_init_request(p_hwfn, &p_ent,
713 CORE_RAMROD_TX_QUEUE_STOP,
714 PROTOCOLID_CORE, &init_data);
715 if (rc)
716 return rc;
717
718 return qed_spq_post(p_hwfn, p_ent, NULL);
719}
720
721static int
722qed_ll2_acquire_connection_rx(struct qed_hwfn *p_hwfn,
723 struct qed_ll2_info *p_ll2_info, u16 rx_num_desc)
724{
725 struct qed_ll2_rx_packet *p_descq;
726 u32 capacity;
727 int rc = 0;
728
729 if (!rx_num_desc)
730 goto out;
731
732 rc = qed_chain_alloc(p_hwfn->cdev,
733 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
734 QED_CHAIN_MODE_NEXT_PTR,
735 QED_CHAIN_CNT_TYPE_U16,
736 rx_num_desc,
737 sizeof(struct core_rx_bd),
738 &p_ll2_info->rx_queue.rxq_chain);
739 if (rc) {
740 DP_NOTICE(p_hwfn, "Failed to allocate ll2 rxq chain\n");
741 goto out;
742 }
743
744 capacity = qed_chain_get_capacity(&p_ll2_info->rx_queue.rxq_chain);
745 p_descq = kcalloc(capacity, sizeof(struct qed_ll2_rx_packet),
746 GFP_KERNEL);
747 if (!p_descq) {
748 rc = -ENOMEM;
749 DP_NOTICE(p_hwfn, "Failed to allocate ll2 Rx desc\n");
750 goto out;
751 }
752 p_ll2_info->rx_queue.descq_array = p_descq;
753
754 rc = qed_chain_alloc(p_hwfn->cdev,
755 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
756 QED_CHAIN_MODE_PBL,
757 QED_CHAIN_CNT_TYPE_U16,
758 rx_num_desc,
759 sizeof(struct core_rx_fast_path_cqe),
760 &p_ll2_info->rx_queue.rcq_chain);
761 if (rc) {
762 DP_NOTICE(p_hwfn, "Failed to allocate ll2 rcq chain\n");
763 goto out;
764 }
765
766 DP_VERBOSE(p_hwfn, QED_MSG_LL2,
767 "Allocated LL2 Rxq [Type %08x] with 0x%08x buffers\n",
768 p_ll2_info->conn_type, rx_num_desc);
769
770out:
771 return rc;
772}
773
774static int qed_ll2_acquire_connection_tx(struct qed_hwfn *p_hwfn,
775 struct qed_ll2_info *p_ll2_info,
776 u16 tx_num_desc)
777{
778 struct qed_ll2_tx_packet *p_descq;
779 u32 capacity;
780 int rc = 0;
781
782 if (!tx_num_desc)
783 goto out;
784
785 rc = qed_chain_alloc(p_hwfn->cdev,
786 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
787 QED_CHAIN_MODE_PBL,
788 QED_CHAIN_CNT_TYPE_U16,
789 tx_num_desc,
790 sizeof(struct core_tx_bd),
791 &p_ll2_info->tx_queue.txq_chain);
792 if (rc)
793 goto out;
794
795 capacity = qed_chain_get_capacity(&p_ll2_info->tx_queue.txq_chain);
796 p_descq = kcalloc(capacity, sizeof(struct qed_ll2_tx_packet),
797 GFP_KERNEL);
798 if (!p_descq) {
799 rc = -ENOMEM;
800 goto out;
801 }
802 p_ll2_info->tx_queue.descq_array = p_descq;
803
804 DP_VERBOSE(p_hwfn, QED_MSG_LL2,
805 "Allocated LL2 Txq [Type %08x] with 0x%08x buffers\n",
806 p_ll2_info->conn_type, tx_num_desc);
807
808out:
809 if (rc)
810 DP_NOTICE(p_hwfn,
811 "Can't allocate memory for Tx LL2 with 0x%08x buffers\n",
812 tx_num_desc);
813 return rc;
814}
815
816int qed_ll2_acquire_connection(struct qed_hwfn *p_hwfn,
817 struct qed_ll2_info *p_params,
818 u16 rx_num_desc,
819 u16 tx_num_desc,
820 u8 *p_connection_handle)
821{
822 qed_int_comp_cb_t comp_rx_cb, comp_tx_cb;
823 struct qed_ll2_info *p_ll2_info = NULL;
824 int rc;
825 u8 i;
826
827 if (!p_connection_handle || !p_hwfn->p_ll2_info)
828 return -EINVAL;
829
830 /* Find a free connection to be used */
831 for (i = 0; (i < QED_MAX_NUM_OF_LL2_CONNECTIONS); i++) {
832 mutex_lock(&p_hwfn->p_ll2_info[i].mutex);
833 if (p_hwfn->p_ll2_info[i].b_active) {
834 mutex_unlock(&p_hwfn->p_ll2_info[i].mutex);
835 continue;
836 }
837
838 p_hwfn->p_ll2_info[i].b_active = true;
839 p_ll2_info = &p_hwfn->p_ll2_info[i];
840 mutex_unlock(&p_hwfn->p_ll2_info[i].mutex);
841 break;
842 }
843 if (!p_ll2_info)
844 return -EBUSY;
845
846 p_ll2_info->conn_type = p_params->conn_type;
847 p_ll2_info->mtu = p_params->mtu;
848 p_ll2_info->rx_drop_ttl0_flg = p_params->rx_drop_ttl0_flg;
849 p_ll2_info->rx_vlan_removal_en = p_params->rx_vlan_removal_en;
850 p_ll2_info->tx_tc = p_params->tx_tc;
851 p_ll2_info->tx_dest = p_params->tx_dest;
852 p_ll2_info->ai_err_packet_too_big = p_params->ai_err_packet_too_big;
853 p_ll2_info->ai_err_no_buf = p_params->ai_err_no_buf;
Ram Amraniabd49672016-10-01 22:00:01 +0300854 p_ll2_info->gsi_enable = p_params->gsi_enable;
Yuval Mintz0a7fb112016-10-01 21:59:55 +0300855
856 rc = qed_ll2_acquire_connection_rx(p_hwfn, p_ll2_info, rx_num_desc);
857 if (rc)
858 goto q_allocate_fail;
859
860 rc = qed_ll2_acquire_connection_tx(p_hwfn, p_ll2_info, tx_num_desc);
861 if (rc)
862 goto q_allocate_fail;
863
864 /* Register callbacks for the Rx/Tx queues */
865 comp_rx_cb = qed_ll2_rxq_completion;
866 comp_tx_cb = qed_ll2_txq_completion;
867
868 if (rx_num_desc) {
869 qed_int_register_cb(p_hwfn, comp_rx_cb,
870 &p_hwfn->p_ll2_info[i],
871 &p_ll2_info->rx_queue.rx_sb_index,
872 &p_ll2_info->rx_queue.p_fw_cons);
873 p_ll2_info->rx_queue.b_cb_registred = true;
874 }
875
876 if (tx_num_desc) {
877 qed_int_register_cb(p_hwfn,
878 comp_tx_cb,
879 &p_hwfn->p_ll2_info[i],
880 &p_ll2_info->tx_queue.tx_sb_index,
881 &p_ll2_info->tx_queue.p_fw_cons);
882 p_ll2_info->tx_queue.b_cb_registred = true;
883 }
884
885 *p_connection_handle = i;
886 return rc;
887
888q_allocate_fail:
889 qed_ll2_release_connection(p_hwfn, i);
890 return -ENOMEM;
891}
892
893static int qed_ll2_establish_connection_rx(struct qed_hwfn *p_hwfn,
894 struct qed_ll2_info *p_ll2_conn)
895{
896 u8 action_on_error = 0;
897
898 if (!QED_LL2_RX_REGISTERED(p_ll2_conn))
899 return 0;
900
901 DIRECT_REG_WR(p_ll2_conn->rx_queue.set_prod_addr, 0x0);
902
903 SET_FIELD(action_on_error,
904 CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG,
905 p_ll2_conn->ai_err_packet_too_big);
906 SET_FIELD(action_on_error,
907 CORE_RX_ACTION_ON_ERROR_NO_BUFF, p_ll2_conn->ai_err_no_buf);
908
909 return qed_sp_ll2_rx_queue_start(p_hwfn, p_ll2_conn, action_on_error);
910}
911
912int qed_ll2_establish_connection(struct qed_hwfn *p_hwfn, u8 connection_handle)
913{
914 struct qed_ll2_info *p_ll2_conn;
915 struct qed_ll2_rx_queue *p_rx;
916 struct qed_ll2_tx_queue *p_tx;
917 int rc = -EINVAL;
918 u32 i, capacity;
919 u8 qid;
920
921 p_ll2_conn = qed_ll2_handle_sanity_lock(p_hwfn, connection_handle);
922 if (!p_ll2_conn)
923 return -EINVAL;
924 p_rx = &p_ll2_conn->rx_queue;
925 p_tx = &p_ll2_conn->tx_queue;
926
927 qed_chain_reset(&p_rx->rxq_chain);
928 qed_chain_reset(&p_rx->rcq_chain);
929 INIT_LIST_HEAD(&p_rx->active_descq);
930 INIT_LIST_HEAD(&p_rx->free_descq);
931 INIT_LIST_HEAD(&p_rx->posting_descq);
932 spin_lock_init(&p_rx->lock);
933 capacity = qed_chain_get_capacity(&p_rx->rxq_chain);
934 for (i = 0; i < capacity; i++)
935 list_add_tail(&p_rx->descq_array[i].list_entry,
936 &p_rx->free_descq);
937 *p_rx->p_fw_cons = 0;
938
939 qed_chain_reset(&p_tx->txq_chain);
940 INIT_LIST_HEAD(&p_tx->active_descq);
941 INIT_LIST_HEAD(&p_tx->free_descq);
942 INIT_LIST_HEAD(&p_tx->sending_descq);
943 spin_lock_init(&p_tx->lock);
944 capacity = qed_chain_get_capacity(&p_tx->txq_chain);
945 for (i = 0; i < capacity; i++)
946 list_add_tail(&p_tx->descq_array[i].list_entry,
947 &p_tx->free_descq);
948 p_tx->cur_completing_bd_idx = 0;
949 p_tx->bds_idx = 0;
950 p_tx->b_completing_packet = false;
951 p_tx->cur_send_packet = NULL;
952 p_tx->cur_send_frag_num = 0;
953 p_tx->cur_completing_frag_num = 0;
954 *p_tx->p_fw_cons = 0;
955
956 qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_CORE, &p_ll2_conn->cid);
957
958 qid = p_hwfn->hw_info.resc_start[QED_LL2_QUEUE] + connection_handle;
959 p_ll2_conn->queue_id = qid;
960 p_ll2_conn->tx_stats_id = qid;
961 p_rx->set_prod_addr = (u8 __iomem *)p_hwfn->regview +
962 GTT_BAR0_MAP_REG_TSDM_RAM +
963 TSTORM_LL2_RX_PRODS_OFFSET(qid);
964 p_tx->doorbell_addr = (u8 __iomem *)p_hwfn->doorbells +
965 qed_db_addr(p_ll2_conn->cid,
966 DQ_DEMS_LEGACY);
967
968 rc = qed_ll2_establish_connection_rx(p_hwfn, p_ll2_conn);
969 if (rc)
970 return rc;
971
972 rc = qed_sp_ll2_tx_queue_start(p_hwfn, p_ll2_conn);
973 if (rc)
974 return rc;
975
976 if (p_hwfn->hw_info.personality != QED_PCI_ETH_ROCE)
977 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PRS_REG_USE_LIGHT_L2, 1);
978
979 return rc;
980}
981
982static void qed_ll2_post_rx_buffer_notify_fw(struct qed_hwfn *p_hwfn,
983 struct qed_ll2_rx_queue *p_rx,
984 struct qed_ll2_rx_packet *p_curp)
985{
986 struct qed_ll2_rx_packet *p_posting_packet = NULL;
987 struct core_ll2_rx_prod rx_prod = { 0, 0, 0 };
988 bool b_notify_fw = false;
989 u16 bd_prod, cq_prod;
990
991 /* This handles the flushing of already posted buffers */
992 while (!list_empty(&p_rx->posting_descq)) {
993 p_posting_packet = list_first_entry(&p_rx->posting_descq,
994 struct qed_ll2_rx_packet,
995 list_entry);
996 list_del(&p_posting_packet->list_entry);
997 list_add_tail(&p_posting_packet->list_entry,
998 &p_rx->active_descq);
999 b_notify_fw = true;
1000 }
1001
1002 /* This handles the supplied packet [if there is one] */
1003 if (p_curp) {
1004 list_add_tail(&p_curp->list_entry, &p_rx->active_descq);
1005 b_notify_fw = true;
1006 }
1007
1008 if (!b_notify_fw)
1009 return;
1010
1011 bd_prod = qed_chain_get_prod_idx(&p_rx->rxq_chain);
1012 cq_prod = qed_chain_get_prod_idx(&p_rx->rcq_chain);
1013 rx_prod.bd_prod = cpu_to_le16(bd_prod);
1014 rx_prod.cqe_prod = cpu_to_le16(cq_prod);
1015 DIRECT_REG_WR(p_rx->set_prod_addr, *((u32 *)&rx_prod));
1016}
1017
1018int qed_ll2_post_rx_buffer(struct qed_hwfn *p_hwfn,
1019 u8 connection_handle,
1020 dma_addr_t addr,
1021 u16 buf_len, void *cookie, u8 notify_fw)
1022{
1023 struct core_rx_bd_with_buff_len *p_curb = NULL;
1024 struct qed_ll2_rx_packet *p_curp = NULL;
1025 struct qed_ll2_info *p_ll2_conn;
1026 struct qed_ll2_rx_queue *p_rx;
1027 unsigned long flags;
1028 void *p_data;
1029 int rc = 0;
1030
1031 p_ll2_conn = qed_ll2_handle_sanity(p_hwfn, connection_handle);
1032 if (!p_ll2_conn)
1033 return -EINVAL;
1034 p_rx = &p_ll2_conn->rx_queue;
1035
1036 spin_lock_irqsave(&p_rx->lock, flags);
1037 if (!list_empty(&p_rx->free_descq))
1038 p_curp = list_first_entry(&p_rx->free_descq,
1039 struct qed_ll2_rx_packet, list_entry);
1040 if (p_curp) {
1041 if (qed_chain_get_elem_left(&p_rx->rxq_chain) &&
1042 qed_chain_get_elem_left(&p_rx->rcq_chain)) {
1043 p_data = qed_chain_produce(&p_rx->rxq_chain);
1044 p_curb = (struct core_rx_bd_with_buff_len *)p_data;
1045 qed_chain_produce(&p_rx->rcq_chain);
1046 }
1047 }
1048
1049 /* If we're lacking entires, let's try to flush buffers to FW */
1050 if (!p_curp || !p_curb) {
1051 rc = -EBUSY;
1052 p_curp = NULL;
1053 goto out_notify;
1054 }
1055
1056 /* We have an Rx packet we can fill */
1057 DMA_REGPAIR_LE(p_curb->addr, addr);
1058 p_curb->buff_length = cpu_to_le16(buf_len);
1059 p_curp->rx_buf_addr = addr;
1060 p_curp->cookie = cookie;
1061 p_curp->rxq_bd = p_curb;
1062 p_curp->buf_length = buf_len;
1063 list_del(&p_curp->list_entry);
1064
1065 /* Check if we only want to enqueue this packet without informing FW */
1066 if (!notify_fw) {
1067 list_add_tail(&p_curp->list_entry, &p_rx->posting_descq);
1068 goto out;
1069 }
1070
1071out_notify:
1072 qed_ll2_post_rx_buffer_notify_fw(p_hwfn, p_rx, p_curp);
1073out:
1074 spin_unlock_irqrestore(&p_rx->lock, flags);
1075 return rc;
1076}
1077
1078static void qed_ll2_prepare_tx_packet_set(struct qed_hwfn *p_hwfn,
1079 struct qed_ll2_tx_queue *p_tx,
1080 struct qed_ll2_tx_packet *p_curp,
1081 u8 num_of_bds,
1082 dma_addr_t first_frag,
1083 u16 first_frag_len, void *p_cookie,
1084 u8 notify_fw)
1085{
1086 list_del(&p_curp->list_entry);
1087 p_curp->cookie = p_cookie;
1088 p_curp->bd_used = num_of_bds;
1089 p_curp->notify_fw = notify_fw;
1090 p_tx->cur_send_packet = p_curp;
1091 p_tx->cur_send_frag_num = 0;
1092
1093 p_curp->bds_set[p_tx->cur_send_frag_num].tx_frag = first_frag;
1094 p_curp->bds_set[p_tx->cur_send_frag_num].frag_len = first_frag_len;
1095 p_tx->cur_send_frag_num++;
1096}
1097
1098static void qed_ll2_prepare_tx_packet_set_bd(struct qed_hwfn *p_hwfn,
1099 struct qed_ll2_info *p_ll2,
1100 struct qed_ll2_tx_packet *p_curp,
1101 u8 num_of_bds,
1102 enum core_tx_dest tx_dest,
1103 u16 vlan,
1104 u8 bd_flags,
1105 u16 l4_hdr_offset_w,
Ram Amraniabd49672016-10-01 22:00:01 +03001106 enum core_roce_flavor_type type,
Yuval Mintz0a7fb112016-10-01 21:59:55 +03001107 dma_addr_t first_frag,
1108 u16 first_frag_len)
1109{
1110 struct qed_chain *p_tx_chain = &p_ll2->tx_queue.txq_chain;
1111 u16 prod_idx = qed_chain_get_prod_idx(p_tx_chain);
1112 struct core_tx_bd *start_bd = NULL;
1113 u16 frag_idx;
1114
1115 start_bd = (struct core_tx_bd *)qed_chain_produce(p_tx_chain);
1116 start_bd->nw_vlan_or_lb_echo = cpu_to_le16(vlan);
1117 SET_FIELD(start_bd->bitfield1, CORE_TX_BD_L4_HDR_OFFSET_W,
1118 cpu_to_le16(l4_hdr_offset_w));
1119 SET_FIELD(start_bd->bitfield1, CORE_TX_BD_TX_DST, tx_dest);
1120 start_bd->bd_flags.as_bitfield = bd_flags;
1121 start_bd->bd_flags.as_bitfield |= CORE_TX_BD_FLAGS_START_BD_MASK <<
1122 CORE_TX_BD_FLAGS_START_BD_SHIFT;
1123 SET_FIELD(start_bd->bitfield0, CORE_TX_BD_NBDS, num_of_bds);
1124 DMA_REGPAIR_LE(start_bd->addr, first_frag);
1125 start_bd->nbytes = cpu_to_le16(first_frag_len);
1126
Ram Amraniabd49672016-10-01 22:00:01 +03001127 SET_FIELD(start_bd->bd_flags.as_bitfield, CORE_TX_BD_FLAGS_ROCE_FLAV,
1128 type);
1129
Yuval Mintz0a7fb112016-10-01 21:59:55 +03001130 DP_VERBOSE(p_hwfn,
1131 (NETIF_MSG_TX_QUEUED | QED_MSG_LL2),
1132 "LL2 [q 0x%02x cid 0x%08x type 0x%08x] Tx Producer at [0x%04x] - set with a %04x bytes %02x BDs buffer at %08x:%08x\n",
1133 p_ll2->queue_id,
1134 p_ll2->cid,
1135 p_ll2->conn_type,
1136 prod_idx,
1137 first_frag_len,
1138 num_of_bds,
1139 le32_to_cpu(start_bd->addr.hi),
1140 le32_to_cpu(start_bd->addr.lo));
1141
1142 if (p_ll2->tx_queue.cur_send_frag_num == num_of_bds)
1143 return;
1144
1145 /* Need to provide the packet with additional BDs for frags */
1146 for (frag_idx = p_ll2->tx_queue.cur_send_frag_num;
1147 frag_idx < num_of_bds; frag_idx++) {
1148 struct core_tx_bd **p_bd = &p_curp->bds_set[frag_idx].txq_bd;
1149
1150 *p_bd = (struct core_tx_bd *)qed_chain_produce(p_tx_chain);
1151 (*p_bd)->bd_flags.as_bitfield = 0;
1152 (*p_bd)->bitfield1 = 0;
1153 (*p_bd)->bitfield0 = 0;
1154 p_curp->bds_set[frag_idx].tx_frag = 0;
1155 p_curp->bds_set[frag_idx].frag_len = 0;
1156 }
1157}
1158
1159/* This should be called while the Txq spinlock is being held */
1160static void qed_ll2_tx_packet_notify(struct qed_hwfn *p_hwfn,
1161 struct qed_ll2_info *p_ll2_conn)
1162{
1163 bool b_notify = p_ll2_conn->tx_queue.cur_send_packet->notify_fw;
1164 struct qed_ll2_tx_queue *p_tx = &p_ll2_conn->tx_queue;
1165 struct qed_ll2_tx_packet *p_pkt = NULL;
1166 struct core_db_data db_msg = { 0, 0, 0 };
1167 u16 bd_prod;
1168
1169 /* If there are missing BDs, don't do anything now */
1170 if (p_ll2_conn->tx_queue.cur_send_frag_num !=
1171 p_ll2_conn->tx_queue.cur_send_packet->bd_used)
1172 return;
1173
1174 /* Push the current packet to the list and clean after it */
1175 list_add_tail(&p_ll2_conn->tx_queue.cur_send_packet->list_entry,
1176 &p_ll2_conn->tx_queue.sending_descq);
1177 p_ll2_conn->tx_queue.cur_send_packet = NULL;
1178 p_ll2_conn->tx_queue.cur_send_frag_num = 0;
1179
1180 /* Notify FW of packet only if requested to */
1181 if (!b_notify)
1182 return;
1183
1184 bd_prod = qed_chain_get_prod_idx(&p_ll2_conn->tx_queue.txq_chain);
1185
1186 while (!list_empty(&p_tx->sending_descq)) {
1187 p_pkt = list_first_entry(&p_tx->sending_descq,
1188 struct qed_ll2_tx_packet, list_entry);
1189 if (!p_pkt)
1190 break;
1191
1192 list_del(&p_pkt->list_entry);
1193 list_add_tail(&p_pkt->list_entry, &p_tx->active_descq);
1194 }
1195
1196 SET_FIELD(db_msg.params, CORE_DB_DATA_DEST, DB_DEST_XCM);
1197 SET_FIELD(db_msg.params, CORE_DB_DATA_AGG_CMD, DB_AGG_CMD_SET);
1198 SET_FIELD(db_msg.params, CORE_DB_DATA_AGG_VAL_SEL,
1199 DQ_XCM_CORE_TX_BD_PROD_CMD);
1200 db_msg.agg_flags = DQ_XCM_CORE_DQ_CF_CMD;
1201 db_msg.spq_prod = cpu_to_le16(bd_prod);
1202
1203 /* Make sure the BDs data is updated before ringing the doorbell */
1204 wmb();
1205
1206 DIRECT_REG_WR(p_tx->doorbell_addr, *((u32 *)&db_msg));
1207
1208 DP_VERBOSE(p_hwfn,
1209 (NETIF_MSG_TX_QUEUED | QED_MSG_LL2),
1210 "LL2 [q 0x%02x cid 0x%08x type 0x%08x] Doorbelled [producer 0x%04x]\n",
1211 p_ll2_conn->queue_id,
1212 p_ll2_conn->cid, p_ll2_conn->conn_type, db_msg.spq_prod);
1213}
1214
1215int qed_ll2_prepare_tx_packet(struct qed_hwfn *p_hwfn,
1216 u8 connection_handle,
1217 u8 num_of_bds,
1218 u16 vlan,
1219 u8 bd_flags,
1220 u16 l4_hdr_offset_w,
Ram Amraniabd49672016-10-01 22:00:01 +03001221 enum qed_ll2_roce_flavor_type qed_roce_flavor,
Yuval Mintz0a7fb112016-10-01 21:59:55 +03001222 dma_addr_t first_frag,
1223 u16 first_frag_len, void *cookie, u8 notify_fw)
1224{
1225 struct qed_ll2_tx_packet *p_curp = NULL;
1226 struct qed_ll2_info *p_ll2_conn = NULL;
Ram Amraniabd49672016-10-01 22:00:01 +03001227 enum core_roce_flavor_type roce_flavor;
Yuval Mintz0a7fb112016-10-01 21:59:55 +03001228 struct qed_ll2_tx_queue *p_tx;
1229 struct qed_chain *p_tx_chain;
1230 unsigned long flags;
1231 int rc = 0;
1232
1233 p_ll2_conn = qed_ll2_handle_sanity(p_hwfn, connection_handle);
1234 if (!p_ll2_conn)
1235 return -EINVAL;
1236 p_tx = &p_ll2_conn->tx_queue;
1237 p_tx_chain = &p_tx->txq_chain;
1238
1239 if (num_of_bds > CORE_LL2_TX_MAX_BDS_PER_PACKET)
1240 return -EIO;
1241
1242 spin_lock_irqsave(&p_tx->lock, flags);
1243 if (p_tx->cur_send_packet) {
1244 rc = -EEXIST;
1245 goto out;
1246 }
1247
1248 /* Get entry, but only if we have tx elements for it */
1249 if (!list_empty(&p_tx->free_descq))
1250 p_curp = list_first_entry(&p_tx->free_descq,
1251 struct qed_ll2_tx_packet, list_entry);
1252 if (p_curp && qed_chain_get_elem_left(p_tx_chain) < num_of_bds)
1253 p_curp = NULL;
1254
1255 if (!p_curp) {
1256 rc = -EBUSY;
1257 goto out;
1258 }
1259
Ram Amraniabd49672016-10-01 22:00:01 +03001260 if (qed_roce_flavor == QED_LL2_ROCE) {
1261 roce_flavor = CORE_ROCE;
1262 } else if (qed_roce_flavor == QED_LL2_RROCE) {
1263 roce_flavor = CORE_RROCE;
1264 } else {
1265 rc = -EINVAL;
1266 goto out;
1267 }
1268
Yuval Mintz0a7fb112016-10-01 21:59:55 +03001269 /* Prepare packet and BD, and perhaps send a doorbell to FW */
1270 qed_ll2_prepare_tx_packet_set(p_hwfn, p_tx, p_curp,
1271 num_of_bds, first_frag,
1272 first_frag_len, cookie, notify_fw);
1273 qed_ll2_prepare_tx_packet_set_bd(p_hwfn, p_ll2_conn, p_curp,
1274 num_of_bds, CORE_TX_DEST_NW,
1275 vlan, bd_flags, l4_hdr_offset_w,
Ram Amraniabd49672016-10-01 22:00:01 +03001276 roce_flavor,
Yuval Mintz0a7fb112016-10-01 21:59:55 +03001277 first_frag, first_frag_len);
1278
1279 qed_ll2_tx_packet_notify(p_hwfn, p_ll2_conn);
1280
1281out:
1282 spin_unlock_irqrestore(&p_tx->lock, flags);
1283 return rc;
1284}
1285
1286int qed_ll2_set_fragment_of_tx_packet(struct qed_hwfn *p_hwfn,
1287 u8 connection_handle,
1288 dma_addr_t addr, u16 nbytes)
1289{
1290 struct qed_ll2_tx_packet *p_cur_send_packet = NULL;
1291 struct qed_ll2_info *p_ll2_conn = NULL;
1292 u16 cur_send_frag_num = 0;
1293 struct core_tx_bd *p_bd;
1294 unsigned long flags;
1295
1296 p_ll2_conn = qed_ll2_handle_sanity(p_hwfn, connection_handle);
1297 if (!p_ll2_conn)
1298 return -EINVAL;
1299
1300 if (!p_ll2_conn->tx_queue.cur_send_packet)
1301 return -EINVAL;
1302
1303 p_cur_send_packet = p_ll2_conn->tx_queue.cur_send_packet;
1304 cur_send_frag_num = p_ll2_conn->tx_queue.cur_send_frag_num;
1305
1306 if (cur_send_frag_num >= p_cur_send_packet->bd_used)
1307 return -EINVAL;
1308
1309 /* Fill the BD information, and possibly notify FW */
1310 p_bd = p_cur_send_packet->bds_set[cur_send_frag_num].txq_bd;
1311 DMA_REGPAIR_LE(p_bd->addr, addr);
1312 p_bd->nbytes = cpu_to_le16(nbytes);
1313 p_cur_send_packet->bds_set[cur_send_frag_num].tx_frag = addr;
1314 p_cur_send_packet->bds_set[cur_send_frag_num].frag_len = nbytes;
1315
1316 p_ll2_conn->tx_queue.cur_send_frag_num++;
1317
1318 spin_lock_irqsave(&p_ll2_conn->tx_queue.lock, flags);
1319 qed_ll2_tx_packet_notify(p_hwfn, p_ll2_conn);
1320 spin_unlock_irqrestore(&p_ll2_conn->tx_queue.lock, flags);
1321
1322 return 0;
1323}
1324
1325int qed_ll2_terminate_connection(struct qed_hwfn *p_hwfn, u8 connection_handle)
1326{
1327 struct qed_ll2_info *p_ll2_conn = NULL;
1328 int rc = -EINVAL;
1329
1330 p_ll2_conn = qed_ll2_handle_sanity_lock(p_hwfn, connection_handle);
1331 if (!p_ll2_conn)
1332 return -EINVAL;
1333
1334 /* Stop Tx & Rx of connection, if needed */
1335 if (QED_LL2_TX_REGISTERED(p_ll2_conn)) {
1336 rc = qed_sp_ll2_tx_queue_stop(p_hwfn, p_ll2_conn);
1337 if (rc)
1338 return rc;
1339 qed_ll2_txq_flush(p_hwfn, connection_handle);
1340 }
1341
1342 if (QED_LL2_RX_REGISTERED(p_ll2_conn)) {
1343 rc = qed_sp_ll2_rx_queue_stop(p_hwfn, p_ll2_conn);
1344 if (rc)
1345 return rc;
1346 qed_ll2_rxq_flush(p_hwfn, connection_handle);
1347 }
1348
1349 return rc;
1350}
1351
1352void qed_ll2_release_connection(struct qed_hwfn *p_hwfn, u8 connection_handle)
1353{
1354 struct qed_ll2_info *p_ll2_conn = NULL;
1355
1356 p_ll2_conn = qed_ll2_handle_sanity(p_hwfn, connection_handle);
1357 if (!p_ll2_conn)
1358 return;
1359
1360 if (QED_LL2_RX_REGISTERED(p_ll2_conn)) {
1361 p_ll2_conn->rx_queue.b_cb_registred = false;
1362 qed_int_unregister_cb(p_hwfn, p_ll2_conn->rx_queue.rx_sb_index);
1363 }
1364
1365 if (QED_LL2_TX_REGISTERED(p_ll2_conn)) {
1366 p_ll2_conn->tx_queue.b_cb_registred = false;
1367 qed_int_unregister_cb(p_hwfn, p_ll2_conn->tx_queue.tx_sb_index);
1368 }
1369
1370 kfree(p_ll2_conn->tx_queue.descq_array);
1371 qed_chain_free(p_hwfn->cdev, &p_ll2_conn->tx_queue.txq_chain);
1372
1373 kfree(p_ll2_conn->rx_queue.descq_array);
1374 qed_chain_free(p_hwfn->cdev, &p_ll2_conn->rx_queue.rxq_chain);
1375 qed_chain_free(p_hwfn->cdev, &p_ll2_conn->rx_queue.rcq_chain);
1376
1377 qed_cxt_release_cid(p_hwfn, p_ll2_conn->cid);
1378
1379 mutex_lock(&p_ll2_conn->mutex);
1380 p_ll2_conn->b_active = false;
1381 mutex_unlock(&p_ll2_conn->mutex);
1382}
1383
1384struct qed_ll2_info *qed_ll2_alloc(struct qed_hwfn *p_hwfn)
1385{
1386 struct qed_ll2_info *p_ll2_connections;
1387 u8 i;
1388
1389 /* Allocate LL2's set struct */
1390 p_ll2_connections = kcalloc(QED_MAX_NUM_OF_LL2_CONNECTIONS,
1391 sizeof(struct qed_ll2_info), GFP_KERNEL);
1392 if (!p_ll2_connections) {
1393 DP_NOTICE(p_hwfn, "Failed to allocate `struct qed_ll2'\n");
1394 return NULL;
1395 }
1396
1397 for (i = 0; i < QED_MAX_NUM_OF_LL2_CONNECTIONS; i++)
1398 p_ll2_connections[i].my_id = i;
1399
1400 return p_ll2_connections;
1401}
1402
1403void qed_ll2_setup(struct qed_hwfn *p_hwfn,
1404 struct qed_ll2_info *p_ll2_connections)
1405{
1406 int i;
1407
1408 for (i = 0; i < QED_MAX_NUM_OF_LL2_CONNECTIONS; i++)
1409 mutex_init(&p_ll2_connections[i].mutex);
1410}
1411
1412void qed_ll2_free(struct qed_hwfn *p_hwfn,
1413 struct qed_ll2_info *p_ll2_connections)
1414{
1415 kfree(p_ll2_connections);
1416}
1417
1418static void _qed_ll2_get_tstats(struct qed_hwfn *p_hwfn,
1419 struct qed_ptt *p_ptt,
1420 struct qed_ll2_info *p_ll2_conn,
1421 struct qed_ll2_stats *p_stats)
1422{
1423 struct core_ll2_tstorm_per_queue_stat tstats;
1424 u8 qid = p_ll2_conn->queue_id;
1425 u32 tstats_addr;
1426
1427 memset(&tstats, 0, sizeof(tstats));
1428 tstats_addr = BAR0_MAP_REG_TSDM_RAM +
1429 CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(qid);
1430 qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, sizeof(tstats));
1431
1432 p_stats->packet_too_big_discard =
1433 HILO_64_REGPAIR(tstats.packet_too_big_discard);
1434 p_stats->no_buff_discard = HILO_64_REGPAIR(tstats.no_buff_discard);
1435}
1436
1437static void _qed_ll2_get_ustats(struct qed_hwfn *p_hwfn,
1438 struct qed_ptt *p_ptt,
1439 struct qed_ll2_info *p_ll2_conn,
1440 struct qed_ll2_stats *p_stats)
1441{
1442 struct core_ll2_ustorm_per_queue_stat ustats;
1443 u8 qid = p_ll2_conn->queue_id;
1444 u32 ustats_addr;
1445
1446 memset(&ustats, 0, sizeof(ustats));
1447 ustats_addr = BAR0_MAP_REG_USDM_RAM +
1448 CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(qid);
1449 qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, sizeof(ustats));
1450
1451 p_stats->rcv_ucast_bytes = HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
1452 p_stats->rcv_mcast_bytes = HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
1453 p_stats->rcv_bcast_bytes = HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
1454 p_stats->rcv_ucast_pkts = HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
1455 p_stats->rcv_mcast_pkts = HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
1456 p_stats->rcv_bcast_pkts = HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
1457}
1458
1459static void _qed_ll2_get_pstats(struct qed_hwfn *p_hwfn,
1460 struct qed_ptt *p_ptt,
1461 struct qed_ll2_info *p_ll2_conn,
1462 struct qed_ll2_stats *p_stats)
1463{
1464 struct core_ll2_pstorm_per_queue_stat pstats;
1465 u8 stats_id = p_ll2_conn->tx_stats_id;
1466 u32 pstats_addr;
1467
1468 memset(&pstats, 0, sizeof(pstats));
1469 pstats_addr = BAR0_MAP_REG_PSDM_RAM +
1470 CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(stats_id);
1471 qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, sizeof(pstats));
1472
1473 p_stats->sent_ucast_bytes = HILO_64_REGPAIR(pstats.sent_ucast_bytes);
1474 p_stats->sent_mcast_bytes = HILO_64_REGPAIR(pstats.sent_mcast_bytes);
1475 p_stats->sent_bcast_bytes = HILO_64_REGPAIR(pstats.sent_bcast_bytes);
1476 p_stats->sent_ucast_pkts = HILO_64_REGPAIR(pstats.sent_ucast_pkts);
1477 p_stats->sent_mcast_pkts = HILO_64_REGPAIR(pstats.sent_mcast_pkts);
1478 p_stats->sent_bcast_pkts = HILO_64_REGPAIR(pstats.sent_bcast_pkts);
1479}
1480
1481int qed_ll2_get_stats(struct qed_hwfn *p_hwfn,
1482 u8 connection_handle, struct qed_ll2_stats *p_stats)
1483{
1484 struct qed_ll2_info *p_ll2_conn = NULL;
1485 struct qed_ptt *p_ptt;
1486
1487 memset(p_stats, 0, sizeof(*p_stats));
1488
1489 if ((connection_handle >= QED_MAX_NUM_OF_LL2_CONNECTIONS) ||
1490 !p_hwfn->p_ll2_info)
1491 return -EINVAL;
1492
1493 p_ll2_conn = &p_hwfn->p_ll2_info[connection_handle];
1494
1495 p_ptt = qed_ptt_acquire(p_hwfn);
1496 if (!p_ptt) {
1497 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1498 return -EINVAL;
1499 }
1500
1501 _qed_ll2_get_tstats(p_hwfn, p_ptt, p_ll2_conn, p_stats);
1502 _qed_ll2_get_ustats(p_hwfn, p_ptt, p_ll2_conn, p_stats);
1503 if (p_ll2_conn->tx_stats_en)
1504 _qed_ll2_get_pstats(p_hwfn, p_ptt, p_ll2_conn, p_stats);
1505
1506 qed_ptt_release(p_hwfn, p_ptt);
1507 return 0;
1508}
1509
1510static void qed_ll2_register_cb_ops(struct qed_dev *cdev,
1511 const struct qed_ll2_cb_ops *ops,
1512 void *cookie)
1513{
1514 cdev->ll2->cbs = ops;
1515 cdev->ll2->cb_cookie = cookie;
1516}
1517
1518static int qed_ll2_start(struct qed_dev *cdev, struct qed_ll2_params *params)
1519{
1520 struct qed_ll2_info ll2_info;
Wei Yongjun88a24282016-10-10 14:08:28 +00001521 struct qed_ll2_buffer *buffer, *tmp_buffer;
Yuval Mintz0a7fb112016-10-01 21:59:55 +03001522 enum qed_ll2_conn_type conn_type;
1523 struct qed_ptt *p_ptt;
1524 int rc, i;
1525
1526 /* Initialize LL2 locks & lists */
1527 INIT_LIST_HEAD(&cdev->ll2->list);
1528 spin_lock_init(&cdev->ll2->lock);
1529 cdev->ll2->rx_size = NET_SKB_PAD + ETH_HLEN +
1530 L1_CACHE_BYTES + params->mtu;
1531 cdev->ll2->frags_mapped = params->frags_mapped;
1532
1533 /*Allocate memory for LL2 */
1534 DP_INFO(cdev, "Allocating LL2 buffers of size %08x bytes\n",
1535 cdev->ll2->rx_size);
1536 for (i = 0; i < QED_LL2_RX_SIZE; i++) {
1537 buffer = kzalloc(sizeof(*buffer), GFP_KERNEL);
1538 if (!buffer) {
1539 DP_INFO(cdev, "Failed to allocate LL2 buffers\n");
1540 goto fail;
1541 }
1542
1543 rc = qed_ll2_alloc_buffer(cdev, (u8 **)&buffer->data,
1544 &buffer->phys_addr);
1545 if (rc) {
1546 kfree(buffer);
1547 goto fail;
1548 }
1549
1550 list_add_tail(&buffer->list, &cdev->ll2->list);
1551 }
1552
1553 switch (QED_LEADING_HWFN(cdev)->hw_info.personality) {
1554 case QED_PCI_ISCSI:
1555 conn_type = QED_LL2_TYPE_ISCSI;
1556 break;
1557 case QED_PCI_ETH_ROCE:
1558 conn_type = QED_LL2_TYPE_ROCE;
1559 break;
1560 default:
1561 conn_type = QED_LL2_TYPE_TEST;
1562 }
1563
1564 /* Prepare the temporary ll2 information */
1565 memset(&ll2_info, 0, sizeof(ll2_info));
1566 ll2_info.conn_type = conn_type;
1567 ll2_info.mtu = params->mtu;
1568 ll2_info.rx_drop_ttl0_flg = params->drop_ttl0_packets;
1569 ll2_info.rx_vlan_removal_en = params->rx_vlan_stripping;
1570 ll2_info.tx_tc = 0;
1571 ll2_info.tx_dest = CORE_TX_DEST_NW;
Ram Amraniabd49672016-10-01 22:00:01 +03001572 ll2_info.gsi_enable = 1;
Yuval Mintz0a7fb112016-10-01 21:59:55 +03001573
1574 rc = qed_ll2_acquire_connection(QED_LEADING_HWFN(cdev), &ll2_info,
1575 QED_LL2_RX_SIZE, QED_LL2_TX_SIZE,
1576 &cdev->ll2->handle);
1577 if (rc) {
1578 DP_INFO(cdev, "Failed to acquire LL2 connection\n");
1579 goto fail;
1580 }
1581
1582 rc = qed_ll2_establish_connection(QED_LEADING_HWFN(cdev),
1583 cdev->ll2->handle);
1584 if (rc) {
1585 DP_INFO(cdev, "Failed to establish LL2 connection\n");
1586 goto release_fail;
1587 }
1588
1589 /* Post all Rx buffers to FW */
1590 spin_lock_bh(&cdev->ll2->lock);
Wei Yongjun88a24282016-10-10 14:08:28 +00001591 list_for_each_entry_safe(buffer, tmp_buffer, &cdev->ll2->list, list) {
Yuval Mintz0a7fb112016-10-01 21:59:55 +03001592 rc = qed_ll2_post_rx_buffer(QED_LEADING_HWFN(cdev),
1593 cdev->ll2->handle,
1594 buffer->phys_addr, 0, buffer, 1);
1595 if (rc) {
1596 DP_INFO(cdev,
1597 "Failed to post an Rx buffer; Deleting it\n");
1598 dma_unmap_single(&cdev->pdev->dev, buffer->phys_addr,
1599 cdev->ll2->rx_size, DMA_FROM_DEVICE);
1600 kfree(buffer->data);
1601 list_del(&buffer->list);
1602 kfree(buffer);
1603 } else {
1604 cdev->ll2->rx_cnt++;
1605 }
1606 }
1607 spin_unlock_bh(&cdev->ll2->lock);
1608
1609 if (!cdev->ll2->rx_cnt) {
1610 DP_INFO(cdev, "Failed passing even a single Rx buffer\n");
1611 goto release_terminate;
1612 }
1613
1614 if (!is_valid_ether_addr(params->ll2_mac_address)) {
1615 DP_INFO(cdev, "Invalid Ethernet address\n");
1616 goto release_terminate;
1617 }
1618
1619 p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
1620 if (!p_ptt) {
1621 DP_INFO(cdev, "Failed to acquire PTT\n");
1622 goto release_terminate;
1623 }
1624
1625 rc = qed_llh_add_mac_filter(QED_LEADING_HWFN(cdev), p_ptt,
1626 params->ll2_mac_address);
1627 qed_ptt_release(QED_LEADING_HWFN(cdev), p_ptt);
1628 if (rc) {
1629 DP_ERR(cdev, "Failed to allocate LLH filter\n");
1630 goto release_terminate_all;
1631 }
1632
1633 ether_addr_copy(cdev->ll2_mac_address, params->ll2_mac_address);
1634
1635 return 0;
1636
1637release_terminate_all:
1638
1639release_terminate:
1640 qed_ll2_terminate_connection(QED_LEADING_HWFN(cdev), cdev->ll2->handle);
1641release_fail:
1642 qed_ll2_release_connection(QED_LEADING_HWFN(cdev), cdev->ll2->handle);
1643fail:
1644 qed_ll2_kill_buffers(cdev);
1645 cdev->ll2->handle = QED_LL2_UNUSED_HANDLE;
1646 return -EINVAL;
1647}
1648
1649static int qed_ll2_stop(struct qed_dev *cdev)
1650{
1651 struct qed_ptt *p_ptt;
1652 int rc;
1653
1654 if (cdev->ll2->handle == QED_LL2_UNUSED_HANDLE)
1655 return 0;
1656
1657 p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
1658 if (!p_ptt) {
1659 DP_INFO(cdev, "Failed to acquire PTT\n");
1660 goto fail;
1661 }
1662
1663 qed_llh_remove_mac_filter(QED_LEADING_HWFN(cdev), p_ptt,
1664 cdev->ll2_mac_address);
1665 qed_ptt_release(QED_LEADING_HWFN(cdev), p_ptt);
1666 eth_zero_addr(cdev->ll2_mac_address);
1667
1668 rc = qed_ll2_terminate_connection(QED_LEADING_HWFN(cdev),
1669 cdev->ll2->handle);
1670 if (rc)
1671 DP_INFO(cdev, "Failed to terminate LL2 connection\n");
1672
1673 qed_ll2_kill_buffers(cdev);
1674
1675 qed_ll2_release_connection(QED_LEADING_HWFN(cdev), cdev->ll2->handle);
1676 cdev->ll2->handle = QED_LL2_UNUSED_HANDLE;
1677
1678 return rc;
1679fail:
1680 return -EINVAL;
1681}
1682
1683static int qed_ll2_start_xmit(struct qed_dev *cdev, struct sk_buff *skb)
1684{
1685 const skb_frag_t *frag;
1686 int rc = -EINVAL, i;
1687 dma_addr_t mapping;
1688 u16 vlan = 0;
1689 u8 flags = 0;
1690
1691 if (unlikely(skb->ip_summed != CHECKSUM_NONE)) {
1692 DP_INFO(cdev, "Cannot transmit a checksumed packet\n");
1693 return -EINVAL;
1694 }
1695
1696 if (1 + skb_shinfo(skb)->nr_frags > CORE_LL2_TX_MAX_BDS_PER_PACKET) {
1697 DP_ERR(cdev, "Cannot transmit a packet with %d fragments\n",
1698 1 + skb_shinfo(skb)->nr_frags);
1699 return -EINVAL;
1700 }
1701
1702 mapping = dma_map_single(&cdev->pdev->dev, skb->data,
1703 skb->len, DMA_TO_DEVICE);
1704 if (unlikely(dma_mapping_error(&cdev->pdev->dev, mapping))) {
1705 DP_NOTICE(cdev, "SKB mapping failed\n");
1706 return -EINVAL;
1707 }
1708
1709 /* Request HW to calculate IP csum */
1710 if (!((vlan_get_protocol(skb) == htons(ETH_P_IPV6)) &&
1711 ipv6_hdr(skb)->nexthdr == NEXTHDR_IPV6))
1712 flags |= BIT(CORE_TX_BD_FLAGS_IP_CSUM_SHIFT);
1713
1714 if (skb_vlan_tag_present(skb)) {
1715 vlan = skb_vlan_tag_get(skb);
1716 flags |= BIT(CORE_TX_BD_FLAGS_VLAN_INSERTION_SHIFT);
1717 }
1718
1719 rc = qed_ll2_prepare_tx_packet(QED_LEADING_HWFN(cdev),
1720 cdev->ll2->handle,
1721 1 + skb_shinfo(skb)->nr_frags,
Ram Amraniabd49672016-10-01 22:00:01 +03001722 vlan, flags, 0, 0 /* RoCE FLAVOR */,
1723 mapping, skb->len, skb, 1);
Yuval Mintz0a7fb112016-10-01 21:59:55 +03001724 if (rc)
1725 goto err;
1726
1727 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1728 frag = &skb_shinfo(skb)->frags[i];
1729 if (!cdev->ll2->frags_mapped) {
1730 mapping = skb_frag_dma_map(&cdev->pdev->dev, frag, 0,
1731 skb_frag_size(frag),
1732 DMA_TO_DEVICE);
1733
1734 if (unlikely(dma_mapping_error(&cdev->pdev->dev,
1735 mapping))) {
1736 DP_NOTICE(cdev,
1737 "Unable to map frag - dropping packet\n");
1738 goto err;
1739 }
1740 } else {
1741 mapping = page_to_phys(skb_frag_page(frag)) |
1742 frag->page_offset;
1743 }
1744
1745 rc = qed_ll2_set_fragment_of_tx_packet(QED_LEADING_HWFN(cdev),
1746 cdev->ll2->handle,
1747 mapping,
1748 skb_frag_size(frag));
1749
1750 /* if failed not much to do here, partial packet has been posted
1751 * we can't free memory, will need to wait for completion.
1752 */
1753 if (rc)
1754 goto err2;
1755 }
1756
1757 return 0;
1758
1759err:
1760 dma_unmap_single(&cdev->pdev->dev, mapping, skb->len, DMA_TO_DEVICE);
1761
1762err2:
1763 return rc;
1764}
1765
1766static int qed_ll2_stats(struct qed_dev *cdev, struct qed_ll2_stats *stats)
1767{
1768 if (!cdev->ll2)
1769 return -EINVAL;
1770
1771 return qed_ll2_get_stats(QED_LEADING_HWFN(cdev),
1772 cdev->ll2->handle, stats);
1773}
1774
1775const struct qed_ll2_ops qed_ll2_ops_pass = {
1776 .start = &qed_ll2_start,
1777 .stop = &qed_ll2_stop,
1778 .start_xmit = &qed_ll2_start_xmit,
1779 .register_cb_ops = &qed_ll2_register_cb_ops,
1780 .get_stats = &qed_ll2_stats,
1781};
1782
1783int qed_ll2_alloc_if(struct qed_dev *cdev)
1784{
1785 cdev->ll2 = kzalloc(sizeof(*cdev->ll2), GFP_KERNEL);
1786 return cdev->ll2 ? 0 : -ENOMEM;
1787}
1788
1789void qed_ll2_dealloc_if(struct qed_dev *cdev)
1790{
1791 kfree(cdev->ll2);
1792 cdev->ll2 = NULL;
1793}