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gerrit-public.fairphone.software / kernel / msm-5.4 / 0189efb8f4f830b9ac7a7c56c0c6e260859e950d / . / drivers / net / ethernet / qlogic / qed / qed_roce.h
blob: 691413176734dc452531db084930fe90630c4411 [file] [log] [blame]
Ram Amrani51ff1722016-10-01 21:59:57 +0300[diff] [blame]1/* QLogic qed NIC Driver
2 * Copyright (c) 2015-2016 QLogic Corporation
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32#ifndef _QED_ROCE_H
33#define _QED_ROCE_H
34#include <linux/types.h>
35#include <linux/bitops.h>
36#include <linux/kernel.h>
37#include <linux/list.h>
38#include <linux/slab.h>
39#include <linux/spinlock.h>
40#include <linux/qed/qed_if.h>
41#include <linux/qed/qed_roce_if.h>
42#include "qed.h"
43#include "qed_dev_api.h"
44#include "qed_hsi.h"
Ram Amraniabd49672016-10-01 22:00:01 +0300[diff] [blame]45#include "qed_ll2.h"
Ram Amrani51ff1722016-10-01 21:59:57 +0300[diff] [blame]46
47#define QED_RDMA_MAX_FMR (RDMA_MAX_TIDS)
48#define QED_RDMA_MAX_P_KEY (1)
49#define QED_RDMA_MAX_WQE (0x7FFF)
50#define QED_RDMA_MAX_SRQ_WQE_ELEM (0x7FFF)
51#define QED_RDMA_PAGE_SIZE_CAPS (0xFFFFF000)
52#define QED_RDMA_ACK_DELAY (15)
53#define QED_RDMA_MAX_MR_SIZE (0x10000000000ULL)
54#define QED_RDMA_MAX_CQS (RDMA_MAX_CQS)
55#define QED_RDMA_MAX_MRS (RDMA_MAX_TIDS)
56/* Add 1 for header element */
57#define QED_RDMA_MAX_SRQ_ELEM_PER_WQE (RDMA_MAX_SGE_PER_RQ_WQE + 1)
58#define QED_RDMA_MAX_SGE_PER_SRQ_WQE (RDMA_MAX_SGE_PER_RQ_WQE)
59#define QED_RDMA_SRQ_WQE_ELEM_SIZE (16)
60#define QED_RDMA_MAX_SRQS (32 * 1024)
61
62#define QED_RDMA_MAX_CQE_32_BIT (0x7FFFFFFF - 1)
63#define QED_RDMA_MAX_CQE_16_BIT (0x7FFF - 1)
64
65enum qed_rdma_toggle_bit {
66 QED_RDMA_TOGGLE_BIT_CLEAR = 0,
67 QED_RDMA_TOGGLE_BIT_SET = 1
68};
69
70struct qed_bmap {
71 unsigned long *bitmap;
72 u32 max_count;
73};
74
75struct qed_rdma_info {
76 /* spin lock to protect bitmaps */
77 spinlock_t lock;
78
79 struct qed_bmap cq_map;
80 struct qed_bmap pd_map;
81 struct qed_bmap tid_map;
82 struct qed_bmap qp_map;
83 struct qed_bmap srq_map;
84 struct qed_bmap cid_map;
85 struct qed_bmap dpi_map;
86 struct qed_bmap toggle_bits;
87 struct qed_rdma_events events;
88 struct qed_rdma_device *dev;
89 struct qed_rdma_port *port;
90 u32 last_tid;
91 u8 num_cnqs;
92 u32 num_qps;
93 u32 num_mrs;
94 u16 queue_zone_base;
95 enum protocol_type proto;
96};
97
Ram Amranic295f862016-10-01 21:59:58 +0300[diff] [blame]98struct qed_rdma_resize_cq_in_params {
99 u16 icid;
100 u32 cq_size;
101 bool pbl_two_level;
102 u64 pbl_ptr;
103 u16 pbl_num_pages;
104 u8 pbl_page_size_log;
105};
106
107struct qed_rdma_resize_cq_out_params {
108 u32 prod;
109 u32 cons;
110};
111
112struct qed_rdma_resize_cnq_in_params {
113 u32 cnq_id;
114 u32 pbl_page_size_log;
115 u64 pbl_ptr;
116};
117
Ram Amranif1093942016-10-01 21:59:59 +0300[diff] [blame]118struct qed_rdma_qp {
119 struct regpair qp_handle;
120 struct regpair qp_handle_async;
121 u32 qpid;
122 u16 icid;
123 enum qed_roce_qp_state cur_state;
124 bool use_srq;
125 bool signal_all;
126 bool fmr_and_reserved_lkey;
127
128 bool incoming_rdma_read_en;
129 bool incoming_rdma_write_en;
130 bool incoming_atomic_en;
131 bool e2e_flow_control_en;
132
133 u16 pd;
134 u16 pkey;
135 u32 dest_qp;
136 u16 mtu;
137 u16 srq_id;
138 u8 traffic_class_tos;
139 u8 hop_limit_ttl;
140 u16 dpi;
141 u32 flow_label;
142 bool lb_indication;
143 u16 vlan_id;
144 u32 ack_timeout;
145 u8 retry_cnt;
146 u8 rnr_retry_cnt;
147 u8 min_rnr_nak_timer;
148 bool sqd_async;
149 union qed_gid sgid;
150 union qed_gid dgid;
151 enum roce_mode roce_mode;
152 u16 udp_src_port;
153 u8 stats_queue;
154
155 /* requeseter */
156 u8 max_rd_atomic_req;
157 u32 sq_psn;
158 u16 sq_cq_id;
159 u16 sq_num_pages;
160 dma_addr_t sq_pbl_ptr;
161 void *orq;
162 dma_addr_t orq_phys_addr;
163 u8 orq_num_pages;
164 bool req_offloaded;
165
166 /* responder */
167 u8 max_rd_atomic_resp;
168 u32 rq_psn;
169 u16 rq_cq_id;
170 u16 rq_num_pages;
171 dma_addr_t rq_pbl_ptr;
172 void *irq;
173 dma_addr_t irq_phys_addr;
174 u8 irq_num_pages;
175 bool resp_offloaded;
176
177 u8 remote_mac_addr[6];
178 u8 local_mac_addr[6];
179
180 void *shared_queue;
181 dma_addr_t shared_queue_phys_addr;
182};
183
Yuval Mintz0189efb2016-10-13 22:57:02 +0300[diff] [blame^]184#if IS_ENABLED(CONFIG_QED_RDMA)
185void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
Ram Amrani51ff1722016-10-01 21:59:57 +0300[diff] [blame]186void qed_async_roce_event(struct qed_hwfn *p_hwfn,
187 struct event_ring_entry *p_eqe);
Yuval Mintz0189efb2016-10-13 22:57:02 +0300[diff] [blame^]188void qed_ll2b_complete_tx_gsi_packet(struct qed_hwfn *p_hwfn,
189 u8 connection_handle,
190 void *cookie,
191 dma_addr_t first_frag_addr,
192 bool b_last_fragment, bool b_last_packet);
193void qed_ll2b_release_tx_gsi_packet(struct qed_hwfn *p_hwfn,
194 u8 connection_handle,
195 void *cookie,
196 dma_addr_t first_frag_addr,
197 bool b_last_fragment, bool b_last_packet);
198void qed_ll2b_complete_rx_gsi_packet(struct qed_hwfn *p_hwfn,
199 u8 connection_handle,
200 void *cookie,
201 dma_addr_t rx_buf_addr,
202 u16 data_length,
203 u8 data_length_error,
204 u16 parse_flags,
205 u16 vlan,
206 u32 src_mac_addr_hi,
207 u16 src_mac_addr_lo, bool b_last_packet);
Ram Amrani51ff1722016-10-01 21:59:57 +0300[diff] [blame]208#else
Yuval Mintz0189efb2016-10-13 22:57:02 +0300[diff] [blame^]209static inline void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) {}
210static inline void qed_async_roce_event(struct qed_hwfn *p_hwfn, struct event_ring_entry *p_eqe) {}
211static inline void qed_ll2b_complete_tx_gsi_packet(struct qed_hwfn *p_hwfn,
212 u8 connection_handle,
213 void *cookie,
214 dma_addr_t first_frag_addr,
215 bool b_last_fragment,
216 bool b_last_packet) {}
217static inline void qed_ll2b_release_tx_gsi_packet(struct qed_hwfn *p_hwfn,
218 u8 connection_handle,
219 void *cookie,
220 dma_addr_t first_frag_addr,
221 bool b_last_fragment,
222 bool b_last_packet) {}
223static inline void qed_ll2b_complete_rx_gsi_packet(struct qed_hwfn *p_hwfn,
224 u8 connection_handle,
225 void *cookie,
226 dma_addr_t rx_buf_addr,
227 u16 data_length,
228 u8 data_length_error,
229 u16 parse_flags,
230 u16 vlan,
231 u32 src_mac_addr_hi,
232 u16 src_mac_addr_lo,
233 bool b_last_packet) {}
Ram Amrani51ff1722016-10-01 21:59:57 +0300[diff] [blame]234#endif
235#endif