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gerrit-public.fairphone.software / kernel / msm-5.4 / 01b6722fdf65a91d588338e5a1964d57fa2dd590 / . / drivers / clk / bcm / clk-iproc.h
blob: ff7bfad48c136dbac1dfa040fac05187868f5248 [file] [log] [blame]
Ray Jui5fe225c2015-05-05 11:13:19 -0700[diff] [blame]1/*
2 * Copyright (C) 2014 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _CLK_IPROC_H
15#define _CLK_IPROC_H
16
17#include <linux/kernel.h>
18#include <linux/list.h>
19#include <linux/spinlock.h>
20#include <linux/slab.h>
21#include <linux/device.h>
22#include <linux/of.h>
23#include <linux/clk-provider.h>
24
25#define IPROC_CLK_NAME_LEN 25
26#define IPROC_CLK_INVALID_OFFSET 0xffffffff
27#define bit_mask(width) ((1 << (width)) - 1)
28
29/* clocks that should not be disabled at runtime */
30#define IPROC_CLK_AON BIT(0)
31
32/* PLL that requires gating through ASIU */
33#define IPROC_CLK_PLL_ASIU BIT(1)
34
35/* PLL that has fractional part of the NDIV */
36#define IPROC_CLK_PLL_HAS_NDIV_FRAC BIT(2)
37
38/*
39 * Some of the iProc PLL/clocks may have an ASIC bug that requires read back
40 * of the same register following the write to flush the write transaction into
41 * the intended register
42 */
43#define IPROC_CLK_NEEDS_READ_BACK BIT(3)
44
45/*
46 * Some PLLs require the PLL SW override bit to be set before changes can be
47 * applied to the PLL
48 */
49#define IPROC_CLK_PLL_NEEDS_SW_CFG BIT(4)
50
51/*
Jon Mason01b67222015-10-15 15:48:26 -0400[diff] [blame^]52 * Some PLLs use a different way to control clock power, via the PWRDWN bit in
53 * the PLL control register
54 */
55#define IPROC_CLK_EMBED_PWRCTRL BIT(5)
56
57/*
Ray Jui5fe225c2015-05-05 11:13:19 -0700[diff] [blame]58 * Parameters for VCO frequency configuration
59 *
60 * VCO frequency =
61 * ((ndiv_int + ndiv_frac / 2^20) * (ref freqeuncy / pdiv)
62 */
63struct iproc_pll_vco_param {
64 unsigned long rate;
65 unsigned int ndiv_int;
66 unsigned int ndiv_frac;
67 unsigned int pdiv;
68};
69
70struct iproc_clk_reg_op {
71 unsigned int offset;
72 unsigned int shift;
73 unsigned int width;
74};
75
76/*
77 * Clock gating control at the top ASIU level
78 */
79struct iproc_asiu_gate {
80 unsigned int offset;
81 unsigned int en_shift;
82};
83
84/*
85 * Control of powering on/off of a PLL
86 *
87 * Before powering off a PLL, input isolation (ISO) needs to be enabled
88 */
89struct iproc_pll_aon_pwr_ctrl {
90 unsigned int offset;
91 unsigned int pwr_width;
92 unsigned int pwr_shift;
93 unsigned int iso_shift;
94};
95
96/*
97 * Control of the PLL reset, with Ki, Kp, and Ka parameters
98 */
99struct iproc_pll_reset_ctrl {
100 unsigned int offset;
101 unsigned int reset_shift;
102 unsigned int p_reset_shift;
103 unsigned int ki_shift;
104 unsigned int ki_width;
105 unsigned int kp_shift;
106 unsigned int kp_width;
107 unsigned int ka_shift;
108 unsigned int ka_width;
109};
110
111/*
112 * To enable SW control of the PLL
113 */
114struct iproc_pll_sw_ctrl {
115 unsigned int offset;
116 unsigned int shift;
117};
118
119struct iproc_pll_vco_ctrl {
120 unsigned int u_offset;
121 unsigned int l_offset;
122};
123
124/*
125 * Main PLL control parameters
126 */
127struct iproc_pll_ctrl {
128 unsigned long flags;
129 struct iproc_pll_aon_pwr_ctrl aon;
130 struct iproc_asiu_gate asiu;
131 struct iproc_pll_reset_ctrl reset;
132 struct iproc_pll_sw_ctrl sw_ctrl;
133 struct iproc_clk_reg_op ndiv_int;
134 struct iproc_clk_reg_op ndiv_frac;
135 struct iproc_clk_reg_op pdiv;
136 struct iproc_pll_vco_ctrl vco_ctrl;
137 struct iproc_clk_reg_op status;
138};
139
140/*
141 * Controls enabling/disabling a PLL derived clock
142 */
143struct iproc_clk_enable_ctrl {
144 unsigned int offset;
145 unsigned int enable_shift;
146 unsigned int hold_shift;
147 unsigned int bypass_shift;
148};
149
150/*
151 * Main clock control parameters for clocks derived from the PLLs
152 */
153struct iproc_clk_ctrl {
154 unsigned int channel;
155 unsigned long flags;
156 struct iproc_clk_enable_ctrl enable;
157 struct iproc_clk_reg_op mdiv;
158};
159
160/*
161 * Divisor of the ASIU clocks
162 */
163struct iproc_asiu_div {
164 unsigned int offset;
165 unsigned int en_shift;
166 unsigned int high_shift;
167 unsigned int high_width;
168 unsigned int low_shift;
169 unsigned int low_width;
170};
171
172void __init iproc_armpll_setup(struct device_node *node);
173void __init iproc_pll_clk_setup(struct device_node *node,
174 const struct iproc_pll_ctrl *pll_ctrl,
175 const struct iproc_pll_vco_param *vco,
176 unsigned int num_vco_entries,
177 const struct iproc_clk_ctrl *clk_ctrl,
178 unsigned int num_clks);
179void __init iproc_asiu_setup(struct device_node *node,
180 const struct iproc_asiu_div *div,
181 const struct iproc_asiu_gate *gate,
182 unsigned int num_clks);
183
184#endif /* _CLK_IPROC_H */