blob: 8ead864f354a7737d53ada5132ea5d36769ae234 [file] [log] [blame]
Jeeja KPd8c2dab2015-07-09 15:20:09 +05301/*
2 * skl.c - Implementation of ASoC Intel SKL HD Audio driver
3 *
4 * Copyright (C) 2014-2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 *
7 * Derived mostly from Intel HDA driver with following copyrights:
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
22 */
23
24#include <linux/module.h>
25#include <linux/pci.h>
26#include <linux/pm_runtime.h>
27#include <linux/platform_device.h>
28#include <sound/pcm.h>
Vinod Koulcc18c5f2015-11-05 21:34:13 +053029#include "../common/sst-acpi.h"
Jeeja KPd8c2dab2015-07-09 15:20:09 +053030#include "skl.h"
31
32/*
33 * initialize the PCI registers
34 */
35static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg,
36 unsigned char mask, unsigned char val)
37{
38 unsigned char data;
39
40 pci_read_config_byte(pci, reg, &data);
41 data &= ~mask;
42 data |= (val & mask);
43 pci_write_config_byte(pci, reg, data);
44}
45
46static void skl_init_pci(struct skl *skl)
47{
48 struct hdac_ext_bus *ebus = &skl->ebus;
49
50 /*
51 * Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
52 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
53 * Ensuring these bits are 0 clears playback static on some HD Audio
54 * codecs.
55 * The PCI register TCSEL is defined in the Intel manuals.
56 */
57 dev_dbg(ebus_to_hbus(ebus)->dev, "Clearing TCSEL\n");
58 skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0);
59}
60
61/* called from IRQ */
62static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr)
63{
64 snd_pcm_period_elapsed(hstr->substream);
65}
66
67static irqreturn_t skl_interrupt(int irq, void *dev_id)
68{
69 struct hdac_ext_bus *ebus = dev_id;
70 struct hdac_bus *bus = ebus_to_hbus(ebus);
71 u32 status;
72
73 if (!pm_runtime_active(bus->dev))
74 return IRQ_NONE;
75
76 spin_lock(&bus->reg_lock);
77
78 status = snd_hdac_chip_readl(bus, INTSTS);
79 if (status == 0 || status == 0xffffffff) {
80 spin_unlock(&bus->reg_lock);
81 return IRQ_NONE;
82 }
83
84 /* clear rirb int */
85 status = snd_hdac_chip_readb(bus, RIRBSTS);
86 if (status & RIRB_INT_MASK) {
87 if (status & RIRB_INT_RESPONSE)
88 snd_hdac_bus_update_rirb(bus);
89 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
90 }
91
92 spin_unlock(&bus->reg_lock);
93
94 return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED;
95}
96
97static irqreturn_t skl_threaded_handler(int irq, void *dev_id)
98{
99 struct hdac_ext_bus *ebus = dev_id;
100 struct hdac_bus *bus = ebus_to_hbus(ebus);
101 u32 status;
102
103 status = snd_hdac_chip_readl(bus, INTSTS);
104
105 snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update);
106
107 return IRQ_HANDLED;
108}
109
110static int skl_acquire_irq(struct hdac_ext_bus *ebus, int do_disconnect)
111{
112 struct skl *skl = ebus_to_skl(ebus);
113 struct hdac_bus *bus = ebus_to_hbus(ebus);
114 int ret;
115
116 ret = request_threaded_irq(skl->pci->irq, skl_interrupt,
117 skl_threaded_handler,
118 IRQF_SHARED,
119 KBUILD_MODNAME, ebus);
120 if (ret) {
121 dev_err(bus->dev,
122 "unable to grab IRQ %d, disabling device\n",
123 skl->pci->irq);
124 return ret;
125 }
126
127 bus->irq = skl->pci->irq;
128 pci_intx(skl->pci, 1);
129
130 return 0;
131}
132
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530133#ifdef CONFIG_PM
Jeeja KP61722f42015-10-27 09:23:00 +0900134static int _skl_suspend(struct hdac_ext_bus *ebus)
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530135{
Jeeja KP2a29b202015-10-07 11:31:58 +0100136 struct skl *skl = ebus_to_skl(ebus);
Jeeja KP61722f42015-10-27 09:23:00 +0900137 struct hdac_bus *bus = ebus_to_hbus(ebus);
Jeeja KP2a29b202015-10-07 11:31:58 +0100138 int ret;
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530139
Jeeja KP01bb84b2015-10-09 09:01:51 +0100140 snd_hdac_ext_bus_link_power_down_all(ebus);
141
Jeeja KP2a29b202015-10-07 11:31:58 +0100142 ret = skl_suspend_dsp(skl);
143 if (ret < 0)
144 return ret;
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530145
146 snd_hdac_bus_stop_chip(bus);
147 snd_hdac_bus_enter_link_reset(bus);
148
149 return 0;
150}
151
Jeeja KP61722f42015-10-27 09:23:00 +0900152static int _skl_resume(struct hdac_ext_bus *ebus)
153{
154 struct skl *skl = ebus_to_skl(ebus);
155 struct hdac_bus *bus = ebus_to_hbus(ebus);
156
157 skl_init_pci(skl);
158 snd_hdac_bus_init_chip(bus, true);
159
160 return skl_resume_dsp(skl);
161}
162#endif
163
164#ifdef CONFIG_PM_SLEEP
165/*
166 * power management
167 */
168static int skl_suspend(struct device *dev)
169{
170 struct pci_dev *pci = to_pci_dev(dev);
171 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
172
173 return _skl_suspend(ebus);
174}
175
176static int skl_resume(struct device *dev)
177{
178 struct pci_dev *pci = to_pci_dev(dev);
179 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
180
181 return _skl_resume(ebus);
182}
183#endif /* CONFIG_PM_SLEEP */
184
185#ifdef CONFIG_PM
186static int skl_runtime_suspend(struct device *dev)
187{
188 struct pci_dev *pci = to_pci_dev(dev);
189 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
190 struct hdac_bus *bus = ebus_to_hbus(ebus);
191
192 dev_dbg(bus->dev, "in %s\n", __func__);
193
194 /* enable controller wake up event */
195 snd_hdac_chip_updatew(bus, WAKEEN, 0, STATESTS_INT_MASK);
196
197 return _skl_suspend(ebus);
198}
199
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530200static int skl_runtime_resume(struct device *dev)
201{
202 struct pci_dev *pci = to_pci_dev(dev);
203 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
204 struct hdac_bus *bus = ebus_to_hbus(ebus);
Jeeja KP2a29b202015-10-07 11:31:58 +0100205 struct skl *skl = ebus_to_skl(ebus);
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530206 int status;
207
208 dev_dbg(bus->dev, "in %s\n", __func__);
209
210 /* Read STATESTS before controller reset */
211 status = snd_hdac_chip_readw(bus, STATESTS);
212
Jeeja KP2a29b202015-10-07 11:31:58 +0100213 skl_init_pci(skl);
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530214 snd_hdac_bus_init_chip(bus, true);
215 /* disable controller Wake Up event */
216 snd_hdac_chip_updatew(bus, WAKEEN, STATESTS_INT_MASK, 0);
217
Jeeja KP61722f42015-10-27 09:23:00 +0900218 return _skl_resume(ebus);
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530219}
220#endif /* CONFIG_PM */
221
222static const struct dev_pm_ops skl_pm = {
223 SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume)
224 SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL)
225};
226
227/*
228 * destructor
229 */
230static int skl_free(struct hdac_ext_bus *ebus)
231{
232 struct skl *skl = ebus_to_skl(ebus);
233 struct hdac_bus *bus = ebus_to_hbus(ebus);
234
235 skl->init_failed = 1; /* to be sure */
236
237 snd_hdac_ext_stop_streams(ebus);
238
239 if (bus->irq >= 0)
240 free_irq(bus->irq, (void *)bus);
241 if (bus->remap_addr)
242 iounmap(bus->remap_addr);
243
244 snd_hdac_bus_free_stream_pages(bus);
245 snd_hdac_stream_free_all(ebus);
246 snd_hdac_link_free_all(ebus);
247 pci_release_regions(skl->pci);
248 pci_disable_device(skl->pci);
249
250 snd_hdac_ext_bus_exit(ebus);
251
252 return 0;
253}
254
Vinod Koulcc18c5f2015-11-05 21:34:13 +0530255static int skl_machine_device_register(struct skl *skl, void *driver_data)
256{
257 struct hdac_bus *bus = ebus_to_hbus(&skl->ebus);
258 struct platform_device *pdev;
259 struct sst_acpi_mach *mach = driver_data;
260 int ret;
261
262 mach = sst_acpi_find_machine(mach);
263 if (mach == NULL) {
264 dev_err(bus->dev, "No matching machine driver found\n");
265 return -ENODEV;
266 }
Vinod Koulaecf6fd2015-11-05 21:34:15 +0530267 skl->fw_name = mach->fw_filename;
Vinod Koulcc18c5f2015-11-05 21:34:13 +0530268
269 pdev = platform_device_alloc(mach->drv_name, -1);
270 if (pdev == NULL) {
271 dev_err(bus->dev, "platform device alloc failed\n");
272 return -EIO;
273 }
274
275 ret = platform_device_add(pdev);
276 if (ret) {
277 dev_err(bus->dev, "failed to add machine device\n");
278 platform_device_put(pdev);
279 return -EIO;
280 }
281 skl->i2s_dev = pdev;
282
283 return 0;
284}
285
286static void skl_machine_device_unregister(struct skl *skl)
287{
288 if (skl->i2s_dev)
289 platform_device_unregister(skl->i2s_dev);
290}
291
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530292static int skl_dmic_device_register(struct skl *skl)
293{
294 struct hdac_bus *bus = ebus_to_hbus(&skl->ebus);
295 struct platform_device *pdev;
296 int ret;
297
298 /* SKL has one dmic port, so allocate dmic device for this */
299 pdev = platform_device_alloc("dmic-codec", -1);
300 if (!pdev) {
301 dev_err(bus->dev, "failed to allocate dmic device\n");
302 return -ENOMEM;
303 }
304
305 ret = platform_device_add(pdev);
306 if (ret) {
307 dev_err(bus->dev, "failed to add dmic device: %d\n", ret);
308 platform_device_put(pdev);
309 return ret;
310 }
311 skl->dmic_dev = pdev;
312
313 return 0;
314}
315
316static void skl_dmic_device_unregister(struct skl *skl)
317{
318 if (skl->dmic_dev)
319 platform_device_unregister(skl->dmic_dev);
320}
321
322/*
323 * Probe the given codec address
324 */
325static int probe_codec(struct hdac_ext_bus *ebus, int addr)
326{
327 struct hdac_bus *bus = ebus_to_hbus(ebus);
328 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
329 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
330 unsigned int res;
331
332 mutex_lock(&bus->cmd_mutex);
333 snd_hdac_bus_send_cmd(bus, cmd);
334 snd_hdac_bus_get_response(bus, addr, &res);
335 mutex_unlock(&bus->cmd_mutex);
336 if (res == -1)
337 return -EIO;
338 dev_dbg(bus->dev, "codec #%d probed OK\n", addr);
339
340 return snd_hdac_ext_bus_device_init(ebus, addr);
341}
342
343/* Codec initialization */
344static int skl_codec_create(struct hdac_ext_bus *ebus)
345{
346 struct hdac_bus *bus = ebus_to_hbus(ebus);
347 int c, max_slots;
348
349 max_slots = HDA_MAX_CODECS;
350
351 /* First try to probe all given codec slots */
352 for (c = 0; c < max_slots; c++) {
353 if ((bus->codec_mask & (1 << c))) {
354 if (probe_codec(ebus, c) < 0) {
355 /*
356 * Some BIOSen give you wrong codec addresses
357 * that don't exist
358 */
359 dev_warn(bus->dev,
360 "Codec #%d probe error; disabling it...\n", c);
361 bus->codec_mask &= ~(1 << c);
362 /*
363 * More badly, accessing to a non-existing
364 * codec often screws up the controller bus,
365 * and disturbs the further communications.
366 * Thus if an error occurs during probing,
367 * better to reset the controller bus to get
368 * back to the sanity state.
369 */
370 snd_hdac_bus_stop_chip(bus);
371 snd_hdac_bus_init_chip(bus, true);
372 }
373 }
374 }
375
376 return 0;
377}
378
379static const struct hdac_bus_ops bus_core_ops = {
380 .command = snd_hdac_bus_send_cmd,
381 .get_response = snd_hdac_bus_get_response,
382};
383
384/*
385 * constructor
386 */
387static int skl_create(struct pci_dev *pci,
388 const struct hdac_io_ops *io_ops,
389 struct skl **rskl)
390{
391 struct skl *skl;
392 struct hdac_ext_bus *ebus;
393
394 int err;
395
396 *rskl = NULL;
397
398 err = pci_enable_device(pci);
399 if (err < 0)
400 return err;
401
402 skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL);
403 if (!skl) {
404 pci_disable_device(pci);
405 return -ENOMEM;
406 }
407 ebus = &skl->ebus;
408 snd_hdac_ext_bus_init(ebus, &pci->dev, &bus_core_ops, io_ops);
409 ebus->bus.use_posbuf = 1;
410 skl->pci = pci;
411
412 ebus->bus.bdl_pos_adj = 0;
413
414 *rskl = skl;
415
416 return 0;
417}
418
419static int skl_first_init(struct hdac_ext_bus *ebus)
420{
421 struct skl *skl = ebus_to_skl(ebus);
422 struct hdac_bus *bus = ebus_to_hbus(ebus);
423 struct pci_dev *pci = skl->pci;
424 int err;
425 unsigned short gcap;
426 int cp_streams, pb_streams, start_idx;
427
428 err = pci_request_regions(pci, "Skylake HD audio");
429 if (err < 0)
430 return err;
431
432 bus->addr = pci_resource_start(pci, 0);
433 bus->remap_addr = pci_ioremap_bar(pci, 0);
434 if (bus->remap_addr == NULL) {
435 dev_err(bus->dev, "ioremap error\n");
436 return -ENXIO;
437 }
438
Jeeja KP05057002015-07-09 15:20:11 +0530439 snd_hdac_ext_bus_parse_capabilities(ebus);
440
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530441 if (skl_acquire_irq(ebus, 0) < 0)
442 return -EBUSY;
443
444 pci_set_master(pci);
445 synchronize_irq(bus->irq);
446
447 gcap = snd_hdac_chip_readw(bus, GCAP);
448 dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap);
449
450 /* allow 64bit DMA address if supported by H/W */
451 if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) {
452 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64));
453 } else {
454 dma_set_mask(bus->dev, DMA_BIT_MASK(32));
455 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32));
456 }
457
458 /* read number of streams from GCAP register */
459 cp_streams = (gcap >> 8) & 0x0f;
460 pb_streams = (gcap >> 12) & 0x0f;
461
462 if (!pb_streams && !cp_streams)
463 return -EIO;
464
465 ebus->num_streams = cp_streams + pb_streams;
466
467 /* initialize streams */
468 snd_hdac_ext_stream_init_all
469 (ebus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE);
470 start_idx = cp_streams;
471 snd_hdac_ext_stream_init_all
472 (ebus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK);
473
474 err = snd_hdac_bus_alloc_stream_pages(bus);
475 if (err < 0)
476 return err;
477
478 /* initialize chip */
479 skl_init_pci(skl);
480
481 snd_hdac_bus_init_chip(bus, true);
482
483 /* codec detection */
484 if (!bus->codec_mask) {
Jeeja KP029890c2015-10-27 09:22:47 +0900485 dev_info(bus->dev, "no hda codecs found!\n");
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530486 }
487
488 return 0;
489}
490
491static int skl_probe(struct pci_dev *pci,
492 const struct pci_device_id *pci_id)
493{
494 struct skl *skl;
495 struct hdac_ext_bus *ebus = NULL;
496 struct hdac_bus *bus = NULL;
497 int err;
498
499 /* we use ext core ops, so provide NULL for ops here */
500 err = skl_create(pci, NULL, &skl);
501 if (err < 0)
502 return err;
503
504 ebus = &skl->ebus;
505 bus = ebus_to_hbus(ebus);
506
507 err = skl_first_init(ebus);
508 if (err < 0)
509 goto out_free;
510
Jeeja KP87b2bdf2015-10-07 11:31:59 +0100511 skl->nhlt = skl_nhlt_init(bus->dev);
512
513 if (skl->nhlt == NULL)
514 goto out_free;
515
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530516 pci_set_drvdata(skl->pci, ebus);
517
Jeeja KP05057002015-07-09 15:20:11 +0530518 /* check if dsp is there */
519 if (ebus->ppcap) {
Vinod Koulcc18c5f2015-11-05 21:34:13 +0530520 err = skl_machine_device_register(skl,
521 (void *)pci_id->driver_data);
522 if (err < 0)
523 goto out_free;
524
Jeeja KP2a29b202015-10-07 11:31:58 +0100525 err = skl_init_dsp(skl);
526 if (err < 0) {
527 dev_dbg(bus->dev, "error failed to register dsp\n");
Vinod Koulcc18c5f2015-11-05 21:34:13 +0530528 goto out_mach_free;
Jeeja KP2a29b202015-10-07 11:31:58 +0100529 }
Jeeja KP05057002015-07-09 15:20:11 +0530530 }
Jeeja KP05057002015-07-09 15:20:11 +0530531 if (ebus->mlcap)
532 snd_hdac_ext_bus_get_ml_capabilities(ebus);
533
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530534 /* create device for soc dmic */
535 err = skl_dmic_device_register(skl);
536 if (err < 0)
Jeeja KP2a29b202015-10-07 11:31:58 +0100537 goto out_dsp_free;
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530538
539 /* register platform dai and controls */
540 err = skl_platform_register(bus->dev);
541 if (err < 0)
542 goto out_dmic_free;
543
544 /* create codec instances */
545 err = skl_codec_create(ebus);
546 if (err < 0)
547 goto out_unregister;
548
549 /*configure PM */
550 pm_runtime_set_autosuspend_delay(bus->dev, SKL_SUSPEND_DELAY);
551 pm_runtime_use_autosuspend(bus->dev);
552 pm_runtime_put_noidle(bus->dev);
553 pm_runtime_allow(bus->dev);
554
555 return 0;
556
557out_unregister:
558 skl_platform_unregister(bus->dev);
559out_dmic_free:
560 skl_dmic_device_unregister(skl);
Jeeja KP2a29b202015-10-07 11:31:58 +0100561out_dsp_free:
562 skl_free_dsp(skl);
Vinod Koulcc18c5f2015-11-05 21:34:13 +0530563out_mach_free:
564 skl_machine_device_unregister(skl);
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530565out_free:
566 skl->init_failed = 1;
567 skl_free(ebus);
568
569 return err;
570}
571
572static void skl_remove(struct pci_dev *pci)
573{
574 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
575 struct skl *skl = ebus_to_skl(ebus);
576
577 if (pci_dev_run_wake(pci))
578 pm_runtime_get_noresume(&pci->dev);
579 pci_dev_put(pci);
580 skl_platform_unregister(&pci->dev);
Jeeja KP2a29b202015-10-07 11:31:58 +0100581 skl_free_dsp(skl);
Vinod Koulcc18c5f2015-11-05 21:34:13 +0530582 skl_machine_device_unregister(skl);
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530583 skl_dmic_device_unregister(skl);
584 skl_free(ebus);
585 dev_set_drvdata(&pci->dev, NULL);
586}
587
Vinod Koulcc18c5f2015-11-05 21:34:13 +0530588static struct sst_acpi_mach sst_skl_devdata[] = {
589 { "INT343A", "skl_alc286s_i2s", "intel/dsp_fw_release.bin", NULL, NULL, NULL },
Fang, Yang A02cc2352015-11-05 22:53:08 +0530590 { "INT343B", "skl_nau88l25_ssm4567_i2s", "intel/dsp_fw_release.bin",
591 NULL, NULL, NULL },
Vinod Koulcc18c5f2015-11-05 21:34:13 +0530592 {}
593};
594
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530595/* PCI IDs */
596static const struct pci_device_id skl_ids[] = {
597 /* Sunrise Point-LP */
Vinod Koulcc18c5f2015-11-05 21:34:13 +0530598 { PCI_DEVICE(0x8086, 0x9d70),
599 .driver_data = (unsigned long)&sst_skl_devdata},
Jeeja KPd8c2dab2015-07-09 15:20:09 +0530600 { 0, }
601};
602MODULE_DEVICE_TABLE(pci, skl_ids);
603
604/* pci_driver definition */
605static struct pci_driver skl_driver = {
606 .name = KBUILD_MODNAME,
607 .id_table = skl_ids,
608 .probe = skl_probe,
609 .remove = skl_remove,
610 .driver = {
611 .pm = &skl_pm,
612 },
613};
614module_pci_driver(skl_driver);
615
616MODULE_LICENSE("GPL v2");
617MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver");