blob: dc977b1c8eab9e6405948948fc942f240b1cfa7c [file] [log] [blame]
Auke Kok9a799d72007-09-15 14:07:45 -07001/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
Don Skidmorea52055e2011-02-23 09:58:39 +00004 Copyright(c) 1999 - 2011 Intel Corporation.
Auke Kok9a799d72007-09-15 14:07:45 -07005
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
Auke Kok9a799d72007-09-15 14:07:45 -070023 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
Stephen Hemminger9c8eb722007-10-29 10:46:24 -070032#include "ixgbe.h"
Auke Kok9a799d72007-09-15 14:07:45 -070033#include "ixgbe_phy.h"
34
35#define IXGBE_82598_MAX_TX_QUEUES 32
36#define IXGBE_82598_MAX_RX_QUEUES 64
37#define IXGBE_82598_RAR_ENTRIES 16
Christopher Leech2c5645c2008-08-26 04:27:02 -070038#define IXGBE_82598_MC_TBL_SIZE 128
39#define IXGBE_82598_VFT_TBL_SIZE 128
Auke Kok9a799d72007-09-15 14:07:45 -070040
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +000041static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
Mallikarjuna R Chilakala21ce8492010-05-13 17:33:41 +000042 ixgbe_link_speed speed,
43 bool autoneg,
44 bool autoneg_wait_to_complete);
Donald Skidmorec4900be2008-11-20 21:11:42 -080045static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
46 u8 *eeprom_data);
Auke Kok9a799d72007-09-15 14:07:45 -070047
Jesse Brandeburgc44ade92008-09-11 19:59:59 -070048/**
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +000049 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
50 * @hw: pointer to the HW structure
51 *
52 * The defaults for 82598 should be in the range of 50us to 50ms,
53 * however the hardware default for these parts is 500us to 1ms which is less
54 * than the 10ms recommended by the pci-e spec. To address this we need to
55 * increase the value to either 10ms to 250ms for capability version 1 config,
56 * or 16ms to 55ms for version 2.
57 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +000058static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +000059{
60 struct ixgbe_adapter *adapter = hw->back;
61 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
62 u16 pcie_devctl2;
63
64 /* only take action if timeout value is defaulted to 0 */
65 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
66 goto out;
67
68 /*
69 * if capababilities version is type 1 we can write the
70 * timeout of 10ms to 250ms through the GCR register
71 */
72 if (!(gcr & IXGBE_GCR_CAP_VER2)) {
73 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms;
74 goto out;
75 }
76
77 /*
78 * for version 2 capabilities we need to write the config space
79 * directly in order to set the completion timeout value for
80 * 16ms to 55ms
81 */
82 pci_read_config_word(adapter->pdev,
83 IXGBE_PCI_DEVICE_CONTROL2, &pcie_devctl2);
84 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;
85 pci_write_config_word(adapter->pdev,
86 IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
87out:
88 /* disable completion timeout resend */
89 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
90 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
91}
92
93/**
Peter P Waskiewicz Jreb7f1392009-02-01 01:18:58 -080094 * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
95 * @hw: pointer to hardware structure
96 *
97 * Read PCIe configuration space, and get the MSI-X vector count from
98 * the capabilities table.
99 **/
Hannes Eder1aef47c2009-02-14 11:38:36 +0000100static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
Peter P Waskiewicz Jreb7f1392009-02-01 01:18:58 -0800101{
102 struct ixgbe_adapter *adapter = hw->back;
103 u16 msix_count;
104 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS,
105 &msix_count);
106 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
107
108 /* MSI-X count is zero-based in HW, so increment to give proper value */
109 msix_count++;
110
111 return msix_count;
112}
113
114/**
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700115 */
Auke Kok9a799d72007-09-15 14:07:45 -0700116static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
117{
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700118 struct ixgbe_mac_info *mac = &hw->mac;
PJ Waskiewicz03cfa202009-03-19 01:23:29 +0000119
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700120 /* Call PHY identify routine to get the phy type */
121 ixgbe_identify_phy_generic(hw);
Auke Kok3957d632007-10-31 15:22:10 -0700122
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000123 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
124 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
125 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
126 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
127 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
128 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
129
130 return 0;
131}
132
133/**
134 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
135 * @hw: pointer to hardware structure
136 *
137 * Initialize any function pointers that were not able to be
138 * set during get_invariants because the PHY/SFP type was
139 * not known. Perform the SFP init if necessary.
140 *
141 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +0000142static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000143{
144 struct ixgbe_mac_info *mac = &hw->mac;
145 struct ixgbe_phy_info *phy = &hw->phy;
146 s32 ret_val = 0;
147 u16 list_offset, data_offset;
148
149 /* Identify the PHY */
150 phy->ops.identify(hw);
151
152 /* Overwrite the link function pointers if copper PHY */
153 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
154 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000155 mac->ops.get_link_capabilities =
Don Skidmorea391f1d2010-11-16 19:27:15 -0800156 &ixgbe_get_copper_link_capabilities_generic;
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000157 }
158
159 switch (hw->phy.type) {
Jesse Brandeburg0befdb32008-10-31 00:46:40 -0700160 case ixgbe_phy_tn:
161 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
162 phy->ops.get_firmware_version =
163 &ixgbe_get_phy_firmware_version_tnx;
164 break;
Donald Skidmorec4900be2008-11-20 21:11:42 -0800165 case ixgbe_phy_nl:
166 phy->ops.reset = &ixgbe_reset_phy_nl;
167
168 /* Call SFP+ identify routine to get the SFP+ module type */
169 ret_val = phy->ops.identify_sfp(hw);
170 if (ret_val != 0)
171 goto out;
172 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
173 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
174 goto out;
175 }
176
177 /* Check to see if SFP+ module is supported */
178 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000179 &list_offset,
180 &data_offset);
Donald Skidmorec4900be2008-11-20 21:11:42 -0800181 if (ret_val != 0) {
182 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
183 goto out;
184 }
185 break;
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700186 default:
187 break;
Auke Kok3957d632007-10-31 15:22:10 -0700188 }
189
Donald Skidmorec4900be2008-11-20 21:11:42 -0800190out:
191 return ret_val;
Auke Kok9a799d72007-09-15 14:07:45 -0700192}
193
194/**
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +0000195 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
196 * @hw: pointer to hardware structure
197 *
198 * Starts the hardware using the generic start_hw function.
199 * Then set pcie completion timeout
200 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +0000201static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +0000202{
203 s32 ret_val = 0;
204
205 ret_val = ixgbe_start_hw_generic(hw);
206
207 /* set the completion timeout for interface */
208 if (ret_val == 0)
209 ixgbe_set_pcie_completion_timeout(hw);
210
211 return ret_val;
212}
213
214/**
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700215 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
Auke Kok9a799d72007-09-15 14:07:45 -0700216 * @hw: pointer to hardware structure
217 * @speed: pointer to link speed
218 * @autoneg: boolean auto-negotiation value
219 *
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700220 * Determines the link capabilities by reading the AUTOC register.
Auke Kok9a799d72007-09-15 14:07:45 -0700221 **/
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700222static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
Peter P Waskiewiczb4617242008-09-11 20:04:46 -0700223 ixgbe_link_speed *speed,
224 bool *autoneg)
Auke Kok9a799d72007-09-15 14:07:45 -0700225{
226 s32 status = 0;
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000227 u32 autoc = 0;
Auke Kok9a799d72007-09-15 14:07:45 -0700228
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800229 /*
230 * Determine link capabilities based on the stored value of AUTOC,
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000231 * which represents EEPROM defaults. If AUTOC value has not been
232 * stored, use the current register value.
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800233 */
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000234 if (hw->mac.orig_link_settings_stored)
235 autoc = hw->mac.orig_autoc;
236 else
237 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
238
239 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
Auke Kok9a799d72007-09-15 14:07:45 -0700240 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
241 *speed = IXGBE_LINK_SPEED_1GB_FULL;
242 *autoneg = false;
243 break;
244
245 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
246 *speed = IXGBE_LINK_SPEED_10GB_FULL;
247 *autoneg = false;
248 break;
249
250 case IXGBE_AUTOC_LMS_1G_AN:
251 *speed = IXGBE_LINK_SPEED_1GB_FULL;
252 *autoneg = true;
253 break;
254
255 case IXGBE_AUTOC_LMS_KX4_AN:
256 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
257 *speed = IXGBE_LINK_SPEED_UNKNOWN;
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000258 if (autoc & IXGBE_AUTOC_KX4_SUPP)
Auke Kok9a799d72007-09-15 14:07:45 -0700259 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000260 if (autoc & IXGBE_AUTOC_KX_SUPP)
Auke Kok9a799d72007-09-15 14:07:45 -0700261 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
262 *autoneg = true;
263 break;
264
265 default:
266 status = IXGBE_ERR_LINK_SETUP;
267 break;
268 }
269
270 return status;
271}
272
273/**
Auke Kok9a799d72007-09-15 14:07:45 -0700274 * ixgbe_get_media_type_82598 - Determines media type
275 * @hw: pointer to hardware structure
276 *
277 * Returns the media type (fiber, copper, backplane)
278 **/
279static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
280{
281 enum ixgbe_media_type media_type;
282
Emil Tantilov037c6d02011-02-25 07:49:39 +0000283 /* Detect if there is a copper PHY attached. */
284 switch (hw->phy.type) {
285 case ixgbe_phy_cu_unknown:
286 case ixgbe_phy_tn:
287 case ixgbe_phy_aq:
288 media_type = ixgbe_media_type_copper;
289 goto out;
290 default:
291 break;
292 }
293
Auke Kok9a799d72007-09-15 14:07:45 -0700294 /* Media type for I82598 is based on device ID */
295 switch (hw->device_id) {
Don Skidmore1e336d02009-01-26 20:57:51 -0800296 case IXGBE_DEV_ID_82598:
Don Skidmore2f21bdd2009-02-01 01:18:23 -0800297 case IXGBE_DEV_ID_82598_BX:
Emil Tantilov037c6d02011-02-25 07:49:39 +0000298 /* Default device ID is mezzanine card KX/KX4 */
Don Skidmore1e336d02009-01-26 20:57:51 -0800299 media_type = ixgbe_media_type_backplane;
300 break;
Auke Kok9a799d72007-09-15 14:07:45 -0700301 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
302 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
Donald Skidmorec4900be2008-11-20 21:11:42 -0800303 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
304 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
Jesse Brandeburgb95f5fc2008-09-11 19:58:59 -0700305 case IXGBE_DEV_ID_82598EB_XF_LR:
Donald Skidmorec4900be2008-11-20 21:11:42 -0800306 case IXGBE_DEV_ID_82598EB_SFP_LOM:
Auke Kok9a799d72007-09-15 14:07:45 -0700307 media_type = ixgbe_media_type_fiber;
308 break;
Peter P Waskiewicz Jr6b1be192009-09-14 07:48:10 +0000309 case IXGBE_DEV_ID_82598EB_CX4:
310 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
311 media_type = ixgbe_media_type_cx4;
312 break;
Jesse Brandeburg0befdb32008-10-31 00:46:40 -0700313 case IXGBE_DEV_ID_82598AT:
Peter P Waskiewicz Jr3845bec2009-07-16 15:50:52 +0000314 case IXGBE_DEV_ID_82598AT2:
Jesse Brandeburg0befdb32008-10-31 00:46:40 -0700315 media_type = ixgbe_media_type_copper;
316 break;
Auke Kok9a799d72007-09-15 14:07:45 -0700317 default:
318 media_type = ixgbe_media_type_unknown;
319 break;
320 }
Emil Tantilov037c6d02011-02-25 07:49:39 +0000321out:
Auke Kok9a799d72007-09-15 14:07:45 -0700322 return media_type;
323}
324
325/**
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800326 * ixgbe_fc_enable_82598 - Enable flow control
327 * @hw: pointer to hardware structure
328 * @packetbuf_num: packet buffer number (0-7)
329 *
330 * Enable flow control according to the current settings.
331 **/
332static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
333{
334 s32 ret_val = 0;
335 u32 fctrl_reg;
336 u32 rmcs_reg;
337 u32 reg;
John Fastabend16b61be2010-11-16 19:26:44 -0800338 u32 rx_pba_size;
Don Skidmorea626e842010-02-11 04:13:49 +0000339 u32 link_speed = 0;
340 bool link_up;
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800341
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +0000342#ifdef CONFIG_DCB
343 if (hw->fc.requested_mode == ixgbe_fc_pfc)
344 goto out;
345
346#endif /* CONFIG_DCB */
Don Skidmorea626e842010-02-11 04:13:49 +0000347 /*
348 * On 82598 having Rx FC on causes resets while doing 1G
349 * so if it's on turn it off once we know link_speed. For
350 * more details see 82598 Specification update.
351 */
352 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
353 if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) {
354 switch (hw->fc.requested_mode) {
355 case ixgbe_fc_full:
356 hw->fc.requested_mode = ixgbe_fc_tx_pause;
357 break;
358 case ixgbe_fc_rx_pause:
359 hw->fc.requested_mode = ixgbe_fc_none;
360 break;
361 default:
362 /* no change */
363 break;
364 }
365 }
366
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +0000367 /* Negotiate the fc mode to use */
368 ret_val = ixgbe_fc_autoneg(hw);
369 if (ret_val)
370 goto out;
371
372 /* Disable any previous flow control settings */
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800373 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
374 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
375
376 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
377 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
378
379 /*
380 * The possible values of fc.current_mode are:
381 * 0: Flow control is completely disabled
382 * 1: Rx flow control is enabled (we can receive pause frames,
383 * but not send pause frames).
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +0000384 * 2: Tx flow control is enabled (we can send pause frames but
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800385 * we do not support receiving pause frames).
386 * 3: Both Rx and Tx flow control (symmetric) are enabled.
387 * other: Invalid.
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +0000388#ifdef CONFIG_DCB
389 * 4: Priority Flow Control is enabled.
390#endif
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800391 */
392 switch (hw->fc.current_mode) {
393 case ixgbe_fc_none:
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +0000394 /*
395 * Flow control is disabled by software override or autoneg.
396 * The code below will actually disable it in the HW.
397 */
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800398 break;
399 case ixgbe_fc_rx_pause:
400 /*
401 * Rx Flow control is enabled and Tx Flow control is
402 * disabled by software override. Since there really
403 * isn't a way to advertise that we are capable of RX
404 * Pause ONLY, we will advertise that we support both
405 * symmetric and asymmetric Rx PAUSE. Later, we will
406 * disable the adapter's ability to send PAUSE frames.
407 */
408 fctrl_reg |= IXGBE_FCTRL_RFCE;
409 break;
410 case ixgbe_fc_tx_pause:
411 /*
412 * Tx Flow control is enabled, and Rx Flow control is
413 * disabled by software override.
414 */
415 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
416 break;
417 case ixgbe_fc_full:
418 /* Flow control (both Rx and Tx) is enabled by SW override. */
419 fctrl_reg |= IXGBE_FCTRL_RFCE;
420 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
421 break;
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +0000422#ifdef CONFIG_DCB
423 case ixgbe_fc_pfc:
424 goto out;
425 break;
426#endif /* CONFIG_DCB */
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800427 default:
428 hw_dbg(hw, "Flow control param set incorrectly\n");
Peter P Waskiewicz Jr539e5f02009-09-30 12:07:38 +0000429 ret_val = IXGBE_ERR_CONFIG;
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800430 goto out;
431 break;
432 }
433
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +0000434 /* Set 802.3x based flow control settings. */
PJ Waskiewicz2132d382009-04-09 22:26:21 +0000435 fctrl_reg |= IXGBE_FCTRL_DPF;
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800436 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
437 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
438
439 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
440 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
John Fastabend16b61be2010-11-16 19:26:44 -0800441 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
442 rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800443
John Fastabend16b61be2010-11-16 19:26:44 -0800444 reg = (rx_pba_size - hw->fc.low_water) << 6;
445 if (hw->fc.send_xon)
446 reg |= IXGBE_FCRTL_XONE;
447 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), reg);
448
449 reg = (rx_pba_size - hw->fc.high_water) << 10;
450 reg |= IXGBE_FCRTH_FCEN;
451
452 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), reg);
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800453 }
454
455 /* Configure pause time (2 TCs per register) */
Peter P Waskiewicz Jr264857b2009-05-17 12:35:16 +0000456 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800457 if ((packetbuf_num & 1) == 0)
458 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
459 else
460 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
461 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
462
463 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
464
465out:
466 return ret_val;
467}
468
469/**
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000470 * ixgbe_start_mac_link_82598 - Configures MAC link settings
Auke Kok9a799d72007-09-15 14:07:45 -0700471 * @hw: pointer to hardware structure
472 *
473 * Configures link settings based on values in the ixgbe_hw struct.
474 * Restarts the link. Performs autonegotiation if needed.
475 **/
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000476static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
477 bool autoneg_wait_to_complete)
Auke Kok9a799d72007-09-15 14:07:45 -0700478{
479 u32 autoc_reg;
480 u32 links_reg;
481 u32 i;
482 s32 status = 0;
483
Auke Kok9a799d72007-09-15 14:07:45 -0700484 /* Restart link */
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800485 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
Auke Kok9a799d72007-09-15 14:07:45 -0700486 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
487 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
488
489 /* Only poll for autoneg to complete if specified to do so */
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000490 if (autoneg_wait_to_complete) {
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800491 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
492 IXGBE_AUTOC_LMS_KX4_AN ||
493 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
494 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
Auke Kok9a799d72007-09-15 14:07:45 -0700495 links_reg = 0; /* Just in case Autoneg time = 0 */
496 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
497 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
498 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
499 break;
500 msleep(100);
501 }
502 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
503 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700504 hw_dbg(hw, "Autonegotiation did not complete.\n");
Auke Kok9a799d72007-09-15 14:07:45 -0700505 }
506 }
507 }
508
Auke Kok9a799d72007-09-15 14:07:45 -0700509 /* Add delay to filter out noises during initial link setup */
510 msleep(50);
511
512 return status;
513}
514
515/**
Mallikarjuna R Chilakala734e9792009-12-15 11:57:20 +0000516 * ixgbe_validate_link_ready - Function looks for phy link
517 * @hw: pointer to hardware structure
518 *
519 * Function indicates success when phy link is available. If phy is not ready
520 * within 5 seconds of MAC indicating link, the function returns error.
521 **/
522static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)
523{
524 u32 timeout;
525 u16 an_reg;
526
527 if (hw->device_id != IXGBE_DEV_ID_82598AT2)
528 return 0;
529
530 for (timeout = 0;
531 timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) {
532 hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg);
533
534 if ((an_reg & MDIO_AN_STAT1_COMPLETE) &&
535 (an_reg & MDIO_STAT1_LSTATUS))
536 break;
537
538 msleep(100);
539 }
540
541 if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) {
542 hw_dbg(hw, "Link was indicated but link is down\n");
543 return IXGBE_ERR_LINK_SETUP;
544 }
545
546 return 0;
547}
548
549/**
Auke Kok9a799d72007-09-15 14:07:45 -0700550 * ixgbe_check_mac_link_82598 - Get link/speed status
551 * @hw: pointer to hardware structure
552 * @speed: pointer to link speed
553 * @link_up: true is link is up, false otherwise
Jesse Brandeburgcf8280e2008-09-11 19:55:32 -0700554 * @link_up_wait_to_complete: bool used to wait for link up or not
Auke Kok9a799d72007-09-15 14:07:45 -0700555 *
556 * Reads the links register to determine if link is up and the current speed
557 **/
Peter P Waskiewiczb4617242008-09-11 20:04:46 -0700558static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
559 ixgbe_link_speed *speed, bool *link_up,
560 bool link_up_wait_to_complete)
Auke Kok9a799d72007-09-15 14:07:45 -0700561{
562 u32 links_reg;
Jesse Brandeburgcf8280e2008-09-11 19:55:32 -0700563 u32 i;
Donald Skidmorec4900be2008-11-20 21:11:42 -0800564 u16 link_reg, adapt_comp_reg;
565
566 /*
567 * SERDES PHY requires us to read link status from register 0xC79F.
568 * Bit 0 set indicates link is up/ready; clear indicates link down.
569 * 0xC00C is read to check that the XAUI lanes are active. Bit 0
570 * clear indicates active; set indicates inactive.
571 */
572 if (hw->phy.type == ixgbe_phy_nl) {
Ben Hutchings6b73e102009-04-29 08:08:58 +0000573 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
574 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
575 hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD,
Donald Skidmorec4900be2008-11-20 21:11:42 -0800576 &adapt_comp_reg);
577 if (link_up_wait_to_complete) {
578 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
579 if ((link_reg & 1) &&
580 ((adapt_comp_reg & 1) == 0)) {
581 *link_up = true;
582 break;
583 } else {
584 *link_up = false;
585 }
586 msleep(100);
587 hw->phy.ops.read_reg(hw, 0xC79F,
Ben Hutchings6b73e102009-04-29 08:08:58 +0000588 MDIO_MMD_PMAPMD,
Donald Skidmorec4900be2008-11-20 21:11:42 -0800589 &link_reg);
590 hw->phy.ops.read_reg(hw, 0xC00C,
Ben Hutchings6b73e102009-04-29 08:08:58 +0000591 MDIO_MMD_PMAPMD,
Donald Skidmorec4900be2008-11-20 21:11:42 -0800592 &adapt_comp_reg);
593 }
594 } else {
595 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
596 *link_up = true;
597 else
598 *link_up = false;
599 }
600
601 if (*link_up == false)
602 goto out;
603 }
Auke Kok9a799d72007-09-15 14:07:45 -0700604
605 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
Jesse Brandeburgcf8280e2008-09-11 19:55:32 -0700606 if (link_up_wait_to_complete) {
607 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
608 if (links_reg & IXGBE_LINKS_UP) {
609 *link_up = true;
610 break;
611 } else {
612 *link_up = false;
613 }
614 msleep(100);
615 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
616 }
617 } else {
618 if (links_reg & IXGBE_LINKS_UP)
619 *link_up = true;
620 else
621 *link_up = false;
622 }
Auke Kok9a799d72007-09-15 14:07:45 -0700623
624 if (links_reg & IXGBE_LINKS_SPEED)
625 *speed = IXGBE_LINK_SPEED_10GB_FULL;
626 else
627 *speed = IXGBE_LINK_SPEED_1GB_FULL;
628
Mallikarjuna R Chilakala734e9792009-12-15 11:57:20 +0000629 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == true) &&
630 (ixgbe_validate_link_ready(hw) != 0))
631 *link_up = false;
632
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +0000633 /* if link is down, zero out the current_mode */
634 if (*link_up == false) {
635 hw->fc.current_mode = ixgbe_fc_none;
636 hw->fc.fc_was_autonegged = false;
637 }
Donald Skidmorec4900be2008-11-20 21:11:42 -0800638out:
Auke Kok9a799d72007-09-15 14:07:45 -0700639 return 0;
640}
641
642/**
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000643 * ixgbe_setup_mac_link_82598 - Set MAC link speed
Auke Kok9a799d72007-09-15 14:07:45 -0700644 * @hw: pointer to hardware structure
645 * @speed: new link speed
646 * @autoneg: true if auto-negotiation enabled
Emil Tantilov037c6d02011-02-25 07:49:39 +0000647 * @autoneg_wait_to_complete: true when waiting for completion is needed
Auke Kok9a799d72007-09-15 14:07:45 -0700648 *
649 * Set the link speed in the AUTOC register and restarts link.
650 **/
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000651static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800652 ixgbe_link_speed speed, bool autoneg,
653 bool autoneg_wait_to_complete)
Auke Kok9a799d72007-09-15 14:07:45 -0700654{
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800655 s32 status = 0;
656 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
657 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
658 u32 autoc = curr_autoc;
659 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
Auke Kok9a799d72007-09-15 14:07:45 -0700660
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800661 /* Check to see if speed passed in is supported. */
662 ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg);
663 speed &= link_capabilities;
664
665 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
Auke Kok9a799d72007-09-15 14:07:45 -0700666 status = IXGBE_ERR_LINK_SETUP;
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800667
668 /* Set KX4/KX support according to speed requested */
669 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
670 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
671 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
672 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
673 autoc |= IXGBE_AUTOC_KX4_SUPP;
674 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
675 autoc |= IXGBE_AUTOC_KX_SUPP;
676 if (autoc != curr_autoc)
677 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
Auke Kok9a799d72007-09-15 14:07:45 -0700678 }
679
680 if (status == 0) {
Auke Kok9a799d72007-09-15 14:07:45 -0700681 /*
682 * Setup and restart the link based on the new values in
683 * ixgbe_hw This will write the AUTOC register based on the new
684 * stored values
685 */
Emil Tantilov037c6d02011-02-25 07:49:39 +0000686 status = ixgbe_start_mac_link_82598(hw,
687 autoneg_wait_to_complete);
Auke Kok9a799d72007-09-15 14:07:45 -0700688 }
689
690 return status;
691}
692
693
694/**
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000695 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
Auke Kok9a799d72007-09-15 14:07:45 -0700696 * @hw: pointer to hardware structure
697 * @speed: new link speed
698 * @autoneg: true if autonegotiation enabled
699 * @autoneg_wait_to_complete: true if waiting is needed to complete
700 *
701 * Sets the link speed in the AUTOC register in the MAC and restarts link.
702 **/
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000703static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
Peter P Waskiewiczb4617242008-09-11 20:04:46 -0700704 ixgbe_link_speed speed,
705 bool autoneg,
706 bool autoneg_wait_to_complete)
Auke Kok9a799d72007-09-15 14:07:45 -0700707{
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700708 s32 status;
Auke Kok9a799d72007-09-15 14:07:45 -0700709
710 /* Setup the PHY according to input speed */
Peter P Waskiewiczb4617242008-09-11 20:04:46 -0700711 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
712 autoneg_wait_to_complete);
Auke Kok3957d632007-10-31 15:22:10 -0700713 /* Set up MAC */
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000714 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
Auke Kok9a799d72007-09-15 14:07:45 -0700715
716 return status;
717}
718
719/**
720 * ixgbe_reset_hw_82598 - Performs hardware reset
721 * @hw: pointer to hardware structure
722 *
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700723 * Resets the hardware by resetting the transmit and receive units, masks and
Auke Kok9a799d72007-09-15 14:07:45 -0700724 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
725 * reset.
726 **/
727static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
728{
729 s32 status = 0;
Don Skidmore8ca783a2009-05-26 20:40:47 -0700730 s32 phy_status = 0;
Auke Kok9a799d72007-09-15 14:07:45 -0700731 u32 ctrl;
732 u32 gheccr;
733 u32 i;
734 u32 autoc;
735 u8 analog_val;
736
737 /* Call adapter stop to disable tx/rx and clear interrupts */
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700738 hw->mac.ops.stop_adapter(hw);
Auke Kok9a799d72007-09-15 14:07:45 -0700739
740 /*
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700741 * Power up the Atlas Tx lanes if they are currently powered down.
742 * Atlas Tx lanes are powered down for MAC loopback tests, but
Auke Kok9a799d72007-09-15 14:07:45 -0700743 * they are not automatically restored on reset.
744 */
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700745 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700746 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700747 /* Enable Tx Atlas so packets can be transmitted again */
748 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
749 &analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700750 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700751 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
752 analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700753
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700754 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
755 &analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700756 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700757 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
758 analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700759
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700760 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
761 &analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700762 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700763 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
764 analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700765
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700766 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
767 &analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700768 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700769 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
770 analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700771 }
772
773 /* Reset PHY */
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000774 if (hw->phy.reset_disable == false) {
775 /* PHY ops must be identified and initialized prior to reset */
776
777 /* Init PHY and function pointers, perform SFP setup */
Don Skidmore8ca783a2009-05-26 20:40:47 -0700778 phy_status = hw->phy.ops.init(hw);
779 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000780 goto reset_hw_out;
Don Skidmore8ca783a2009-05-26 20:40:47 -0700781 else if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
782 goto no_phy_reset;
783
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700784 hw->phy.ops.reset(hw);
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000785 }
Auke Kok9a799d72007-09-15 14:07:45 -0700786
Don Skidmore8ca783a2009-05-26 20:40:47 -0700787no_phy_reset:
Auke Kok9a799d72007-09-15 14:07:45 -0700788 /*
789 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
790 * access and verify no pending requests before reset
791 */
Emil Tantilova4297dc2011-02-14 08:45:13 +0000792 ixgbe_disable_pcie_master(hw);
Auke Kok9a799d72007-09-15 14:07:45 -0700793
Emil Tantilova4297dc2011-02-14 08:45:13 +0000794mac_reset_top:
Auke Kok9a799d72007-09-15 14:07:45 -0700795 /*
796 * Issue global reset to the MAC. This needs to be a SW reset.
797 * If link reset is used, it might reset the MAC when mng is using it
798 */
799 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
800 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
801 IXGBE_WRITE_FLUSH(hw);
802
803 /* Poll for reset bit to self-clear indicating reset is complete */
804 for (i = 0; i < 10; i++) {
805 udelay(1);
806 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
807 if (!(ctrl & IXGBE_CTRL_RST))
808 break;
809 }
810 if (ctrl & IXGBE_CTRL_RST) {
811 status = IXGBE_ERR_RESET_FAILED;
812 hw_dbg(hw, "Reset polling failed to complete.\n");
813 }
814
Emil Tantilova4297dc2011-02-14 08:45:13 +0000815 /*
816 * Double resets are required for recovery from certain error
817 * conditions. Between resets, it is necessary to stall to allow time
818 * for any pending HW events to complete. We use 1usec since that is
819 * what is needed for ixgbe_disable_pcie_master(). The second reset
820 * then clears out any effects of those events.
821 */
822 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
823 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
824 udelay(1);
825 goto mac_reset_top;
826 }
827
Auke Kok9a799d72007-09-15 14:07:45 -0700828 msleep(50);
829
830 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
831 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
832 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
833
834 /*
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800835 * Store the original AUTOC value if it has not been
836 * stored off yet. Otherwise restore the stored original
837 * AUTOC value since the reset operation sets back to deaults.
Auke Kok9a799d72007-09-15 14:07:45 -0700838 */
839 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800840 if (hw->mac.orig_link_settings_stored == false) {
841 hw->mac.orig_autoc = autoc;
842 hw->mac.orig_link_settings_stored = true;
843 } else if (autoc != hw->mac.orig_autoc) {
844 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
Auke Kok9a799d72007-09-15 14:07:45 -0700845 }
846
Emil Tantilov278675d2011-02-19 08:43:49 +0000847 /* Store the permanent mac address */
848 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
849
Waskiewicz Jr, Peter Paca6bee2009-05-17 12:32:48 +0000850 /*
851 * Store MAC address from RAR0, clear receive address registers, and
852 * clear the multicast table
853 */
854 hw->mac.ops.init_rx_addrs(hw);
855
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000856reset_hw_out:
Don Skidmore8ca783a2009-05-26 20:40:47 -0700857 if (phy_status)
858 status = phy_status;
859
Auke Kok9a799d72007-09-15 14:07:45 -0700860 return status;
861}
862
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700863/**
864 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
865 * @hw: pointer to hardware struct
866 * @rar: receive address register index to associate with a VMDq index
867 * @vmdq: VMDq set index
868 **/
Hannes Edere855aac2008-12-26 00:03:59 -0800869static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700870{
871 u32 rar_high;
Emil Tantilovc700f4e2011-02-17 11:34:58 +0000872 u32 rar_entries = hw->mac.num_rar_entries;
873
874 /* Make sure we are using a valid rar index range */
875 if (rar >= rar_entries) {
876 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
877 return IXGBE_ERR_INVALID_ARGUMENT;
878 }
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700879
880 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
881 rar_high &= ~IXGBE_RAH_VIND_MASK;
882 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
883 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
884 return 0;
885}
886
887/**
888 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
889 * @hw: pointer to hardware struct
890 * @rar: receive address register index to associate with a VMDq index
891 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
892 **/
893static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
894{
895 u32 rar_high;
896 u32 rar_entries = hw->mac.num_rar_entries;
897
Emil Tantilovc700f4e2011-02-17 11:34:58 +0000898
899 /* Make sure we are using a valid rar index range */
900 if (rar >= rar_entries) {
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700901 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
Emil Tantilovc700f4e2011-02-17 11:34:58 +0000902 return IXGBE_ERR_INVALID_ARGUMENT;
903 }
904
905 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
906 if (rar_high & IXGBE_RAH_VIND_MASK) {
907 rar_high &= ~IXGBE_RAH_VIND_MASK;
908 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700909 }
910
911 return 0;
912}
913
914/**
915 * ixgbe_set_vfta_82598 - Set VLAN filter table
916 * @hw: pointer to hardware structure
917 * @vlan: VLAN id to write to VLAN filter
918 * @vind: VMDq output index that maps queue to VLAN id in VFTA
919 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
920 *
921 * Turn on/off specified VLAN in the VLAN filter table.
922 **/
Hannes Edere855aac2008-12-26 00:03:59 -0800923static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
924 bool vlan_on)
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700925{
926 u32 regindex;
927 u32 bitindex;
928 u32 bits;
929 u32 vftabyte;
930
931 if (vlan > 4095)
932 return IXGBE_ERR_PARAM;
933
934 /* Determine 32-bit word position in array */
935 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
936
937 /* Determine the location of the (VMD) queue index */
938 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
939 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
940
941 /* Set the nibble for VMD queue index */
942 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
943 bits &= (~(0x0F << bitindex));
944 bits |= (vind << bitindex);
945 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
946
947 /* Determine the location of the bit for this VLAN id */
948 bitindex = vlan & 0x1F; /* lower five bits */
949
950 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
951 if (vlan_on)
952 /* Turn on this VLAN id */
953 bits |= (1 << bitindex);
954 else
955 /* Turn off this VLAN id */
956 bits &= ~(1 << bitindex);
957 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
958
959 return 0;
960}
961
962/**
963 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
964 * @hw: pointer to hardware structure
965 *
966 * Clears the VLAN filer table, and the VMDq index associated with the filter
967 **/
968static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
969{
970 u32 offset;
971 u32 vlanbyte;
972
973 for (offset = 0; offset < hw->mac.vft_size; offset++)
974 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
975
976 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
977 for (offset = 0; offset < hw->mac.vft_size; offset++)
978 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
Peter P Waskiewiczb4617242008-09-11 20:04:46 -0700979 0);
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700980
981 return 0;
982}
983
984/**
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700985 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
986 * @hw: pointer to hardware structure
987 * @reg: analog register to read
988 * @val: read value
989 *
990 * Performs read operation to Atlas analog register specified.
991 **/
Hannes Edere855aac2008-12-26 00:03:59 -0800992static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700993{
994 u32 atlas_ctl;
995
996 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
997 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
998 IXGBE_WRITE_FLUSH(hw);
999 udelay(10);
1000 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
1001 *val = (u8)atlas_ctl;
1002
1003 return 0;
1004}
1005
1006/**
1007 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
1008 * @hw: pointer to hardware structure
1009 * @reg: atlas register to write
1010 * @val: value to write
1011 *
1012 * Performs write operation to Atlas analog register specified.
1013 **/
Hannes Edere855aac2008-12-26 00:03:59 -08001014static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001015{
1016 u32 atlas_ctl;
1017
1018 atlas_ctl = (reg << 8) | val;
1019 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1020 IXGBE_WRITE_FLUSH(hw);
1021 udelay(10);
1022
1023 return 0;
1024}
1025
1026/**
Emil Tantilov8c7bea32011-02-19 08:43:44 +00001027 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
Donald Skidmorec4900be2008-11-20 21:11:42 -08001028 * @hw: pointer to hardware structure
1029 * @byte_offset: EEPROM byte offset to read
1030 * @eeprom_data: value read
1031 *
Emil Tantilov8c7bea32011-02-19 08:43:44 +00001032 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
Donald Skidmorec4900be2008-11-20 21:11:42 -08001033 **/
Hannes Edere855aac2008-12-26 00:03:59 -08001034static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1035 u8 *eeprom_data)
Donald Skidmorec4900be2008-11-20 21:11:42 -08001036{
1037 s32 status = 0;
1038 u16 sfp_addr = 0;
1039 u16 sfp_data = 0;
1040 u16 sfp_stat = 0;
1041 u32 i;
1042
1043 if (hw->phy.type == ixgbe_phy_nl) {
1044 /*
1045 * phy SDA/SCL registers are at addresses 0xC30A to
1046 * 0xC30D. These registers are used to talk to the SFP+
1047 * module's EEPROM through the SDA/SCL (I2C) interface.
1048 */
1049 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
1050 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1051 hw->phy.ops.write_reg(hw,
1052 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
Ben Hutchings6b73e102009-04-29 08:08:58 +00001053 MDIO_MMD_PMAPMD,
Donald Skidmorec4900be2008-11-20 21:11:42 -08001054 sfp_addr);
1055
1056 /* Poll status */
1057 for (i = 0; i < 100; i++) {
1058 hw->phy.ops.read_reg(hw,
1059 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
Ben Hutchings6b73e102009-04-29 08:08:58 +00001060 MDIO_MMD_PMAPMD,
Donald Skidmorec4900be2008-11-20 21:11:42 -08001061 &sfp_stat);
1062 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1063 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1064 break;
1065 msleep(10);
1066 }
1067
1068 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1069 hw_dbg(hw, "EEPROM read did not pass.\n");
1070 status = IXGBE_ERR_SFP_NOT_PRESENT;
1071 goto out;
1072 }
1073
1074 /* Read data */
1075 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
Ben Hutchings6b73e102009-04-29 08:08:58 +00001076 MDIO_MMD_PMAPMD, &sfp_data);
Donald Skidmorec4900be2008-11-20 21:11:42 -08001077
1078 *eeprom_data = (u8)(sfp_data >> 8);
1079 } else {
1080 status = IXGBE_ERR_PHY;
1081 goto out;
1082 }
1083
1084out:
1085 return status;
1086}
1087
1088/**
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001089 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1090 * @hw: pointer to hardware structure
1091 *
1092 * Determines physical layer capabilities of the current configuration.
1093 **/
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00001094static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001095{
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00001096 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001097 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1098 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1099 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1100 u16 ext_ability = 0;
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001101
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001102 hw->phy.ops.identify(hw);
1103
1104 /* Copper PHY must be checked before AUTOC LMS to determine correct
1105 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
Emil Tantilov037c6d02011-02-25 07:49:39 +00001106 switch (hw->phy.type) {
1107 case ixgbe_phy_tn:
1108 case ixgbe_phy_aq:
1109 case ixgbe_phy_cu_unknown:
1110 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE,
1111 MDIO_MMD_PMAPMD, &ext_ability);
Ben Hutchings6b73e102009-04-29 08:08:58 +00001112 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001113 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
Ben Hutchings6b73e102009-04-29 08:08:58 +00001114 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001115 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
Ben Hutchings6b73e102009-04-29 08:08:58 +00001116 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001117 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1118 goto out;
Emil Tantilov037c6d02011-02-25 07:49:39 +00001119 default:
1120 break;
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001121 }
1122
1123 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1124 case IXGBE_AUTOC_LMS_1G_AN:
1125 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1126 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX)
1127 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1128 else
1129 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
Don Skidmore1e336d02009-01-26 20:57:51 -08001130 break;
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001131 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1132 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4)
1133 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1134 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4)
1135 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1136 else /* XAUI */
1137 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001138 break;
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001139 case IXGBE_AUTOC_LMS_KX4_AN:
1140 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
1141 if (autoc & IXGBE_AUTOC_KX_SUPP)
1142 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1143 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1144 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
Donald Skidmorec4900be2008-11-20 21:11:42 -08001145 break;
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001146 default:
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001147 break;
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001148 }
1149
1150 if (hw->phy.type == ixgbe_phy_nl) {
Donald Skidmorec4900be2008-11-20 21:11:42 -08001151 hw->phy.ops.identify_sfp(hw);
1152
1153 switch (hw->phy.sfp_type) {
1154 case ixgbe_sfp_type_da_cu:
1155 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1156 break;
1157 case ixgbe_sfp_type_sr:
1158 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1159 break;
1160 case ixgbe_sfp_type_lr:
1161 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1162 break;
1163 default:
1164 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1165 break;
1166 }
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001167 }
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001168
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001169 switch (hw->device_id) {
1170 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1171 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1172 break;
1173 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1174 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1175 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1176 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1177 break;
1178 case IXGBE_DEV_ID_82598EB_XF_LR:
1179 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1180 break;
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001181 default:
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001182 break;
1183 }
1184
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00001185out:
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001186 return physical_layer;
1187}
1188
Auke Kok9a799d72007-09-15 14:07:45 -07001189static struct ixgbe_mac_operations mac_ops_82598 = {
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001190 .init_hw = &ixgbe_init_hw_generic,
1191 .reset_hw = &ixgbe_reset_hw_82598,
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +00001192 .start_hw = &ixgbe_start_hw_82598,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001193 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
Auke Kok9a799d72007-09-15 14:07:45 -07001194 .get_media_type = &ixgbe_get_media_type_82598,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001195 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00001196 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001197 .get_mac_addr = &ixgbe_get_mac_addr_generic,
1198 .stop_adapter = &ixgbe_stop_adapter_generic,
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00001199 .get_bus_info = &ixgbe_get_bus_info_generic,
1200 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001201 .read_analog_reg8 = &ixgbe_read_analog_reg8_82598,
1202 .write_analog_reg8 = &ixgbe_write_analog_reg8_82598,
Auke Kok3957d632007-10-31 15:22:10 -07001203 .setup_link = &ixgbe_setup_mac_link_82598,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001204 .check_link = &ixgbe_check_mac_link_82598,
1205 .get_link_capabilities = &ixgbe_get_link_capabilities_82598,
1206 .led_on = &ixgbe_led_on_generic,
1207 .led_off = &ixgbe_led_off_generic,
PJ Waskiewicz87c12012009-04-08 13:20:31 +00001208 .blink_led_start = &ixgbe_blink_led_start_generic,
1209 .blink_led_stop = &ixgbe_blink_led_stop_generic,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001210 .set_rar = &ixgbe_set_rar_generic,
1211 .clear_rar = &ixgbe_clear_rar_generic,
1212 .set_vmdq = &ixgbe_set_vmdq_82598,
1213 .clear_vmdq = &ixgbe_clear_vmdq_82598,
1214 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001215 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1216 .enable_mc = &ixgbe_enable_mc_generic,
1217 .disable_mc = &ixgbe_disable_mc_generic,
1218 .clear_vfta = &ixgbe_clear_vfta_82598,
1219 .set_vfta = &ixgbe_set_vfta_82598,
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +00001220 .fc_enable = &ixgbe_fc_enable_82598,
Don Skidmore5e655102011-02-25 01:58:04 +00001221 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
1222 .release_swfw_sync = &ixgbe_release_swfw_sync,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001223};
1224
1225static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1226 .init_params = &ixgbe_init_eeprom_params_generic,
Mallikarjuna R Chilakala21ce8492010-05-13 17:33:41 +00001227 .read = &ixgbe_read_eerd_generic,
Don Skidmorea391f1d2010-11-16 19:27:15 -08001228 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001229 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1230 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1231};
1232
1233static struct ixgbe_phy_operations phy_ops_82598 = {
1234 .identify = &ixgbe_identify_phy_generic,
Donald Skidmorec4900be2008-11-20 21:11:42 -08001235 .identify_sfp = &ixgbe_identify_sfp_module_generic,
PJ Waskiewicz04f165e2009-04-09 22:27:57 +00001236 .init = &ixgbe_init_phy_ops_82598,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001237 .reset = &ixgbe_reset_phy_generic,
1238 .read_reg = &ixgbe_read_phy_reg_generic,
1239 .write_reg = &ixgbe_write_phy_reg_generic,
1240 .setup_link = &ixgbe_setup_phy_link_generic,
1241 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
Donald Skidmorec4900be2008-11-20 21:11:42 -08001242 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598,
Mallikarjuna R Chilakala119fc602010-05-20 23:07:06 -07001243 .check_overtemp = &ixgbe_tn_check_overtemp,
Auke Kok9a799d72007-09-15 14:07:45 -07001244};
1245
Auke Kok3957d632007-10-31 15:22:10 -07001246struct ixgbe_info ixgbe_82598_info = {
Auke Kok9a799d72007-09-15 14:07:45 -07001247 .mac = ixgbe_mac_82598EB,
1248 .get_invariants = &ixgbe_get_invariants_82598,
1249 .mac_ops = &mac_ops_82598,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001250 .eeprom_ops = &eeprom_ops_82598,
1251 .phy_ops = &phy_ops_82598,
Auke Kok9a799d72007-09-15 14:07:45 -07001252};
1253