Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel 10 Gigabit PCI Express Linux driver |
Peter P Waskiewicz Jr | 3efac5a | 2009-02-01 01:19:20 -0800 | [diff] [blame] | 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
| 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
| 22 | Contact Information: |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 25 | |
| 26 | *******************************************************************************/ |
| 27 | |
| 28 | #include <linux/pci.h> |
| 29 | #include <linux/delay.h> |
| 30 | #include <linux/sched.h> |
| 31 | |
| 32 | #include "ixgbe_common.h" |
| 33 | #include "ixgbe_phy.h" |
| 34 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 35 | static void ixgbe_i2c_start(struct ixgbe_hw *hw); |
| 36 | static void ixgbe_i2c_stop(struct ixgbe_hw *hw); |
| 37 | static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); |
| 38 | static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); |
| 39 | static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); |
| 40 | static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); |
| 41 | static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); |
| 42 | static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); |
| 43 | static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); |
| 44 | static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); |
| 45 | static bool ixgbe_get_i2c_data(u32 *i2cctl); |
| 46 | static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 47 | static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 48 | static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); |
| 49 | static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 50 | |
| 51 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 52 | * ixgbe_identify_phy_generic - Get physical layer module |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 53 | * @hw: pointer to hardware structure |
| 54 | * |
| 55 | * Determines the physical layer module found on the current adapter. |
| 56 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 57 | s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 58 | { |
| 59 | s32 status = IXGBE_ERR_PHY_ADDR_INVALID; |
| 60 | u32 phy_addr; |
| 61 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 62 | if (hw->phy.type == ixgbe_phy_unknown) { |
| 63 | for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { |
| 64 | if (ixgbe_validate_phy_addr(hw, phy_addr)) { |
| 65 | hw->phy.addr = phy_addr; |
| 66 | ixgbe_get_phy_id(hw); |
| 67 | hw->phy.type = |
| 68 | ixgbe_get_phy_type_from_id(hw->phy.id); |
| 69 | status = 0; |
| 70 | break; |
| 71 | } |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 72 | } |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 73 | } else { |
| 74 | status = 0; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 75 | } |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 76 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 77 | return status; |
| 78 | } |
| 79 | |
| 80 | /** |
| 81 | * ixgbe_validate_phy_addr - Determines phy address is valid |
| 82 | * @hw: pointer to hardware structure |
| 83 | * |
| 84 | **/ |
| 85 | static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) |
| 86 | { |
| 87 | u16 phy_id = 0; |
| 88 | bool valid = false; |
| 89 | |
| 90 | hw->phy.addr = phy_addr; |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 91 | hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, |
| 92 | IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 93 | |
| 94 | if (phy_id != 0xFFFF && phy_id != 0x0) |
| 95 | valid = true; |
| 96 | |
| 97 | return valid; |
| 98 | } |
| 99 | |
| 100 | /** |
| 101 | * ixgbe_get_phy_id - Get the phy type |
| 102 | * @hw: pointer to hardware structure |
| 103 | * |
| 104 | **/ |
| 105 | static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) |
| 106 | { |
| 107 | u32 status; |
| 108 | u16 phy_id_high = 0; |
| 109 | u16 phy_id_low = 0; |
| 110 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 111 | status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, |
| 112 | IXGBE_MDIO_PMA_PMD_DEV_TYPE, |
| 113 | &phy_id_high); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 114 | |
| 115 | if (status == 0) { |
| 116 | hw->phy.id = (u32)(phy_id_high << 16); |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 117 | status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, |
| 118 | IXGBE_MDIO_PMA_PMD_DEV_TYPE, |
| 119 | &phy_id_low); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 120 | hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); |
| 121 | hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); |
| 122 | } |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 123 | return status; |
| 124 | } |
| 125 | |
| 126 | /** |
| 127 | * ixgbe_get_phy_type_from_id - Get the phy type |
| 128 | * @hw: pointer to hardware structure |
| 129 | * |
| 130 | **/ |
| 131 | static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) |
| 132 | { |
| 133 | enum ixgbe_phy_type phy_type; |
| 134 | |
| 135 | switch (phy_id) { |
Jesse Brandeburg | 0befdb3 | 2008-10-31 00:46:40 -0700 | [diff] [blame] | 136 | case TN1010_PHY_ID: |
| 137 | phy_type = ixgbe_phy_tn; |
| 138 | break; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 139 | case QT2022_PHY_ID: |
| 140 | phy_type = ixgbe_phy_qt; |
| 141 | break; |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 142 | case ATH_PHY_ID: |
| 143 | phy_type = ixgbe_phy_nl; |
| 144 | break; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 145 | default: |
| 146 | phy_type = ixgbe_phy_unknown; |
| 147 | break; |
| 148 | } |
| 149 | |
| 150 | return phy_type; |
| 151 | } |
| 152 | |
| 153 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 154 | * ixgbe_reset_phy_generic - Performs a PHY reset |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 155 | * @hw: pointer to hardware structure |
| 156 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 157 | s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 158 | { |
| 159 | /* |
| 160 | * Perform soft PHY reset to the PHY_XS. |
| 161 | * This will cause a soft reset to the PHY |
| 162 | */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 163 | return hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, |
| 164 | IXGBE_MDIO_PHY_XS_DEV_TYPE, |
| 165 | IXGBE_MDIO_PHY_XS_RESET); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 166 | } |
| 167 | |
| 168 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 169 | * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 170 | * @hw: pointer to hardware structure |
| 171 | * @reg_addr: 32 bit address of PHY register to read |
| 172 | * @phy_data: Pointer to read data from PHY register |
| 173 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 174 | s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, |
| 175 | u32 device_type, u16 *phy_data) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 176 | { |
| 177 | u32 command; |
| 178 | u32 i; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 179 | u32 data; |
| 180 | s32 status = 0; |
| 181 | u16 gssr; |
| 182 | |
| 183 | if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) |
| 184 | gssr = IXGBE_GSSR_PHY1_SM; |
| 185 | else |
| 186 | gssr = IXGBE_GSSR_PHY0_SM; |
| 187 | |
| 188 | if (ixgbe_acquire_swfw_sync(hw, gssr) != 0) |
| 189 | status = IXGBE_ERR_SWFW_SYNC; |
| 190 | |
| 191 | if (status == 0) { |
| 192 | /* Setup and write the address cycle command */ |
| 193 | command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 194 | (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | |
| 195 | (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | |
| 196 | (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 197 | |
| 198 | IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); |
| 199 | |
| 200 | /* |
| 201 | * Check every 10 usec to see if the address cycle completed. |
| 202 | * The MDI Command bit will clear when the operation is |
| 203 | * complete |
| 204 | */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 205 | for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 206 | udelay(10); |
| 207 | |
| 208 | command = IXGBE_READ_REG(hw, IXGBE_MSCA); |
| 209 | |
| 210 | if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) |
| 211 | break; |
| 212 | } |
| 213 | |
| 214 | if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { |
| 215 | hw_dbg(hw, "PHY address command did not complete.\n"); |
| 216 | status = IXGBE_ERR_PHY; |
| 217 | } |
| 218 | |
| 219 | if (status == 0) { |
| 220 | /* |
| 221 | * Address cycle complete, setup and write the read |
| 222 | * command |
| 223 | */ |
| 224 | command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 225 | (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | |
| 226 | (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | |
| 227 | (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 228 | |
| 229 | IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); |
| 230 | |
| 231 | /* |
| 232 | * Check every 10 usec to see if the address cycle |
| 233 | * completed. The MDI Command bit will clear when the |
| 234 | * operation is complete |
| 235 | */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 236 | for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 237 | udelay(10); |
| 238 | |
| 239 | command = IXGBE_READ_REG(hw, IXGBE_MSCA); |
| 240 | |
| 241 | if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) |
| 242 | break; |
| 243 | } |
| 244 | |
| 245 | if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 246 | hw_dbg(hw, "PHY read command didn't complete\n"); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 247 | status = IXGBE_ERR_PHY; |
| 248 | } else { |
| 249 | /* |
| 250 | * Read operation is complete. Get the data |
| 251 | * from MSRWD |
| 252 | */ |
| 253 | data = IXGBE_READ_REG(hw, IXGBE_MSRWD); |
| 254 | data >>= IXGBE_MSRWD_READ_DATA_SHIFT; |
| 255 | *phy_data = (u16)(data); |
| 256 | } |
| 257 | } |
| 258 | |
| 259 | ixgbe_release_swfw_sync(hw, gssr); |
| 260 | } |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 261 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 262 | return status; |
| 263 | } |
| 264 | |
| 265 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 266 | * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 267 | * @hw: pointer to hardware structure |
| 268 | * @reg_addr: 32 bit PHY register to write |
| 269 | * @device_type: 5 bit device type |
| 270 | * @phy_data: Data to write to the PHY register |
| 271 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 272 | s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, |
| 273 | u32 device_type, u16 phy_data) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 274 | { |
| 275 | u32 command; |
| 276 | u32 i; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 277 | s32 status = 0; |
| 278 | u16 gssr; |
| 279 | |
| 280 | if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) |
| 281 | gssr = IXGBE_GSSR_PHY1_SM; |
| 282 | else |
| 283 | gssr = IXGBE_GSSR_PHY0_SM; |
| 284 | |
| 285 | if (ixgbe_acquire_swfw_sync(hw, gssr) != 0) |
| 286 | status = IXGBE_ERR_SWFW_SYNC; |
| 287 | |
| 288 | if (status == 0) { |
| 289 | /* Put the data in the MDI single read and write data register*/ |
| 290 | IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); |
| 291 | |
| 292 | /* Setup and write the address cycle command */ |
| 293 | command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 294 | (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | |
| 295 | (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | |
| 296 | (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 297 | |
| 298 | IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); |
| 299 | |
| 300 | /* |
| 301 | * Check every 10 usec to see if the address cycle completed. |
| 302 | * The MDI Command bit will clear when the operation is |
| 303 | * complete |
| 304 | */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 305 | for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 306 | udelay(10); |
| 307 | |
| 308 | command = IXGBE_READ_REG(hw, IXGBE_MSCA); |
| 309 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 310 | if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 311 | break; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 312 | } |
| 313 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 314 | if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { |
| 315 | hw_dbg(hw, "PHY address cmd didn't complete\n"); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 316 | status = IXGBE_ERR_PHY; |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 317 | } |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 318 | |
| 319 | if (status == 0) { |
| 320 | /* |
| 321 | * Address cycle complete, setup and write the write |
| 322 | * command |
| 323 | */ |
| 324 | command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 325 | (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | |
| 326 | (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | |
| 327 | (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 328 | |
| 329 | IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); |
| 330 | |
| 331 | /* |
| 332 | * Check every 10 usec to see if the address cycle |
| 333 | * completed. The MDI Command bit will clear when the |
| 334 | * operation is complete |
| 335 | */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 336 | for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 337 | udelay(10); |
| 338 | |
| 339 | command = IXGBE_READ_REG(hw, IXGBE_MSCA); |
| 340 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 341 | if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 342 | break; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 343 | } |
| 344 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 345 | if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { |
| 346 | hw_dbg(hw, "PHY address cmd didn't complete\n"); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 347 | status = IXGBE_ERR_PHY; |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 348 | } |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 349 | } |
| 350 | |
| 351 | ixgbe_release_swfw_sync(hw, gssr); |
| 352 | } |
| 353 | |
| 354 | return status; |
| 355 | } |
| 356 | |
| 357 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 358 | * ixgbe_setup_phy_link_generic - Set and restart autoneg |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 359 | * @hw: pointer to hardware structure |
| 360 | * |
| 361 | * Restart autonegotiation and PHY and waits for completion. |
| 362 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 363 | s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 364 | { |
| 365 | s32 status = IXGBE_NOT_IMPLEMENTED; |
| 366 | u32 time_out; |
| 367 | u32 max_time_out = 10; |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 368 | u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 369 | |
| 370 | /* |
| 371 | * Set advertisement settings in PHY based on autoneg_advertised |
| 372 | * settings. If autoneg_advertised = 0, then advertise default values |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 373 | * tnx devices cannot be "forced" to a autoneg 10G and fail. But can |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 374 | * for a 1G. |
| 375 | */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 376 | hw->phy.ops.read_reg(hw, IXGBE_MII_SPEED_SELECTION_REG, |
| 377 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 378 | |
| 379 | if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL) |
| 380 | autoneg_reg &= 0xEFFF; /* 0 in bit 12 is 1G operation */ |
| 381 | else |
| 382 | autoneg_reg |= 0x1000; /* 1 in bit 12 is 10G/1G operation */ |
| 383 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 384 | hw->phy.ops.write_reg(hw, IXGBE_MII_SPEED_SELECTION_REG, |
| 385 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 386 | |
| 387 | /* Restart PHY autonegotiation and wait for completion */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 388 | hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, |
| 389 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 390 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 391 | autoneg_reg |= IXGBE_MII_RESTART; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 392 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 393 | hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, |
| 394 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 395 | |
| 396 | /* Wait for autonegotiation to finish */ |
| 397 | for (time_out = 0; time_out < max_time_out; time_out++) { |
| 398 | udelay(10); |
| 399 | /* Restart PHY autonegotiation and wait for completion */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 400 | status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, |
| 401 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, |
| 402 | &autoneg_reg); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 403 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 404 | autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; |
| 405 | if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) { |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 406 | status = 0; |
| 407 | break; |
| 408 | } |
| 409 | } |
| 410 | |
| 411 | if (time_out == max_time_out) |
| 412 | status = IXGBE_ERR_LINK_SETUP; |
| 413 | |
| 414 | return status; |
| 415 | } |
| 416 | |
| 417 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 418 | * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 419 | * @hw: pointer to hardware structure |
| 420 | * @speed: new link speed |
| 421 | * @autoneg: true if autonegotiation enabled |
| 422 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 423 | s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, |
| 424 | ixgbe_link_speed speed, |
| 425 | bool autoneg, |
| 426 | bool autoneg_wait_to_complete) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 427 | { |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 428 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 429 | /* |
| 430 | * Clear autoneg_advertised and set new values based on input link |
| 431 | * speed. |
| 432 | */ |
| 433 | hw->phy.autoneg_advertised = 0; |
| 434 | |
| 435 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) |
| 436 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 437 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 438 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) |
| 439 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; |
| 440 | |
| 441 | /* Setup link based on the new speed settings */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 442 | hw->phy.ops.setup_link(hw); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 443 | |
| 444 | return 0; |
| 445 | } |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 446 | |
Jesse Brandeburg | 0befdb3 | 2008-10-31 00:46:40 -0700 | [diff] [blame] | 447 | /** |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 448 | * ixgbe_reset_phy_nl - Performs a PHY reset |
| 449 | * @hw: pointer to hardware structure |
| 450 | **/ |
| 451 | s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) |
| 452 | { |
| 453 | u16 phy_offset, control, eword, edata, block_crc; |
| 454 | bool end_data = false; |
| 455 | u16 list_offset, data_offset; |
| 456 | u16 phy_data = 0; |
| 457 | s32 ret_val = 0; |
| 458 | u32 i; |
| 459 | |
| 460 | hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, |
| 461 | IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); |
| 462 | |
| 463 | /* reset the PHY and poll for completion */ |
| 464 | hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, |
| 465 | IXGBE_MDIO_PHY_XS_DEV_TYPE, |
| 466 | (phy_data | IXGBE_MDIO_PHY_XS_RESET)); |
| 467 | |
| 468 | for (i = 0; i < 100; i++) { |
| 469 | hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, |
| 470 | IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); |
| 471 | if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) |
| 472 | break; |
| 473 | msleep(10); |
| 474 | } |
| 475 | |
| 476 | if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { |
| 477 | hw_dbg(hw, "PHY reset did not complete.\n"); |
| 478 | ret_val = IXGBE_ERR_PHY; |
| 479 | goto out; |
| 480 | } |
| 481 | |
| 482 | /* Get init offsets */ |
| 483 | ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, |
| 484 | &data_offset); |
| 485 | if (ret_val != 0) |
| 486 | goto out; |
| 487 | |
| 488 | ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); |
| 489 | data_offset++; |
| 490 | while (!end_data) { |
| 491 | /* |
| 492 | * Read control word from PHY init contents offset |
| 493 | */ |
| 494 | ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); |
| 495 | control = (eword & IXGBE_CONTROL_MASK_NL) >> |
| 496 | IXGBE_CONTROL_SHIFT_NL; |
| 497 | edata = eword & IXGBE_DATA_MASK_NL; |
| 498 | switch (control) { |
| 499 | case IXGBE_DELAY_NL: |
| 500 | data_offset++; |
| 501 | hw_dbg(hw, "DELAY: %d MS\n", edata); |
| 502 | msleep(edata); |
| 503 | break; |
| 504 | case IXGBE_DATA_NL: |
| 505 | hw_dbg(hw, "DATA: \n"); |
| 506 | data_offset++; |
| 507 | hw->eeprom.ops.read(hw, data_offset++, |
| 508 | &phy_offset); |
| 509 | for (i = 0; i < edata; i++) { |
| 510 | hw->eeprom.ops.read(hw, data_offset, &eword); |
| 511 | hw->phy.ops.write_reg(hw, phy_offset, |
| 512 | IXGBE_TWINAX_DEV, eword); |
| 513 | hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword, |
| 514 | phy_offset); |
| 515 | data_offset++; |
| 516 | phy_offset++; |
| 517 | } |
| 518 | break; |
| 519 | case IXGBE_CONTROL_NL: |
| 520 | data_offset++; |
| 521 | hw_dbg(hw, "CONTROL: \n"); |
| 522 | if (edata == IXGBE_CONTROL_EOL_NL) { |
| 523 | hw_dbg(hw, "EOL\n"); |
| 524 | end_data = true; |
| 525 | } else if (edata == IXGBE_CONTROL_SOL_NL) { |
| 526 | hw_dbg(hw, "SOL\n"); |
| 527 | } else { |
| 528 | hw_dbg(hw, "Bad control value\n"); |
| 529 | ret_val = IXGBE_ERR_PHY; |
| 530 | goto out; |
| 531 | } |
| 532 | break; |
| 533 | default: |
| 534 | hw_dbg(hw, "Bad control type\n"); |
| 535 | ret_val = IXGBE_ERR_PHY; |
| 536 | goto out; |
| 537 | } |
| 538 | } |
| 539 | |
| 540 | out: |
| 541 | return ret_val; |
| 542 | } |
| 543 | |
| 544 | /** |
| 545 | * ixgbe_identify_sfp_module_generic - Identifies SFP module and assigns |
| 546 | * the PHY type. |
| 547 | * @hw: pointer to hardware structure |
| 548 | * |
| 549 | * Searches for and indentifies the SFP module. Assings appropriate PHY type. |
| 550 | **/ |
| 551 | s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) |
| 552 | { |
| 553 | s32 status = IXGBE_ERR_PHY_ADDR_INVALID; |
| 554 | u32 vendor_oui = 0; |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 555 | enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 556 | u8 identifier = 0; |
| 557 | u8 comp_codes_1g = 0; |
| 558 | u8 comp_codes_10g = 0; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 559 | u8 oui_bytes[3] = {0, 0, 0}; |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 560 | u8 transmission_media = 0; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 561 | u16 enforce_sfp = 0; |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 562 | |
| 563 | status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, |
| 564 | &identifier); |
| 565 | |
| 566 | if (status == IXGBE_ERR_SFP_NOT_PRESENT) { |
| 567 | hw->phy.sfp_type = ixgbe_sfp_type_not_present; |
| 568 | goto out; |
| 569 | } |
| 570 | |
| 571 | if (identifier == IXGBE_SFF_IDENTIFIER_SFP) { |
| 572 | hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES, |
| 573 | &comp_codes_1g); |
| 574 | hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES, |
| 575 | &comp_codes_10g); |
| 576 | hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_TRANSMISSION_MEDIA, |
| 577 | &transmission_media); |
| 578 | |
| 579 | /* ID Module |
| 580 | * ========= |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 581 | * 0 SFP_DA_CU |
| 582 | * 1 SFP_SR |
| 583 | * 2 SFP_LR |
| 584 | * 3 SFP_DA_CORE0 - 82599-specific |
| 585 | * 4 SFP_DA_CORE1 - 82599-specific |
| 586 | * 5 SFP_SR/LR_CORE0 - 82599-specific |
| 587 | * 6 SFP_SR/LR_CORE1 - 82599-specific |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 588 | */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 589 | if (hw->mac.type == ixgbe_mac_82598EB) { |
| 590 | if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE) |
| 591 | hw->phy.sfp_type = ixgbe_sfp_type_da_cu; |
| 592 | else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) |
| 593 | hw->phy.sfp_type = ixgbe_sfp_type_sr; |
| 594 | else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) |
| 595 | hw->phy.sfp_type = ixgbe_sfp_type_lr; |
| 596 | else |
| 597 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
| 598 | } else if (hw->mac.type == ixgbe_mac_82599EB) { |
| 599 | if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE) |
| 600 | if (hw->bus.lan_id == 0) |
| 601 | hw->phy.sfp_type = |
| 602 | ixgbe_sfp_type_da_cu_core0; |
| 603 | else |
| 604 | hw->phy.sfp_type = |
| 605 | ixgbe_sfp_type_da_cu_core1; |
| 606 | else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) |
| 607 | if (hw->bus.lan_id == 0) |
| 608 | hw->phy.sfp_type = |
| 609 | ixgbe_sfp_type_srlr_core0; |
| 610 | else |
| 611 | hw->phy.sfp_type = |
| 612 | ixgbe_sfp_type_srlr_core1; |
| 613 | else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) |
| 614 | if (hw->bus.lan_id == 0) |
| 615 | hw->phy.sfp_type = |
| 616 | ixgbe_sfp_type_srlr_core0; |
| 617 | else |
| 618 | hw->phy.sfp_type = |
| 619 | ixgbe_sfp_type_srlr_core1; |
| 620 | else |
| 621 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
| 622 | } |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 623 | |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 624 | if (hw->phy.sfp_type != stored_sfp_type) |
| 625 | hw->phy.sfp_setup_needed = true; |
| 626 | |
| 627 | /* Determine if the SFP+ PHY is dual speed or not. */ |
| 628 | if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && |
| 629 | (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || |
| 630 | ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && |
| 631 | (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) |
| 632 | hw->phy.multispeed_fiber = true; |
| 633 | |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 634 | /* Determine PHY vendor */ |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame^] | 635 | if (hw->phy.type != ixgbe_phy_nl) { |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 636 | hw->phy.id = identifier; |
| 637 | hw->phy.ops.read_i2c_eeprom(hw, |
| 638 | IXGBE_SFF_VENDOR_OUI_BYTE0, |
| 639 | &oui_bytes[0]); |
| 640 | hw->phy.ops.read_i2c_eeprom(hw, |
| 641 | IXGBE_SFF_VENDOR_OUI_BYTE1, |
| 642 | &oui_bytes[1]); |
| 643 | hw->phy.ops.read_i2c_eeprom(hw, |
| 644 | IXGBE_SFF_VENDOR_OUI_BYTE2, |
| 645 | &oui_bytes[2]); |
| 646 | |
| 647 | vendor_oui = |
| 648 | ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | |
| 649 | (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | |
| 650 | (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); |
| 651 | |
| 652 | switch (vendor_oui) { |
| 653 | case IXGBE_SFF_VENDOR_OUI_TYCO: |
| 654 | if (transmission_media & |
| 655 | IXGBE_SFF_TWIN_AX_CAPABLE) |
| 656 | hw->phy.type = ixgbe_phy_tw_tyco; |
| 657 | break; |
| 658 | case IXGBE_SFF_VENDOR_OUI_FTL: |
| 659 | hw->phy.type = ixgbe_phy_sfp_ftl; |
| 660 | break; |
| 661 | case IXGBE_SFF_VENDOR_OUI_AVAGO: |
| 662 | hw->phy.type = ixgbe_phy_sfp_avago; |
| 663 | break; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 664 | case IXGBE_SFF_VENDOR_OUI_INTEL: |
| 665 | hw->phy.type = ixgbe_phy_sfp_intel; |
| 666 | break; |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 667 | default: |
| 668 | if (transmission_media & |
| 669 | IXGBE_SFF_TWIN_AX_CAPABLE) |
| 670 | hw->phy.type = ixgbe_phy_tw_unknown; |
| 671 | else |
| 672 | hw->phy.type = ixgbe_phy_sfp_unknown; |
| 673 | break; |
| 674 | } |
| 675 | } |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 676 | if (hw->mac.type == ixgbe_mac_82598EB || |
| 677 | (hw->phy.sfp_type != ixgbe_sfp_type_sr && |
| 678 | hw->phy.sfp_type != ixgbe_sfp_type_lr && |
| 679 | hw->phy.sfp_type != ixgbe_sfp_type_srlr_core0 && |
| 680 | hw->phy.sfp_type != ixgbe_sfp_type_srlr_core1)) { |
| 681 | status = 0; |
| 682 | goto out; |
| 683 | } |
| 684 | |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame^] | 685 | /* This is guaranteed to be 82599, no need to check for NULL */ |
| 686 | hw->mac.ops.get_device_caps(hw, &enforce_sfp); |
| 687 | if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 688 | /* Make sure we're a supported PHY type */ |
| 689 | if (hw->phy.type == ixgbe_phy_sfp_intel) { |
| 690 | status = 0; |
| 691 | } else { |
| 692 | hw_dbg(hw, "SFP+ module not supported\n"); |
| 693 | status = IXGBE_ERR_SFP_NOT_SUPPORTED; |
| 694 | } |
| 695 | } else { |
| 696 | status = 0; |
| 697 | } |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 698 | } |
| 699 | |
| 700 | out: |
| 701 | return status; |
| 702 | } |
| 703 | |
| 704 | /** |
| 705 | * ixgbe_get_sfp_init_sequence_offsets - Checks the MAC's EEPROM to see |
| 706 | * if it supports a given SFP+ module type, if so it returns the offsets to the |
| 707 | * phy init sequence block. |
| 708 | * @hw: pointer to hardware structure |
| 709 | * @list_offset: offset to the SFP ID list |
| 710 | * @data_offset: offset to the SFP data block |
| 711 | **/ |
| 712 | s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, |
| 713 | u16 *list_offset, |
| 714 | u16 *data_offset) |
| 715 | { |
| 716 | u16 sfp_id; |
| 717 | |
| 718 | if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) |
| 719 | return IXGBE_ERR_SFP_NOT_SUPPORTED; |
| 720 | |
| 721 | if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) |
| 722 | return IXGBE_ERR_SFP_NOT_PRESENT; |
| 723 | |
| 724 | if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && |
| 725 | (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) |
| 726 | return IXGBE_ERR_SFP_NOT_SUPPORTED; |
| 727 | |
| 728 | /* Read offset to PHY init contents */ |
| 729 | hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); |
| 730 | |
| 731 | if ((!*list_offset) || (*list_offset == 0xFFFF)) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 732 | return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 733 | |
| 734 | /* Shift offset to first ID word */ |
| 735 | (*list_offset)++; |
| 736 | |
| 737 | /* |
| 738 | * Find the matching SFP ID in the EEPROM |
| 739 | * and program the init sequence |
| 740 | */ |
| 741 | hw->eeprom.ops.read(hw, *list_offset, &sfp_id); |
| 742 | |
| 743 | while (sfp_id != IXGBE_PHY_INIT_END_NL) { |
| 744 | if (sfp_id == hw->phy.sfp_type) { |
| 745 | (*list_offset)++; |
| 746 | hw->eeprom.ops.read(hw, *list_offset, data_offset); |
| 747 | if ((!*data_offset) || (*data_offset == 0xFFFF)) { |
| 748 | hw_dbg(hw, "SFP+ module not supported\n"); |
| 749 | return IXGBE_ERR_SFP_NOT_SUPPORTED; |
| 750 | } else { |
| 751 | break; |
| 752 | } |
| 753 | } else { |
| 754 | (*list_offset) += 2; |
| 755 | if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) |
| 756 | return IXGBE_ERR_PHY; |
| 757 | } |
| 758 | } |
| 759 | |
| 760 | if (sfp_id == IXGBE_PHY_INIT_END_NL) { |
| 761 | hw_dbg(hw, "No matching SFP+ module found\n"); |
| 762 | return IXGBE_ERR_SFP_NOT_SUPPORTED; |
| 763 | } |
| 764 | |
| 765 | return 0; |
| 766 | } |
| 767 | |
| 768 | /** |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 769 | * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface |
| 770 | * @hw: pointer to hardware structure |
| 771 | * @byte_offset: EEPROM byte offset to read |
| 772 | * @eeprom_data: value read |
| 773 | * |
| 774 | * Performs byte read operation to SFP module's EEPROM over I2C interface. |
| 775 | **/ |
| 776 | s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, |
| 777 | u8 *eeprom_data) |
| 778 | { |
| 779 | return hw->phy.ops.read_i2c_byte(hw, byte_offset, |
| 780 | IXGBE_I2C_EEPROM_DEV_ADDR, |
| 781 | eeprom_data); |
| 782 | } |
| 783 | |
| 784 | /** |
| 785 | * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface |
| 786 | * @hw: pointer to hardware structure |
| 787 | * @byte_offset: EEPROM byte offset to write |
| 788 | * @eeprom_data: value to write |
| 789 | * |
| 790 | * Performs byte write operation to SFP module's EEPROM over I2C interface. |
| 791 | **/ |
| 792 | s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, |
| 793 | u8 eeprom_data) |
| 794 | { |
| 795 | return hw->phy.ops.write_i2c_byte(hw, byte_offset, |
| 796 | IXGBE_I2C_EEPROM_DEV_ADDR, |
| 797 | eeprom_data); |
| 798 | } |
| 799 | |
| 800 | /** |
| 801 | * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C |
| 802 | * @hw: pointer to hardware structure |
| 803 | * @byte_offset: byte offset to read |
| 804 | * @data: value read |
| 805 | * |
| 806 | * Performs byte read operation to SFP module's EEPROM over I2C interface at |
| 807 | * a specified deivce address. |
| 808 | **/ |
| 809 | s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, |
| 810 | u8 dev_addr, u8 *data) |
| 811 | { |
| 812 | s32 status = 0; |
| 813 | u32 max_retry = 1; |
| 814 | u32 retry = 0; |
| 815 | bool nack = 1; |
| 816 | |
| 817 | do { |
| 818 | ixgbe_i2c_start(hw); |
| 819 | |
| 820 | /* Device Address and write indication */ |
| 821 | status = ixgbe_clock_out_i2c_byte(hw, dev_addr); |
| 822 | if (status != 0) |
| 823 | goto fail; |
| 824 | |
| 825 | status = ixgbe_get_i2c_ack(hw); |
| 826 | if (status != 0) |
| 827 | goto fail; |
| 828 | |
| 829 | status = ixgbe_clock_out_i2c_byte(hw, byte_offset); |
| 830 | if (status != 0) |
| 831 | goto fail; |
| 832 | |
| 833 | status = ixgbe_get_i2c_ack(hw); |
| 834 | if (status != 0) |
| 835 | goto fail; |
| 836 | |
| 837 | ixgbe_i2c_start(hw); |
| 838 | |
| 839 | /* Device Address and read indication */ |
| 840 | status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); |
| 841 | if (status != 0) |
| 842 | goto fail; |
| 843 | |
| 844 | status = ixgbe_get_i2c_ack(hw); |
| 845 | if (status != 0) |
| 846 | goto fail; |
| 847 | |
| 848 | status = ixgbe_clock_in_i2c_byte(hw, data); |
| 849 | if (status != 0) |
| 850 | goto fail; |
| 851 | |
| 852 | status = ixgbe_clock_out_i2c_bit(hw, nack); |
| 853 | if (status != 0) |
| 854 | goto fail; |
| 855 | |
| 856 | ixgbe_i2c_stop(hw); |
| 857 | break; |
| 858 | |
| 859 | fail: |
| 860 | ixgbe_i2c_bus_clear(hw); |
| 861 | retry++; |
| 862 | if (retry < max_retry) |
| 863 | hw_dbg(hw, "I2C byte read error - Retrying.\n"); |
| 864 | else |
| 865 | hw_dbg(hw, "I2C byte read error.\n"); |
| 866 | |
| 867 | } while (retry < max_retry); |
| 868 | |
| 869 | return status; |
| 870 | } |
| 871 | |
| 872 | /** |
| 873 | * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C |
| 874 | * @hw: pointer to hardware structure |
| 875 | * @byte_offset: byte offset to write |
| 876 | * @data: value to write |
| 877 | * |
| 878 | * Performs byte write operation to SFP module's EEPROM over I2C interface at |
| 879 | * a specified device address. |
| 880 | **/ |
| 881 | s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, |
| 882 | u8 dev_addr, u8 data) |
| 883 | { |
| 884 | s32 status = 0; |
| 885 | u32 max_retry = 1; |
| 886 | u32 retry = 0; |
| 887 | |
| 888 | do { |
| 889 | ixgbe_i2c_start(hw); |
| 890 | |
| 891 | status = ixgbe_clock_out_i2c_byte(hw, dev_addr); |
| 892 | if (status != 0) |
| 893 | goto fail; |
| 894 | |
| 895 | status = ixgbe_get_i2c_ack(hw); |
| 896 | if (status != 0) |
| 897 | goto fail; |
| 898 | |
| 899 | status = ixgbe_clock_out_i2c_byte(hw, byte_offset); |
| 900 | if (status != 0) |
| 901 | goto fail; |
| 902 | |
| 903 | status = ixgbe_get_i2c_ack(hw); |
| 904 | if (status != 0) |
| 905 | goto fail; |
| 906 | |
| 907 | status = ixgbe_clock_out_i2c_byte(hw, data); |
| 908 | if (status != 0) |
| 909 | goto fail; |
| 910 | |
| 911 | status = ixgbe_get_i2c_ack(hw); |
| 912 | if (status != 0) |
| 913 | goto fail; |
| 914 | |
| 915 | ixgbe_i2c_stop(hw); |
| 916 | break; |
| 917 | |
| 918 | fail: |
| 919 | ixgbe_i2c_bus_clear(hw); |
| 920 | retry++; |
| 921 | if (retry < max_retry) |
| 922 | hw_dbg(hw, "I2C byte write error - Retrying.\n"); |
| 923 | else |
| 924 | hw_dbg(hw, "I2C byte write error.\n"); |
| 925 | } while (retry < max_retry); |
| 926 | |
| 927 | return status; |
| 928 | } |
| 929 | |
| 930 | /** |
| 931 | * ixgbe_i2c_start - Sets I2C start condition |
| 932 | * @hw: pointer to hardware structure |
| 933 | * |
| 934 | * Sets I2C start condition (High -> Low on SDA while SCL is High) |
| 935 | **/ |
| 936 | static void ixgbe_i2c_start(struct ixgbe_hw *hw) |
| 937 | { |
| 938 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 939 | |
| 940 | /* Start condition must begin with data and clock high */ |
| 941 | ixgbe_set_i2c_data(hw, &i2cctl, 1); |
| 942 | ixgbe_raise_i2c_clk(hw, &i2cctl); |
| 943 | |
| 944 | /* Setup time for start condition (4.7us) */ |
| 945 | udelay(IXGBE_I2C_T_SU_STA); |
| 946 | |
| 947 | ixgbe_set_i2c_data(hw, &i2cctl, 0); |
| 948 | |
| 949 | /* Hold time for start condition (4us) */ |
| 950 | udelay(IXGBE_I2C_T_HD_STA); |
| 951 | |
| 952 | ixgbe_lower_i2c_clk(hw, &i2cctl); |
| 953 | |
| 954 | /* Minimum low period of clock is 4.7 us */ |
| 955 | udelay(IXGBE_I2C_T_LOW); |
| 956 | |
| 957 | } |
| 958 | |
| 959 | /** |
| 960 | * ixgbe_i2c_stop - Sets I2C stop condition |
| 961 | * @hw: pointer to hardware structure |
| 962 | * |
| 963 | * Sets I2C stop condition (Low -> High on SDA while SCL is High) |
| 964 | **/ |
| 965 | static void ixgbe_i2c_stop(struct ixgbe_hw *hw) |
| 966 | { |
| 967 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 968 | |
| 969 | /* Stop condition must begin with data low and clock high */ |
| 970 | ixgbe_set_i2c_data(hw, &i2cctl, 0); |
| 971 | ixgbe_raise_i2c_clk(hw, &i2cctl); |
| 972 | |
| 973 | /* Setup time for stop condition (4us) */ |
| 974 | udelay(IXGBE_I2C_T_SU_STO); |
| 975 | |
| 976 | ixgbe_set_i2c_data(hw, &i2cctl, 1); |
| 977 | |
| 978 | /* bus free time between stop and start (4.7us)*/ |
| 979 | udelay(IXGBE_I2C_T_BUF); |
| 980 | } |
| 981 | |
| 982 | /** |
| 983 | * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C |
| 984 | * @hw: pointer to hardware structure |
| 985 | * @data: data byte to clock in |
| 986 | * |
| 987 | * Clocks in one byte data via I2C data/clock |
| 988 | **/ |
| 989 | static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) |
| 990 | { |
| 991 | s32 status = 0; |
| 992 | s32 i; |
| 993 | bool bit = 0; |
| 994 | |
| 995 | for (i = 7; i >= 0; i--) { |
| 996 | status = ixgbe_clock_in_i2c_bit(hw, &bit); |
| 997 | *data |= bit << i; |
| 998 | |
| 999 | if (status != 0) |
| 1000 | break; |
| 1001 | } |
| 1002 | |
| 1003 | return status; |
| 1004 | } |
| 1005 | |
| 1006 | /** |
| 1007 | * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C |
| 1008 | * @hw: pointer to hardware structure |
| 1009 | * @data: data byte clocked out |
| 1010 | * |
| 1011 | * Clocks out one byte data via I2C data/clock |
| 1012 | **/ |
| 1013 | static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) |
| 1014 | { |
| 1015 | s32 status = 0; |
| 1016 | s32 i; |
| 1017 | u32 i2cctl; |
| 1018 | bool bit = 0; |
| 1019 | |
| 1020 | for (i = 7; i >= 0; i--) { |
| 1021 | bit = (data >> i) & 0x1; |
| 1022 | status = ixgbe_clock_out_i2c_bit(hw, bit); |
| 1023 | |
| 1024 | if (status != 0) |
| 1025 | break; |
| 1026 | } |
| 1027 | |
| 1028 | /* Release SDA line (set high) */ |
| 1029 | i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1030 | i2cctl |= IXGBE_I2C_DATA_OUT; |
| 1031 | IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl); |
| 1032 | |
| 1033 | return status; |
| 1034 | } |
| 1035 | |
| 1036 | /** |
| 1037 | * ixgbe_get_i2c_ack - Polls for I2C ACK |
| 1038 | * @hw: pointer to hardware structure |
| 1039 | * |
| 1040 | * Clocks in/out one bit via I2C data/clock |
| 1041 | **/ |
| 1042 | static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) |
| 1043 | { |
| 1044 | s32 status; |
| 1045 | u32 i = 0; |
| 1046 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1047 | u32 timeout = 10; |
| 1048 | bool ack = 1; |
| 1049 | |
| 1050 | status = ixgbe_raise_i2c_clk(hw, &i2cctl); |
| 1051 | |
| 1052 | if (status != 0) |
| 1053 | goto out; |
| 1054 | |
| 1055 | /* Minimum high period of clock is 4us */ |
| 1056 | udelay(IXGBE_I2C_T_HIGH); |
| 1057 | |
| 1058 | /* Poll for ACK. Note that ACK in I2C spec is |
| 1059 | * transition from 1 to 0 */ |
| 1060 | for (i = 0; i < timeout; i++) { |
| 1061 | i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1062 | ack = ixgbe_get_i2c_data(&i2cctl); |
| 1063 | |
| 1064 | udelay(1); |
| 1065 | if (ack == 0) |
| 1066 | break; |
| 1067 | } |
| 1068 | |
| 1069 | if (ack == 1) { |
| 1070 | hw_dbg(hw, "I2C ack was not received.\n"); |
| 1071 | status = IXGBE_ERR_I2C; |
| 1072 | } |
| 1073 | |
| 1074 | ixgbe_lower_i2c_clk(hw, &i2cctl); |
| 1075 | |
| 1076 | /* Minimum low period of clock is 4.7 us */ |
| 1077 | udelay(IXGBE_I2C_T_LOW); |
| 1078 | |
| 1079 | out: |
| 1080 | return status; |
| 1081 | } |
| 1082 | |
| 1083 | /** |
| 1084 | * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock |
| 1085 | * @hw: pointer to hardware structure |
| 1086 | * @data: read data value |
| 1087 | * |
| 1088 | * Clocks in one bit via I2C data/clock |
| 1089 | **/ |
| 1090 | static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) |
| 1091 | { |
| 1092 | s32 status; |
| 1093 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1094 | |
| 1095 | status = ixgbe_raise_i2c_clk(hw, &i2cctl); |
| 1096 | |
| 1097 | /* Minimum high period of clock is 4us */ |
| 1098 | udelay(IXGBE_I2C_T_HIGH); |
| 1099 | |
| 1100 | i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1101 | *data = ixgbe_get_i2c_data(&i2cctl); |
| 1102 | |
| 1103 | ixgbe_lower_i2c_clk(hw, &i2cctl); |
| 1104 | |
| 1105 | /* Minimum low period of clock is 4.7 us */ |
| 1106 | udelay(IXGBE_I2C_T_LOW); |
| 1107 | |
| 1108 | return status; |
| 1109 | } |
| 1110 | |
| 1111 | /** |
| 1112 | * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock |
| 1113 | * @hw: pointer to hardware structure |
| 1114 | * @data: data value to write |
| 1115 | * |
| 1116 | * Clocks out one bit via I2C data/clock |
| 1117 | **/ |
| 1118 | static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) |
| 1119 | { |
| 1120 | s32 status; |
| 1121 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1122 | |
| 1123 | status = ixgbe_set_i2c_data(hw, &i2cctl, data); |
| 1124 | if (status == 0) { |
| 1125 | status = ixgbe_raise_i2c_clk(hw, &i2cctl); |
| 1126 | |
| 1127 | /* Minimum high period of clock is 4us */ |
| 1128 | udelay(IXGBE_I2C_T_HIGH); |
| 1129 | |
| 1130 | ixgbe_lower_i2c_clk(hw, &i2cctl); |
| 1131 | |
| 1132 | /* Minimum low period of clock is 4.7 us. |
| 1133 | * This also takes care of the data hold time. |
| 1134 | */ |
| 1135 | udelay(IXGBE_I2C_T_LOW); |
| 1136 | } else { |
| 1137 | status = IXGBE_ERR_I2C; |
| 1138 | hw_dbg(hw, "I2C data was not set to %X\n", data); |
| 1139 | } |
| 1140 | |
| 1141 | return status; |
| 1142 | } |
| 1143 | /** |
| 1144 | * ixgbe_raise_i2c_clk - Raises the I2C SCL clock |
| 1145 | * @hw: pointer to hardware structure |
| 1146 | * @i2cctl: Current value of I2CCTL register |
| 1147 | * |
| 1148 | * Raises the I2C clock line '0'->'1' |
| 1149 | **/ |
| 1150 | static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) |
| 1151 | { |
| 1152 | s32 status = 0; |
| 1153 | |
| 1154 | *i2cctl |= IXGBE_I2C_CLK_OUT; |
| 1155 | |
| 1156 | IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); |
| 1157 | |
| 1158 | /* SCL rise time (1000ns) */ |
| 1159 | udelay(IXGBE_I2C_T_RISE); |
| 1160 | |
| 1161 | return status; |
| 1162 | } |
| 1163 | |
| 1164 | /** |
| 1165 | * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock |
| 1166 | * @hw: pointer to hardware structure |
| 1167 | * @i2cctl: Current value of I2CCTL register |
| 1168 | * |
| 1169 | * Lowers the I2C clock line '1'->'0' |
| 1170 | **/ |
| 1171 | static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) |
| 1172 | { |
| 1173 | |
| 1174 | *i2cctl &= ~IXGBE_I2C_CLK_OUT; |
| 1175 | |
| 1176 | IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); |
| 1177 | |
| 1178 | /* SCL fall time (300ns) */ |
| 1179 | udelay(IXGBE_I2C_T_FALL); |
| 1180 | } |
| 1181 | |
| 1182 | /** |
| 1183 | * ixgbe_set_i2c_data - Sets the I2C data bit |
| 1184 | * @hw: pointer to hardware structure |
| 1185 | * @i2cctl: Current value of I2CCTL register |
| 1186 | * @data: I2C data value (0 or 1) to set |
| 1187 | * |
| 1188 | * Sets the I2C data bit |
| 1189 | **/ |
| 1190 | static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) |
| 1191 | { |
| 1192 | s32 status = 0; |
| 1193 | |
| 1194 | if (data) |
| 1195 | *i2cctl |= IXGBE_I2C_DATA_OUT; |
| 1196 | else |
| 1197 | *i2cctl &= ~IXGBE_I2C_DATA_OUT; |
| 1198 | |
| 1199 | IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); |
| 1200 | |
| 1201 | /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ |
| 1202 | udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); |
| 1203 | |
| 1204 | /* Verify data was set correctly */ |
| 1205 | *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1206 | if (data != ixgbe_get_i2c_data(i2cctl)) { |
| 1207 | status = IXGBE_ERR_I2C; |
| 1208 | hw_dbg(hw, "Error - I2C data was not set to %X.\n", data); |
| 1209 | } |
| 1210 | |
| 1211 | return status; |
| 1212 | } |
| 1213 | |
| 1214 | /** |
| 1215 | * ixgbe_get_i2c_data - Reads the I2C SDA data bit |
| 1216 | * @hw: pointer to hardware structure |
| 1217 | * @i2cctl: Current value of I2CCTL register |
| 1218 | * |
| 1219 | * Returns the I2C data bit value |
| 1220 | **/ |
| 1221 | static bool ixgbe_get_i2c_data(u32 *i2cctl) |
| 1222 | { |
| 1223 | bool data; |
| 1224 | |
| 1225 | if (*i2cctl & IXGBE_I2C_DATA_IN) |
| 1226 | data = 1; |
| 1227 | else |
| 1228 | data = 0; |
| 1229 | |
| 1230 | return data; |
| 1231 | } |
| 1232 | |
| 1233 | /** |
| 1234 | * ixgbe_i2c_bus_clear - Clears the I2C bus |
| 1235 | * @hw: pointer to hardware structure |
| 1236 | * |
| 1237 | * Clears the I2C bus by sending nine clock pulses. |
| 1238 | * Used when data line is stuck low. |
| 1239 | **/ |
| 1240 | static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) |
| 1241 | { |
| 1242 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1243 | u32 i; |
| 1244 | |
| 1245 | ixgbe_set_i2c_data(hw, &i2cctl, 1); |
| 1246 | |
| 1247 | for (i = 0; i < 9; i++) { |
| 1248 | ixgbe_raise_i2c_clk(hw, &i2cctl); |
| 1249 | |
| 1250 | /* Min high period of clock is 4us */ |
| 1251 | udelay(IXGBE_I2C_T_HIGH); |
| 1252 | |
| 1253 | ixgbe_lower_i2c_clk(hw, &i2cctl); |
| 1254 | |
| 1255 | /* Min low period of clock is 4.7us*/ |
| 1256 | udelay(IXGBE_I2C_T_LOW); |
| 1257 | } |
| 1258 | |
| 1259 | /* Put the i2c bus back to default state */ |
| 1260 | ixgbe_i2c_stop(hw); |
| 1261 | } |
| 1262 | |
| 1263 | /** |
Jesse Brandeburg | 0befdb3 | 2008-10-31 00:46:40 -0700 | [diff] [blame] | 1264 | * ixgbe_check_phy_link_tnx - Determine link and speed status |
| 1265 | * @hw: pointer to hardware structure |
| 1266 | * |
| 1267 | * Reads the VS1 register to determine if link is up and the current speed for |
| 1268 | * the PHY. |
| 1269 | **/ |
| 1270 | s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, |
| 1271 | bool *link_up) |
| 1272 | { |
| 1273 | s32 status = 0; |
| 1274 | u32 time_out; |
| 1275 | u32 max_time_out = 10; |
| 1276 | u16 phy_link = 0; |
| 1277 | u16 phy_speed = 0; |
| 1278 | u16 phy_data = 0; |
| 1279 | |
| 1280 | /* Initialize speed and link to default case */ |
| 1281 | *link_up = false; |
| 1282 | *speed = IXGBE_LINK_SPEED_10GB_FULL; |
| 1283 | |
| 1284 | /* |
| 1285 | * Check current speed and link status of the PHY register. |
| 1286 | * This is a vendor specific register and may have to |
| 1287 | * be changed for other copper PHYs. |
| 1288 | */ |
| 1289 | for (time_out = 0; time_out < max_time_out; time_out++) { |
| 1290 | udelay(10); |
| 1291 | status = hw->phy.ops.read_reg(hw, |
| 1292 | IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, |
| 1293 | IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, |
| 1294 | &phy_data); |
| 1295 | phy_link = phy_data & |
| 1296 | IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; |
| 1297 | phy_speed = phy_data & |
| 1298 | IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; |
| 1299 | if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { |
| 1300 | *link_up = true; |
| 1301 | if (phy_speed == |
| 1302 | IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) |
| 1303 | *speed = IXGBE_LINK_SPEED_1GB_FULL; |
| 1304 | break; |
| 1305 | } |
| 1306 | } |
| 1307 | |
| 1308 | return status; |
| 1309 | } |
| 1310 | |
| 1311 | /** |
| 1312 | * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version |
| 1313 | * @hw: pointer to hardware structure |
| 1314 | * @firmware_version: pointer to the PHY Firmware Version |
| 1315 | **/ |
| 1316 | s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, |
| 1317 | u16 *firmware_version) |
| 1318 | { |
| 1319 | s32 status = 0; |
| 1320 | |
| 1321 | status = hw->phy.ops.read_reg(hw, TNX_FW_REV, |
| 1322 | IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, |
| 1323 | firmware_version); |
| 1324 | |
| 1325 | return status; |
| 1326 | } |
| 1327 | |