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gerrit-public.fairphone.software / kernel / msm-5.4 / 049d34e94f9aa2c3ed22a7bad75dd188ec7dacb9 / . / drivers / gpu / drm / exynos / exynos_hdmi.c
blob: 941b235ca1db66c23e7c8bdf36d7f76b1afcacb0 [file] [log] [blame]
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1/*
2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
3 * Authors:
4 * Seung-Woo Kim <sw0312.kim@samsung.com>
5 * Inki Dae <inki.dae@samsung.com>
6 * Joonyoung Shim <jy0922.shim@samsung.com>
7 *
8 * Based on drivers/media/video/s5p-tv/hdmi_drv.c
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
David Howells760285e2012-10-02 18:01:07 +0100[diff] [blame]17#include <drm/drmP.h>
18#include <drm/drm_edid.h>
19#include <drm/drm_crtc_helper.h>
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]20
21#include "regs-hdmi.h"
22
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
25#include <linux/wait.h>
26#include <linux/i2c.h>
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]27#include <linux/platform_device.h>
28#include <linux/interrupt.h>
29#include <linux/irq.h>
30#include <linux/delay.h>
31#include <linux/pm_runtime.h>
32#include <linux/clk.h>
33#include <linux/regulator/consumer.h>
Rahul Sharma22c4f422012-10-04 20:48:55 +0530[diff] [blame]34#include <linux/io.h>
Sachin Kamat3f1c7812013-08-14 16:38:01 +0530[diff] [blame]35#include <linux/of.h>
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]36#include <linux/of_address.h>
Daniel Kurtz2b768132014-02-24 18:52:51 +0900[diff] [blame]37#include <linux/i2c.h>
Rahul Sharma22c4f422012-10-04 20:48:55 +0530[diff] [blame]38#include <linux/of_gpio.h>
Sachin Kamatd34d59b2014-02-04 08:40:18 +0530[diff] [blame]39#include <linux/hdmi.h>
Inki Daef37cd5e2014-05-09 14:25:20 +0900[diff] [blame]40#include <linux/component.h>
Rahul Sharma049d34e2014-05-20 10:36:05 +0530[diff] [blame^]41#include <linux/mfd/syscon.h>
42#include <linux/regmap.h>
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]43
44#include <drm/exynos_drm.h>
45
46#include "exynos_drm_drv.h"
Inki Daef37cd5e2014-05-09 14:25:20 +0900[diff] [blame]47#include "exynos_drm_crtc.h"
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]48#include "exynos_mixer.h"
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]49
Tomasz Stanislawskifca57122012-10-04 20:48:46 +0530[diff] [blame]50#include <linux/gpio.h>
51#include <media/s5p_hdmi.h>
52
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]53#define get_hdmi_display(dev) platform_get_drvdata(to_platform_device(dev))
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]54#define ctx_from_connector(c) container_of(c, struct hdmi_context, connector)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]55
Sean Paul724fd142014-05-09 15:05:10 +0900[diff] [blame]56#define HOTPLUG_DEBOUNCE_MS 1100
57
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]58/* AVI header and aspect ratio */
59#define HDMI_AVI_VERSION 0x02
60#define HDMI_AVI_LENGTH 0x0D
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]61
62/* AUI header info */
63#define HDMI_AUI_VERSION 0x01
64#define HDMI_AUI_LENGTH 0x0A
Shirish S46154152014-03-13 10:58:28 +0530[diff] [blame]65#define AVI_SAME_AS_PIC_ASPECT_RATIO 0x8
66#define AVI_4_3_CENTER_RATIO 0x9
67#define AVI_16_9_CENTER_RATIO 0xa
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]68
Rahul Sharma5a325072012-10-04 20:48:54 +0530[diff] [blame]69enum hdmi_type {
70 HDMI_TYPE13,
71 HDMI_TYPE14,
72};
73
Inki Daebfe4e842014-03-06 14:18:17 +0900[diff] [blame]74struct hdmi_driver_data {
75 unsigned int type;
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]76 const struct hdmiphy_config *phy_confs;
77 unsigned int phy_conf_count;
Inki Daebfe4e842014-03-06 14:18:17 +0900[diff] [blame]78 unsigned int is_apb_phy:1;
79};
80
Joonyoung Shim590f4182012-03-16 18:47:14 +0900[diff] [blame]81struct hdmi_resources {
82 struct clk *hdmi;
83 struct clk *sclk_hdmi;
84 struct clk *sclk_pixel;
85 struct clk *sclk_hdmiphy;
Rahul Sharma59956d32013-06-11 12:24:03 +0530[diff] [blame]86 struct clk *mout_hdmi;
Joonyoung Shim590f4182012-03-16 18:47:14 +0900[diff] [blame]87 struct regulator_bulk_data *regul_bulk;
88 int regul_count;
89};
90
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]91struct hdmi_tg_regs {
92 u8 cmd[1];
93 u8 h_fsz[2];
94 u8 hact_st[2];
95 u8 hact_sz[2];
96 u8 v_fsz[2];
97 u8 vsync[2];
98 u8 vsync2[2];
99 u8 vact_st[2];
100 u8 vact_sz[2];
101 u8 field_chg[2];
102 u8 vact_st2[2];
103 u8 vact_st3[2];
104 u8 vact_st4[2];
105 u8 vsync_top_hdmi[2];
106 u8 vsync_bot_hdmi[2];
107 u8 field_top_hdmi[2];
108 u8 field_bot_hdmi[2];
109 u8 tg_3d[1];
110};
111
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]112struct hdmi_v13_core_regs {
113 u8 h_blank[2];
114 u8 v_blank[3];
115 u8 h_v_line[3];
116 u8 vsync_pol[1];
117 u8 int_pro_mode[1];
118 u8 v_blank_f[3];
119 u8 h_sync_gen[3];
120 u8 v_sync_gen1[3];
121 u8 v_sync_gen2[3];
122 u8 v_sync_gen3[3];
123};
124
125struct hdmi_v14_core_regs {
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]126 u8 h_blank[2];
127 u8 v2_blank[2];
128 u8 v1_blank[2];
129 u8 v_line[2];
130 u8 h_line[2];
131 u8 hsync_pol[1];
132 u8 vsync_pol[1];
133 u8 int_pro_mode[1];
134 u8 v_blank_f0[2];
135 u8 v_blank_f1[2];
136 u8 h_sync_start[2];
137 u8 h_sync_end[2];
138 u8 v_sync_line_bef_2[2];
139 u8 v_sync_line_bef_1[2];
140 u8 v_sync_line_aft_2[2];
141 u8 v_sync_line_aft_1[2];
142 u8 v_sync_line_aft_pxl_2[2];
143 u8 v_sync_line_aft_pxl_1[2];
144 u8 v_blank_f2[2]; /* for 3D mode */
145 u8 v_blank_f3[2]; /* for 3D mode */
146 u8 v_blank_f4[2]; /* for 3D mode */
147 u8 v_blank_f5[2]; /* for 3D mode */
148 u8 v_sync_line_aft_3[2];
149 u8 v_sync_line_aft_4[2];
150 u8 v_sync_line_aft_5[2];
151 u8 v_sync_line_aft_6[2];
152 u8 v_sync_line_aft_pxl_3[2];
153 u8 v_sync_line_aft_pxl_4[2];
154 u8 v_sync_line_aft_pxl_5[2];
155 u8 v_sync_line_aft_pxl_6[2];
156 u8 vact_space_1[2];
157 u8 vact_space_2[2];
158 u8 vact_space_3[2];
159 u8 vact_space_4[2];
160 u8 vact_space_5[2];
161 u8 vact_space_6[2];
162};
163
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]164struct hdmi_v13_conf {
165 struct hdmi_v13_core_regs core;
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]166 struct hdmi_tg_regs tg;
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]167};
168
169struct hdmi_v14_conf {
170 struct hdmi_v14_core_regs core;
171 struct hdmi_tg_regs tg;
172};
173
174struct hdmi_conf_regs {
175 int pixel_clock;
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]176 int cea_video_id;
Shirish S46154152014-03-13 10:58:28 +0530[diff] [blame]177 enum hdmi_picture_aspect aspect_ratio;
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]178 union {
179 struct hdmi_v13_conf v13_conf;
180 struct hdmi_v14_conf v14_conf;
181 } conf;
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]182};
183
Joonyoung Shim590f4182012-03-16 18:47:14 +0900[diff] [blame]184struct hdmi_context {
185 struct device *dev;
186 struct drm_device *drm_dev;
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]187 struct drm_connector connector;
188 struct drm_encoder *encoder;
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]189 bool hpd;
190 bool powered;
Seung-Woo Kim872d20d62012-04-24 17:39:15 +0900[diff] [blame]191 bool dvi_mode;
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]192 struct mutex hdmi_mutex;
Joonyoung Shim590f4182012-03-16 18:47:14 +0900[diff] [blame]193
Joonyoung Shim590f4182012-03-16 18:47:14 +0900[diff] [blame]194 void __iomem *regs;
Sean Paul77006a72013-01-16 10:17:20 -0500[diff] [blame]195 int irq;
Sean Paul724fd142014-05-09 15:05:10 +0900[diff] [blame]196 struct delayed_work hotplug_work;
Joonyoung Shim590f4182012-03-16 18:47:14 +0900[diff] [blame]197
Inki Dae8fa04aa2014-03-13 16:38:31 +0900[diff] [blame]198 struct i2c_adapter *ddc_adpt;
Joonyoung Shim590f4182012-03-16 18:47:14 +0900[diff] [blame]199 struct i2c_client *hdmiphy_port;
200
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]201 /* current hdmiphy conf regs */
Rahul Sharmabfa48422014-04-03 20:41:04 +0530[diff] [blame]202 struct drm_display_mode current_mode;
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]203 struct hdmi_conf_regs mode_conf;
Joonyoung Shim590f4182012-03-16 18:47:14 +0900[diff] [blame]204
205 struct hdmi_resources res;
Joonyoung Shim7ecd34e2012-04-23 19:35:47 +0900[diff] [blame]206
Tomasz Stanislawskifca57122012-10-04 20:48:46 +0530[diff] [blame]207 int hpd_gpio;
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]208 void __iomem *regs_hdmiphy;
209 const struct hdmiphy_config *phy_confs;
210 unsigned int phy_conf_count;
Rahul Sharma5a325072012-10-04 20:48:54 +0530[diff] [blame]211
Rahul Sharma049d34e2014-05-20 10:36:05 +0530[diff] [blame^]212 struct regmap *pmureg;
Rahul Sharma5a325072012-10-04 20:48:54 +0530[diff] [blame]213 enum hdmi_type type;
Joonyoung Shim590f4182012-03-16 18:47:14 +0900[diff] [blame]214};
215
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]216struct hdmiphy_config {
217 int pixel_clock;
218 u8 conf[32];
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]219};
220
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]221/* list of phy config settings */
222static const struct hdmiphy_config hdmiphy_v13_configs[] = {
223 {
224 .pixel_clock = 27000000,
225 .conf = {
226 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
227 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
228 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
229 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
230 },
231 },
232 {
233 .pixel_clock = 27027000,
234 .conf = {
235 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
236 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
237 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
238 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
239 },
240 },
241 {
242 .pixel_clock = 74176000,
243 .conf = {
244 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
245 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
246 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
247 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00,
248 },
249 },
250 {
251 .pixel_clock = 74250000,
252 .conf = {
253 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
254 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
255 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
256 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00,
257 },
258 },
259 {
260 .pixel_clock = 148500000,
261 .conf = {
262 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
263 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
264 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
265 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00,
266 },
267 },
268};
269
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]270static const struct hdmiphy_config hdmiphy_v14_configs[] = {
271 {
272 .pixel_clock = 25200000,
273 .conf = {
274 0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
275 0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
276 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
277 0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
278 },
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]279 },
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]280 {
281 .pixel_clock = 27000000,
282 .conf = {
283 0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
284 0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
285 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
286 0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
287 },
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]288 },
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]289 {
290 .pixel_clock = 27027000,
291 .conf = {
292 0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
293 0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
294 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
295 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
296 },
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]297 },
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]298 {
299 .pixel_clock = 36000000,
300 .conf = {
301 0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
302 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
303 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
304 0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
305 },
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]306 },
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]307 {
308 .pixel_clock = 40000000,
309 .conf = {
310 0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
311 0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
312 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
313 0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
314 },
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]315 },
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]316 {
317 .pixel_clock = 65000000,
318 .conf = {
319 0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08,
320 0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80,
321 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
322 0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
323 },
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]324 },
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]325 {
Shirish Se1d883c2014-03-13 14:28:27 +0900[diff] [blame]326 .pixel_clock = 71000000,
327 .conf = {
Shirish S96d26532014-05-05 10:27:51 +0530[diff] [blame]328 0x01, 0xd1, 0x3b, 0x35, 0x40, 0x0c, 0x04, 0x08,
329 0x85, 0xa0, 0x63, 0xd9, 0x45, 0xa0, 0xac, 0x80,
330 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
Shirish Se1d883c2014-03-13 14:28:27 +0900[diff] [blame]331 0x54, 0xad, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
332 },
333 },
334 {
335 .pixel_clock = 73250000,
336 .conf = {
Shirish S96d26532014-05-05 10:27:51 +0530[diff] [blame]337 0x01, 0xd1, 0x3d, 0x35, 0x40, 0x18, 0x02, 0x08,
338 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
339 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
Shirish Se1d883c2014-03-13 14:28:27 +0900[diff] [blame]340 0x54, 0xa8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
341 },
342 },
343 {
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]344 .pixel_clock = 74176000,
345 .conf = {
346 0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
347 0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80,
348 0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
349 0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
350 },
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]351 },
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]352 {
353 .pixel_clock = 74250000,
354 .conf = {
355 0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
356 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
357 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
358 0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
359 },
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]360 },
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]361 {
362 .pixel_clock = 83500000,
363 .conf = {
364 0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08,
365 0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80,
366 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
367 0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
368 },
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]369 },
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]370 {
371 .pixel_clock = 106500000,
372 .conf = {
373 0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
374 0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
375 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
376 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
377 },
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]378 },
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]379 {
380 .pixel_clock = 108000000,
381 .conf = {
382 0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08,
383 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
384 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
385 0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
386 },
Seung-Woo Kime540adf2012-04-24 17:55:06 +0900[diff] [blame]387 },
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]388 {
Shirish Se1d883c2014-03-13 14:28:27 +0900[diff] [blame]389 .pixel_clock = 115500000,
390 .conf = {
Shirish S96d26532014-05-05 10:27:51 +0530[diff] [blame]391 0x01, 0xd1, 0x30, 0x12, 0x40, 0x40, 0x10, 0x08,
392 0x80, 0x80, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80,
393 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
Shirish Se1d883c2014-03-13 14:28:27 +0900[diff] [blame]394 0x54, 0xaa, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
395 },
396 },
397 {
398 .pixel_clock = 119000000,
399 .conf = {
Shirish S96d26532014-05-05 10:27:51 +0530[diff] [blame]400 0x01, 0xd1, 0x32, 0x1a, 0x40, 0x30, 0xd8, 0x08,
401 0x04, 0xa0, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
402 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
Shirish Se1d883c2014-03-13 14:28:27 +0900[diff] [blame]403 0x54, 0x9d, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
404 },
405 },
406 {
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]407 .pixel_clock = 146250000,
408 .conf = {
409 0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,
410 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
411 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
412 0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
413 },
Seung-Woo Kime540adf2012-04-24 17:55:06 +0900[diff] [blame]414 },
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]415 {
416 .pixel_clock = 148500000,
417 .conf = {
418 0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
419 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
420 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
421 0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
422 },
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]423 },
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]424};
425
Rahul Sharmaa18a2dd2014-04-20 15:51:17 +0530[diff] [blame]426static const struct hdmiphy_config hdmiphy_5420_configs[] = {
427 {
428 .pixel_clock = 25200000,
429 .conf = {
430 0x01, 0x52, 0x3F, 0x55, 0x40, 0x01, 0x00, 0xC8,
431 0x82, 0xC8, 0xBD, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
432 0x06, 0x80, 0x01, 0x84, 0x05, 0x02, 0x24, 0x66,
433 0x54, 0xF4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
434 },
435 },
436 {
437 .pixel_clock = 27000000,
438 .conf = {
439 0x01, 0xD1, 0x22, 0x51, 0x40, 0x08, 0xFC, 0xE0,
440 0x98, 0xE8, 0xCB, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
441 0x06, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
442 0x54, 0xE4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
443 },
444 },
445 {
446 .pixel_clock = 27027000,
447 .conf = {
448 0x01, 0xD1, 0x2D, 0x72, 0x40, 0x64, 0x12, 0xC8,
449 0x43, 0xE8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
450 0x26, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
451 0x54, 0xE3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
452 },
453 },
454 {
455 .pixel_clock = 36000000,
456 .conf = {
457 0x01, 0x51, 0x2D, 0x55, 0x40, 0x40, 0x00, 0xC8,
458 0x02, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
459 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
460 0x54, 0xAB, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
461 },
462 },
463 {
464 .pixel_clock = 40000000,
465 .conf = {
466 0x01, 0xD1, 0x21, 0x31, 0x40, 0x3C, 0x28, 0xC8,
467 0x87, 0xE8, 0xC8, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
468 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
469 0x54, 0x9A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
470 },
471 },
472 {
473 .pixel_clock = 65000000,
474 .conf = {
475 0x01, 0xD1, 0x36, 0x34, 0x40, 0x0C, 0x04, 0xC8,
476 0x82, 0xE8, 0x45, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
477 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
478 0x54, 0xBD, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
479 },
480 },
481 {
482 .pixel_clock = 71000000,
483 .conf = {
484 0x01, 0xD1, 0x3B, 0x35, 0x40, 0x0C, 0x04, 0xC8,
485 0x85, 0xE8, 0x63, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
486 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
487 0x54, 0x57, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
488 },
489 },
490 {
491 .pixel_clock = 73250000,
492 .conf = {
493 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x78, 0x8D, 0xC8,
494 0x81, 0xE8, 0xB7, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
495 0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
496 0x54, 0xA8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
497 },
498 },
499 {
500 .pixel_clock = 74176000,
501 .conf = {
502 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x5B, 0xEF, 0xC8,
503 0x81, 0xE8, 0xB9, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
504 0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
505 0x54, 0xA6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
506 },
507 },
508 {
509 .pixel_clock = 74250000,
510 .conf = {
511 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x40, 0xF8, 0x08,
512 0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
513 0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66,
514 0x54, 0xA5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
515 },
516 },
517 {
518 .pixel_clock = 83500000,
519 .conf = {
520 0x01, 0xD1, 0x23, 0x11, 0x40, 0x0C, 0xFB, 0xC8,
521 0x85, 0xE8, 0xD1, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
522 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
523 0x54, 0x4A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
524 },
525 },
526 {
527 .pixel_clock = 88750000,
528 .conf = {
529 0x01, 0xD1, 0x25, 0x11, 0x40, 0x18, 0xFF, 0xC8,
530 0x83, 0xE8, 0xDE, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
531 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
532 0x54, 0x45, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
533 },
534 },
535 {
536 .pixel_clock = 106500000,
537 .conf = {
538 0x01, 0xD1, 0x2C, 0x12, 0x40, 0x0C, 0x09, 0xC8,
539 0x84, 0xE8, 0x0A, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
540 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
541 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
542 },
543 },
544 {
545 .pixel_clock = 108000000,
546 .conf = {
547 0x01, 0x51, 0x2D, 0x15, 0x40, 0x01, 0x00, 0xC8,
548 0x82, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
549 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
550 0x54, 0xC7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
551 },
552 },
553 {
554 .pixel_clock = 115500000,
555 .conf = {
556 0x01, 0xD1, 0x30, 0x14, 0x40, 0x0C, 0x03, 0xC8,
557 0x88, 0xE8, 0x21, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
558 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
559 0x54, 0x6A, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
560 },
561 },
562 {
563 .pixel_clock = 146250000,
564 .conf = {
565 0x01, 0xD1, 0x3D, 0x15, 0x40, 0x18, 0xFD, 0xC8,
566 0x83, 0xE8, 0x6E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
567 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
568 0x54, 0x54, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
569 },
570 },
571 {
572 .pixel_clock = 148500000,
573 .conf = {
574 0x01, 0xD1, 0x1F, 0x00, 0x40, 0x40, 0xF8, 0x08,
575 0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
576 0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66,
577 0x54, 0x4B, 0x25, 0x03, 0x00, 0x80, 0x01, 0x80,
578 },
579 },
580};
581
582struct hdmi_driver_data exynos5420_hdmi_driver_data = {
583 .type = HDMI_TYPE14,
584 .phy_confs = hdmiphy_5420_configs,
585 .phy_conf_count = ARRAY_SIZE(hdmiphy_5420_configs),
586 .is_apb_phy = 1,
587};
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]588
589struct hdmi_driver_data exynos4212_hdmi_driver_data = {
590 .type = HDMI_TYPE14,
591 .phy_confs = hdmiphy_v14_configs,
592 .phy_conf_count = ARRAY_SIZE(hdmiphy_v14_configs),
593 .is_apb_phy = 0,
594};
595
596struct hdmi_driver_data exynos5_hdmi_driver_data = {
597 .type = HDMI_TYPE14,
598 .phy_confs = hdmiphy_v13_configs,
599 .phy_conf_count = ARRAY_SIZE(hdmiphy_v13_configs),
600 .is_apb_phy = 0,
601};
602
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]603static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
604{
605 return readl(hdata->regs + reg_id);
606}
607
608static inline void hdmi_reg_writeb(struct hdmi_context *hdata,
609 u32 reg_id, u8 value)
610{
611 writeb(value, hdata->regs + reg_id);
612}
613
614static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
615 u32 reg_id, u32 value, u32 mask)
616{
617 u32 old = readl(hdata->regs + reg_id);
618 value = (value & mask) | (old & ~mask);
619 writel(value, hdata->regs + reg_id);
620}
621
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]622static int hdmiphy_reg_writeb(struct hdmi_context *hdata,
623 u32 reg_offset, u8 value)
624{
625 if (hdata->hdmiphy_port) {
626 u8 buffer[2];
627 int ret;
628
629 buffer[0] = reg_offset;
630 buffer[1] = value;
631
632 ret = i2c_master_send(hdata->hdmiphy_port, buffer, 2);
633 if (ret == 2)
634 return 0;
635 return ret;
636 } else {
637 writeb(value, hdata->regs_hdmiphy + (reg_offset<<2));
638 return 0;
639 }
640}
641
642static int hdmiphy_reg_write_buf(struct hdmi_context *hdata,
643 u32 reg_offset, const u8 *buf, u32 len)
644{
645 if ((reg_offset + len) > 32)
646 return -EINVAL;
647
648 if (hdata->hdmiphy_port) {
649 int ret;
650
651 ret = i2c_master_send(hdata->hdmiphy_port, buf, len);
652 if (ret == len)
653 return 0;
654 return ret;
655 } else {
656 int i;
657 for (i = 0; i < len; i++)
658 writeb(buf[i], hdata->regs_hdmiphy +
659 ((reg_offset + i)<<2));
660 return 0;
661 }
662}
663
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]664static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]665{
666#define DUMPREG(reg_id) \
667 DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
668 readl(hdata->regs + reg_id))
669 DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
670 DUMPREG(HDMI_INTC_FLAG);
671 DUMPREG(HDMI_INTC_CON);
672 DUMPREG(HDMI_HPD_STATUS);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]673 DUMPREG(HDMI_V13_PHY_RSTOUT);
674 DUMPREG(HDMI_V13_PHY_VPLL);
675 DUMPREG(HDMI_V13_PHY_CMU);
676 DUMPREG(HDMI_V13_CORE_RSTOUT);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]677
678 DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
679 DUMPREG(HDMI_CON_0);
680 DUMPREG(HDMI_CON_1);
681 DUMPREG(HDMI_CON_2);
682 DUMPREG(HDMI_SYS_STATUS);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]683 DUMPREG(HDMI_V13_PHY_STATUS);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]684 DUMPREG(HDMI_STATUS_EN);
685 DUMPREG(HDMI_HPD);
686 DUMPREG(HDMI_MODE_SEL);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]687 DUMPREG(HDMI_V13_HPD_GEN);
688 DUMPREG(HDMI_V13_DC_CONTROL);
689 DUMPREG(HDMI_V13_VIDEO_PATTERN_GEN);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]690
691 DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
692 DUMPREG(HDMI_H_BLANK_0);
693 DUMPREG(HDMI_H_BLANK_1);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]694 DUMPREG(HDMI_V13_V_BLANK_0);
695 DUMPREG(HDMI_V13_V_BLANK_1);
696 DUMPREG(HDMI_V13_V_BLANK_2);
697 DUMPREG(HDMI_V13_H_V_LINE_0);
698 DUMPREG(HDMI_V13_H_V_LINE_1);
699 DUMPREG(HDMI_V13_H_V_LINE_2);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]700 DUMPREG(HDMI_VSYNC_POL);
701 DUMPREG(HDMI_INT_PRO_MODE);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]702 DUMPREG(HDMI_V13_V_BLANK_F_0);
703 DUMPREG(HDMI_V13_V_BLANK_F_1);
704 DUMPREG(HDMI_V13_V_BLANK_F_2);
705 DUMPREG(HDMI_V13_H_SYNC_GEN_0);
706 DUMPREG(HDMI_V13_H_SYNC_GEN_1);
707 DUMPREG(HDMI_V13_H_SYNC_GEN_2);
708 DUMPREG(HDMI_V13_V_SYNC_GEN_1_0);
709 DUMPREG(HDMI_V13_V_SYNC_GEN_1_1);
710 DUMPREG(HDMI_V13_V_SYNC_GEN_1_2);
711 DUMPREG(HDMI_V13_V_SYNC_GEN_2_0);
712 DUMPREG(HDMI_V13_V_SYNC_GEN_2_1);
713 DUMPREG(HDMI_V13_V_SYNC_GEN_2_2);
714 DUMPREG(HDMI_V13_V_SYNC_GEN_3_0);
715 DUMPREG(HDMI_V13_V_SYNC_GEN_3_1);
716 DUMPREG(HDMI_V13_V_SYNC_GEN_3_2);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]717
718 DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
719 DUMPREG(HDMI_TG_CMD);
720 DUMPREG(HDMI_TG_H_FSZ_L);
721 DUMPREG(HDMI_TG_H_FSZ_H);
722 DUMPREG(HDMI_TG_HACT_ST_L);
723 DUMPREG(HDMI_TG_HACT_ST_H);
724 DUMPREG(HDMI_TG_HACT_SZ_L);
725 DUMPREG(HDMI_TG_HACT_SZ_H);
726 DUMPREG(HDMI_TG_V_FSZ_L);
727 DUMPREG(HDMI_TG_V_FSZ_H);
728 DUMPREG(HDMI_TG_VSYNC_L);
729 DUMPREG(HDMI_TG_VSYNC_H);
730 DUMPREG(HDMI_TG_VSYNC2_L);
731 DUMPREG(HDMI_TG_VSYNC2_H);
732 DUMPREG(HDMI_TG_VACT_ST_L);
733 DUMPREG(HDMI_TG_VACT_ST_H);
734 DUMPREG(HDMI_TG_VACT_SZ_L);
735 DUMPREG(HDMI_TG_VACT_SZ_H);
736 DUMPREG(HDMI_TG_FIELD_CHG_L);
737 DUMPREG(HDMI_TG_FIELD_CHG_H);
738 DUMPREG(HDMI_TG_VACT_ST2_L);
739 DUMPREG(HDMI_TG_VACT_ST2_H);
740 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
741 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
742 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
743 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
744 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
745 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
746 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
747 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
748#undef DUMPREG
749}
750
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]751static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix)
752{
753 int i;
754
755#define DUMPREG(reg_id) \
756 DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
757 readl(hdata->regs + reg_id))
758
759 DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
760 DUMPREG(HDMI_INTC_CON);
761 DUMPREG(HDMI_INTC_FLAG);
762 DUMPREG(HDMI_HPD_STATUS);
763 DUMPREG(HDMI_INTC_CON_1);
764 DUMPREG(HDMI_INTC_FLAG_1);
765 DUMPREG(HDMI_PHY_STATUS_0);
766 DUMPREG(HDMI_PHY_STATUS_PLL);
767 DUMPREG(HDMI_PHY_CON_0);
768 DUMPREG(HDMI_PHY_RSTOUT);
769 DUMPREG(HDMI_PHY_VPLL);
770 DUMPREG(HDMI_PHY_CMU);
771 DUMPREG(HDMI_CORE_RSTOUT);
772
773 DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
774 DUMPREG(HDMI_CON_0);
775 DUMPREG(HDMI_CON_1);
776 DUMPREG(HDMI_CON_2);
777 DUMPREG(HDMI_SYS_STATUS);
778 DUMPREG(HDMI_PHY_STATUS_0);
779 DUMPREG(HDMI_STATUS_EN);
780 DUMPREG(HDMI_HPD);
781 DUMPREG(HDMI_MODE_SEL);
782 DUMPREG(HDMI_ENC_EN);
783 DUMPREG(HDMI_DC_CONTROL);
784 DUMPREG(HDMI_VIDEO_PATTERN_GEN);
785
786 DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
787 DUMPREG(HDMI_H_BLANK_0);
788 DUMPREG(HDMI_H_BLANK_1);
789 DUMPREG(HDMI_V2_BLANK_0);
790 DUMPREG(HDMI_V2_BLANK_1);
791 DUMPREG(HDMI_V1_BLANK_0);
792 DUMPREG(HDMI_V1_BLANK_1);
793 DUMPREG(HDMI_V_LINE_0);
794 DUMPREG(HDMI_V_LINE_1);
795 DUMPREG(HDMI_H_LINE_0);
796 DUMPREG(HDMI_H_LINE_1);
797 DUMPREG(HDMI_HSYNC_POL);
798
799 DUMPREG(HDMI_VSYNC_POL);
800 DUMPREG(HDMI_INT_PRO_MODE);
801 DUMPREG(HDMI_V_BLANK_F0_0);
802 DUMPREG(HDMI_V_BLANK_F0_1);
803 DUMPREG(HDMI_V_BLANK_F1_0);
804 DUMPREG(HDMI_V_BLANK_F1_1);
805
806 DUMPREG(HDMI_H_SYNC_START_0);
807 DUMPREG(HDMI_H_SYNC_START_1);
808 DUMPREG(HDMI_H_SYNC_END_0);
809 DUMPREG(HDMI_H_SYNC_END_1);
810
811 DUMPREG(HDMI_V_SYNC_LINE_BEF_2_0);
812 DUMPREG(HDMI_V_SYNC_LINE_BEF_2_1);
813 DUMPREG(HDMI_V_SYNC_LINE_BEF_1_0);
814 DUMPREG(HDMI_V_SYNC_LINE_BEF_1_1);
815
816 DUMPREG(HDMI_V_SYNC_LINE_AFT_2_0);
817 DUMPREG(HDMI_V_SYNC_LINE_AFT_2_1);
818 DUMPREG(HDMI_V_SYNC_LINE_AFT_1_0);
819 DUMPREG(HDMI_V_SYNC_LINE_AFT_1_1);
820
821 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_0);
822 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_1);
823 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_0);
824 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_1);
825
826 DUMPREG(HDMI_V_BLANK_F2_0);
827 DUMPREG(HDMI_V_BLANK_F2_1);
828 DUMPREG(HDMI_V_BLANK_F3_0);
829 DUMPREG(HDMI_V_BLANK_F3_1);
830 DUMPREG(HDMI_V_BLANK_F4_0);
831 DUMPREG(HDMI_V_BLANK_F4_1);
832 DUMPREG(HDMI_V_BLANK_F5_0);
833 DUMPREG(HDMI_V_BLANK_F5_1);
834
835 DUMPREG(HDMI_V_SYNC_LINE_AFT_3_0);
836 DUMPREG(HDMI_V_SYNC_LINE_AFT_3_1);
837 DUMPREG(HDMI_V_SYNC_LINE_AFT_4_0);
838 DUMPREG(HDMI_V_SYNC_LINE_AFT_4_1);
839 DUMPREG(HDMI_V_SYNC_LINE_AFT_5_0);
840 DUMPREG(HDMI_V_SYNC_LINE_AFT_5_1);
841 DUMPREG(HDMI_V_SYNC_LINE_AFT_6_0);
842 DUMPREG(HDMI_V_SYNC_LINE_AFT_6_1);
843
844 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_0);
845 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_1);
846 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_0);
847 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_1);
848 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_0);
849 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_1);
850 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_0);
851 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_1);
852
853 DUMPREG(HDMI_VACT_SPACE_1_0);
854 DUMPREG(HDMI_VACT_SPACE_1_1);
855 DUMPREG(HDMI_VACT_SPACE_2_0);
856 DUMPREG(HDMI_VACT_SPACE_2_1);
857 DUMPREG(HDMI_VACT_SPACE_3_0);
858 DUMPREG(HDMI_VACT_SPACE_3_1);
859 DUMPREG(HDMI_VACT_SPACE_4_0);
860 DUMPREG(HDMI_VACT_SPACE_4_1);
861 DUMPREG(HDMI_VACT_SPACE_5_0);
862 DUMPREG(HDMI_VACT_SPACE_5_1);
863 DUMPREG(HDMI_VACT_SPACE_6_0);
864 DUMPREG(HDMI_VACT_SPACE_6_1);
865
866 DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
867 DUMPREG(HDMI_TG_CMD);
868 DUMPREG(HDMI_TG_H_FSZ_L);
869 DUMPREG(HDMI_TG_H_FSZ_H);
870 DUMPREG(HDMI_TG_HACT_ST_L);
871 DUMPREG(HDMI_TG_HACT_ST_H);
872 DUMPREG(HDMI_TG_HACT_SZ_L);
873 DUMPREG(HDMI_TG_HACT_SZ_H);
874 DUMPREG(HDMI_TG_V_FSZ_L);
875 DUMPREG(HDMI_TG_V_FSZ_H);
876 DUMPREG(HDMI_TG_VSYNC_L);
877 DUMPREG(HDMI_TG_VSYNC_H);
878 DUMPREG(HDMI_TG_VSYNC2_L);
879 DUMPREG(HDMI_TG_VSYNC2_H);
880 DUMPREG(HDMI_TG_VACT_ST_L);
881 DUMPREG(HDMI_TG_VACT_ST_H);
882 DUMPREG(HDMI_TG_VACT_SZ_L);
883 DUMPREG(HDMI_TG_VACT_SZ_H);
884 DUMPREG(HDMI_TG_FIELD_CHG_L);
885 DUMPREG(HDMI_TG_FIELD_CHG_H);
886 DUMPREG(HDMI_TG_VACT_ST2_L);
887 DUMPREG(HDMI_TG_VACT_ST2_H);
888 DUMPREG(HDMI_TG_VACT_ST3_L);
889 DUMPREG(HDMI_TG_VACT_ST3_H);
890 DUMPREG(HDMI_TG_VACT_ST4_L);
891 DUMPREG(HDMI_TG_VACT_ST4_H);
892 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
893 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
894 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
895 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
896 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
897 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
898 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
899 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
900 DUMPREG(HDMI_TG_3D);
901
902 DRM_DEBUG_KMS("%s: ---- PACKET REGISTERS ----\n", prefix);
903 DUMPREG(HDMI_AVI_CON);
904 DUMPREG(HDMI_AVI_HEADER0);
905 DUMPREG(HDMI_AVI_HEADER1);
906 DUMPREG(HDMI_AVI_HEADER2);
907 DUMPREG(HDMI_AVI_CHECK_SUM);
908 DUMPREG(HDMI_VSI_CON);
909 DUMPREG(HDMI_VSI_HEADER0);
910 DUMPREG(HDMI_VSI_HEADER1);
911 DUMPREG(HDMI_VSI_HEADER2);
912 for (i = 0; i < 7; ++i)
913 DUMPREG(HDMI_VSI_DATA(i));
914
915#undef DUMPREG
916}
917
918static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
919{
Rahul Sharma5a325072012-10-04 20:48:54 +0530[diff] [blame]920 if (hdata->type == HDMI_TYPE13)
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]921 hdmi_v13_regs_dump(hdata, prefix);
922 else
923 hdmi_v14_regs_dump(hdata, prefix);
924}
925
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]926static u8 hdmi_chksum(struct hdmi_context *hdata,
927 u32 start, u8 len, u32 hdr_sum)
928{
929 int i;
930
931 /* hdr_sum : header0 + header1 + header2
932 * start : start address of packet byte1
933 * len : packet bytes - 1 */
934 for (i = 0; i < len; ++i)
935 hdr_sum += 0xff & hdmi_reg_read(hdata, start + i * 4);
936
937 /* return 2's complement of 8 bit hdr_sum */
938 return (u8)(~(hdr_sum & 0xff) + 1);
939}
940
941static void hdmi_reg_infoframe(struct hdmi_context *hdata,
Sachin Kamatd34d59b2014-02-04 08:40:18 +0530[diff] [blame]942 union hdmi_infoframe *infoframe)
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]943{
944 u32 hdr_sum;
945 u8 chksum;
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]946 u32 mod;
947 u32 vic;
948
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]949 mod = hdmi_reg_read(hdata, HDMI_MODE_SEL);
950 if (hdata->dvi_mode) {
951 hdmi_reg_writeb(hdata, HDMI_VSI_CON,
952 HDMI_VSI_CON_DO_NOT_TRANSMIT);
953 hdmi_reg_writeb(hdata, HDMI_AVI_CON,
954 HDMI_AVI_CON_DO_NOT_TRANSMIT);
955 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
956 return;
957 }
958
Sachin Kamatd34d59b2014-02-04 08:40:18 +0530[diff] [blame]959 switch (infoframe->any.type) {
960 case HDMI_INFOFRAME_TYPE_AVI:
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]961 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
Sachin Kamatd34d59b2014-02-04 08:40:18 +0530[diff] [blame]962 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER0, infoframe->any.type);
963 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER1,
964 infoframe->any.version);
965 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER2, infoframe->any.length);
966 hdr_sum = infoframe->any.type + infoframe->any.version +
967 infoframe->any.length;
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]968
969 /* Output format zero hardcoded ,RGB YBCR selection */
970 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(1), 0 << 5 |
971 AVI_ACTIVE_FORMAT_VALID |
972 AVI_UNDERSCANNED_DISPLAY_VALID);
973
Shirish S46154152014-03-13 10:58:28 +0530[diff] [blame]974 /*
975 * Set the aspect ratio as per the mode, mentioned in
976 * Table 9 AVI InfoFrame Data Byte 2 of CEA-861-D Standard
977 */
978 switch (hdata->mode_conf.aspect_ratio) {
979 case HDMI_PICTURE_ASPECT_4_3:
980 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
981 hdata->mode_conf.aspect_ratio |
982 AVI_4_3_CENTER_RATIO);
983 break;
984 case HDMI_PICTURE_ASPECT_16_9:
985 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
986 hdata->mode_conf.aspect_ratio |
987 AVI_16_9_CENTER_RATIO);
988 break;
989 case HDMI_PICTURE_ASPECT_NONE:
990 default:
991 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
992 hdata->mode_conf.aspect_ratio |
993 AVI_SAME_AS_PIC_ASPECT_RATIO);
994 break;
995 }
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]996
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]997 vic = hdata->mode_conf.cea_video_id;
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]998 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), vic);
999
1000 chksum = hdmi_chksum(hdata, HDMI_AVI_BYTE(1),
Sachin Kamatd34d59b2014-02-04 08:40:18 +0530[diff] [blame]1001 infoframe->any.length, hdr_sum);
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]1002 DRM_DEBUG_KMS("AVI checksum = 0x%x\n", chksum);
1003 hdmi_reg_writeb(hdata, HDMI_AVI_CHECK_SUM, chksum);
1004 break;
Sachin Kamatd34d59b2014-02-04 08:40:18 +0530[diff] [blame]1005 case HDMI_INFOFRAME_TYPE_AUDIO:
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]1006 hdmi_reg_writeb(hdata, HDMI_AUI_CON, 0x02);
Sachin Kamatd34d59b2014-02-04 08:40:18 +0530[diff] [blame]1007 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER0, infoframe->any.type);
1008 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER1,
1009 infoframe->any.version);
1010 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER2, infoframe->any.length);
1011 hdr_sum = infoframe->any.type + infoframe->any.version +
1012 infoframe->any.length;
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]1013 chksum = hdmi_chksum(hdata, HDMI_AUI_BYTE(1),
Sachin Kamatd34d59b2014-02-04 08:40:18 +0530[diff] [blame]1014 infoframe->any.length, hdr_sum);
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]1015 DRM_DEBUG_KMS("AUI checksum = 0x%x\n", chksum);
1016 hdmi_reg_writeb(hdata, HDMI_AUI_CHECK_SUM, chksum);
1017 break;
1018 default:
1019 break;
1020 }
1021}
1022
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1023static enum drm_connector_status hdmi_detect(struct drm_connector *connector,
1024 bool force)
Sean Paul45517892014-01-30 16:19:05 -0500[diff] [blame]1025{
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1026 struct hdmi_context *hdata = ctx_from_connector(connector);
Sean Paul45517892014-01-30 16:19:05 -0500[diff] [blame]1027
Sean Paul5137c8c2014-04-03 20:41:03 +0530[diff] [blame]1028 hdata->hpd = gpio_get_value(hdata->hpd_gpio);
1029
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1030 return hdata->hpd ? connector_status_connected :
1031 connector_status_disconnected;
Sean Paul45517892014-01-30 16:19:05 -0500[diff] [blame]1032}
1033
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1034static void hdmi_connector_destroy(struct drm_connector *connector)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1035{
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1036}
1037
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1038static struct drm_connector_funcs hdmi_connector_funcs = {
1039 .dpms = drm_helper_connector_dpms,
1040 .fill_modes = drm_helper_probe_single_connector_modes,
1041 .detect = hdmi_detect,
1042 .destroy = hdmi_connector_destroy,
1043};
1044
1045static int hdmi_get_modes(struct drm_connector *connector)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1046{
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1047 struct hdmi_context *hdata = ctx_from_connector(connector);
1048 struct edid *edid;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1049
Inki Dae8fa04aa2014-03-13 16:38:31 +0900[diff] [blame]1050 if (!hdata->ddc_adpt)
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1051 return -ENODEV;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1052
Inki Dae8fa04aa2014-03-13 16:38:31 +0900[diff] [blame]1053 edid = drm_get_edid(connector, hdata->ddc_adpt);
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1054 if (!edid)
1055 return -ENODEV;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1056
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1057 hdata->dvi_mode = !drm_detect_hdmi_monitor(edid);
Rahul Sharma9c08e4b2013-01-04 07:59:11 -0500[diff] [blame]1058 DRM_DEBUG_KMS("%s : width[%d] x height[%d]\n",
1059 (hdata->dvi_mode ? "dvi monitor" : "hdmi monitor"),
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1060 edid->width_cm, edid->height_cm);
Rahul Sharma9c08e4b2013-01-04 07:59:11 -0500[diff] [blame]1061
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1062 drm_mode_connector_update_edid_property(connector, edid);
1063
1064 return drm_add_edid_modes(connector, edid);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1065}
1066
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1067static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1068{
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]1069 int i;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1070
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]1071 for (i = 0; i < hdata->phy_conf_count; i++)
1072 if (hdata->phy_confs[i].pixel_clock == pixel_clock)
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1073 return i;
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1074
1075 DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
1076 return -EINVAL;
1077}
1078
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1079static int hdmi_mode_valid(struct drm_connector *connector,
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]1080 struct drm_display_mode *mode)
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1081{
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1082 struct hdmi_context *hdata = ctx_from_connector(connector);
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1083 int ret;
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1084
Rahul Sharma16844fb2013-06-10 14:50:00 +0530[diff] [blame]1085 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
1086 mode->hdisplay, mode->vdisplay, mode->vrefresh,
1087 (mode->flags & DRM_MODE_FLAG_INTERLACE) ? true :
1088 false, mode->clock * 1000);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1089
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]1090 ret = mixer_check_mode(mode);
1091 if (ret)
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1092 return MODE_BAD;
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]1093
Rahul Sharma16844fb2013-06-10 14:50:00 +0530[diff] [blame]1094 ret = hdmi_find_phy_conf(hdata, mode->clock * 1000);
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1095 if (ret < 0)
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1096 return MODE_BAD;
1097
1098 return MODE_OK;
1099}
1100
1101static struct drm_encoder *hdmi_best_encoder(struct drm_connector *connector)
1102{
1103 struct hdmi_context *hdata = ctx_from_connector(connector);
1104
1105 return hdata->encoder;
1106}
1107
1108static struct drm_connector_helper_funcs hdmi_connector_helper_funcs = {
1109 .get_modes = hdmi_get_modes,
1110 .mode_valid = hdmi_mode_valid,
1111 .best_encoder = hdmi_best_encoder,
1112};
1113
1114static int hdmi_create_connector(struct exynos_drm_display *display,
1115 struct drm_encoder *encoder)
1116{
1117 struct hdmi_context *hdata = display->ctx;
1118 struct drm_connector *connector = &hdata->connector;
1119 int ret;
1120
1121 hdata->encoder = encoder;
1122 connector->interlace_allowed = true;
1123 connector->polled = DRM_CONNECTOR_POLL_HPD;
1124
1125 ret = drm_connector_init(hdata->drm_dev, connector,
1126 &hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
1127 if (ret) {
1128 DRM_ERROR("Failed to initialize connector with drm\n");
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1129 return ret;
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1130 }
1131
1132 drm_connector_helper_add(connector, &hdmi_connector_helper_funcs);
1133 drm_sysfs_connector_add(connector);
1134 drm_mode_connector_attach_encoder(connector, encoder);
1135
1136 return 0;
1137}
1138
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]1139static void hdmi_mode_fixup(struct exynos_drm_display *display,
1140 struct drm_connector *connector,
1141 const struct drm_display_mode *mode,
1142 struct drm_display_mode *adjusted_mode)
1143{
1144 struct drm_display_mode *m;
1145 int mode_ok;
1146
1147 DRM_DEBUG_KMS("%s\n", __FILE__);
1148
1149 drm_mode_set_crtcinfo(adjusted_mode, 0);
1150
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1151 mode_ok = hdmi_mode_valid(connector, adjusted_mode);
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]1152
1153 /* just return if user desired mode exists. */
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1154 if (mode_ok == MODE_OK)
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]1155 return;
1156
1157 /*
1158 * otherwise, find the most suitable mode among modes and change it
1159 * to adjusted_mode.
1160 */
1161 list_for_each_entry(m, &connector->modes, head) {
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1162 mode_ok = hdmi_mode_valid(connector, m);
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]1163
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]1164 if (mode_ok == MODE_OK) {
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]1165 DRM_INFO("desired mode doesn't exist so\n");
1166 DRM_INFO("use the most suitable mode among modes.\n");
1167
1168 DRM_DEBUG_KMS("Adjusted Mode: [%d]x[%d] [%d]Hz\n",
1169 m->hdisplay, m->vdisplay, m->vrefresh);
1170
Sean Paul75626852014-01-30 16:19:16 -0500[diff] [blame]1171 drm_mode_copy(adjusted_mode, m);
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]1172 break;
1173 }
1174 }
1175}
1176
Seung-Woo Kim3e148ba2012-03-16 18:47:16 +0900[diff] [blame]1177static void hdmi_set_acr(u32 freq, u8 *acr)
1178{
1179 u32 n, cts;
1180
1181 switch (freq) {
1182 case 32000:
1183 n = 4096;
1184 cts = 27000;
1185 break;
1186 case 44100:
1187 n = 6272;
1188 cts = 30000;
1189 break;
1190 case 88200:
1191 n = 12544;
1192 cts = 30000;
1193 break;
1194 case 176400:
1195 n = 25088;
1196 cts = 30000;
1197 break;
1198 case 48000:
1199 n = 6144;
1200 cts = 27000;
1201 break;
1202 case 96000:
1203 n = 12288;
1204 cts = 27000;
1205 break;
1206 case 192000:
1207 n = 24576;
1208 cts = 27000;
1209 break;
1210 default:
1211 n = 0;
1212 cts = 0;
1213 break;
1214 }
1215
1216 acr[1] = cts >> 16;
1217 acr[2] = cts >> 8 & 0xff;
1218 acr[3] = cts & 0xff;
1219
1220 acr[4] = n >> 16;
1221 acr[5] = n >> 8 & 0xff;
1222 acr[6] = n & 0xff;
1223}
1224
1225static void hdmi_reg_acr(struct hdmi_context *hdata, u8 *acr)
1226{
1227 hdmi_reg_writeb(hdata, HDMI_ACR_N0, acr[6]);
1228 hdmi_reg_writeb(hdata, HDMI_ACR_N1, acr[5]);
1229 hdmi_reg_writeb(hdata, HDMI_ACR_N2, acr[4]);
1230 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS0, acr[3]);
1231 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS1, acr[2]);
1232 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS2, acr[1]);
1233 hdmi_reg_writeb(hdata, HDMI_ACR_CTS0, acr[3]);
1234 hdmi_reg_writeb(hdata, HDMI_ACR_CTS1, acr[2]);
1235 hdmi_reg_writeb(hdata, HDMI_ACR_CTS2, acr[1]);
1236
Rahul Sharma5a325072012-10-04 20:48:54 +0530[diff] [blame]1237 if (hdata->type == HDMI_TYPE13)
Seung-Woo Kim3e148ba2012-03-16 18:47:16 +0900[diff] [blame]1238 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 4);
1239 else
1240 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
1241}
1242
1243static void hdmi_audio_init(struct hdmi_context *hdata)
1244{
1245 u32 sample_rate, bits_per_sample, frame_size_code;
1246 u32 data_num, bit_ch, sample_frq;
1247 u32 val;
1248 u8 acr[7];
1249
1250 sample_rate = 44100;
1251 bits_per_sample = 16;
1252 frame_size_code = 0;
1253
1254 switch (bits_per_sample) {
1255 case 20:
1256 data_num = 2;
1257 bit_ch = 1;
1258 break;
1259 case 24:
1260 data_num = 3;
1261 bit_ch = 1;
1262 break;
1263 default:
1264 data_num = 1;
1265 bit_ch = 0;
1266 break;
1267 }
1268
1269 hdmi_set_acr(sample_rate, acr);
1270 hdmi_reg_acr(hdata, acr);
1271
1272 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
1273 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
1274 | HDMI_I2S_MUX_ENABLE);
1275
1276 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
1277 | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
1278
1279 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
1280
1281 sample_frq = (sample_rate == 44100) ? 0 :
1282 (sample_rate == 48000) ? 2 :
1283 (sample_rate == 32000) ? 3 :
1284 (sample_rate == 96000) ? 0xa : 0x0;
1285
1286 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
1287 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
1288
1289 val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
1290 hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
1291
1292 /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
1293 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
1294 | HDMI_I2S_SEL_LRCK(6));
1295 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1)
1296 | HDMI_I2S_SEL_SDATA2(4));
1297 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
1298 | HDMI_I2S_SEL_SDATA2(2));
1299 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
1300
1301 /* I2S_CON_1 & 2 */
1302 hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
1303 | HDMI_I2S_L_CH_LOW_POL);
1304 hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
1305 | HDMI_I2S_SET_BIT_CH(bit_ch)
1306 | HDMI_I2S_SET_SDATA_BIT(data_num)
1307 | HDMI_I2S_BASIC_FORMAT);
1308
1309 /* Configure register related to CUV information */
1310 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0
1311 | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH
1312 | HDMI_I2S_COPYRIGHT
1313 | HDMI_I2S_LINEAR_PCM
1314 | HDMI_I2S_CONSUMER_FORMAT);
1315 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
1316 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
1317 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2
1318 | HDMI_I2S_SET_SMP_FREQ(sample_frq));
1319 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4,
1320 HDMI_I2S_ORG_SMP_FREQ_44_1
1321 | HDMI_I2S_WORD_LEN_MAX24_24BITS
1322 | HDMI_I2S_WORD_LEN_MAX_24BITS);
1323
1324 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
1325}
1326
1327static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff)
1328{
Seung-Woo Kim872d20d62012-04-24 17:39:15 +0900[diff] [blame]1329 if (hdata->dvi_mode)
Seung-Woo Kim3e148ba2012-03-16 18:47:16 +0900[diff] [blame]1330 return;
1331
1332 hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0);
1333 hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ?
1334 HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
1335}
1336
Rahul Sharmabfa48422014-04-03 20:41:04 +0530[diff] [blame]1337static void hdmi_start(struct hdmi_context *hdata, bool start)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1338{
Rahul Sharmabfa48422014-04-03 20:41:04 +0530[diff] [blame]1339 u32 val = start ? HDMI_TG_EN : 0;
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1340
Rahul Sharmabfa48422014-04-03 20:41:04 +0530[diff] [blame]1341 if (hdata->current_mode.flags & DRM_MODE_FLAG_INTERLACE)
1342 val |= HDMI_FIELD_EN;
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1343
Rahul Sharmabfa48422014-04-03 20:41:04 +0530[diff] [blame]1344 hdmi_reg_writemask(hdata, HDMI_CON_0, val, HDMI_EN);
1345 hdmi_reg_writemask(hdata, HDMI_TG_CMD, val, HDMI_TG_EN | HDMI_FIELD_EN);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1346}
1347
1348static void hdmi_conf_init(struct hdmi_context *hdata)
1349{
Sachin Kamatd34d59b2014-02-04 08:40:18 +0530[diff] [blame]1350 union hdmi_infoframe infoframe;
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]1351
Sean Paul77006a72013-01-16 10:17:20 -0500[diff] [blame]1352 /* disable HPD interrupts from HDMI IP block, use GPIO instead */
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1353 hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL |
1354 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1355
1356 /* choose HDMI mode */
1357 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1358 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
Shirish S9a8e1cb2014-02-14 13:04:57 +0530[diff] [blame]1359 /* Apply Video preable and Guard band in HDMI mode only */
1360 hdmi_reg_writeb(hdata, HDMI_CON_2, 0);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1361 /* disable bluescreen */
1362 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1363
Seung-Woo Kim872d20d62012-04-24 17:39:15 +0900[diff] [blame]1364 if (hdata->dvi_mode) {
1365 /* choose DVI mode */
1366 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1367 HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
1368 hdmi_reg_writeb(hdata, HDMI_CON_2,
1369 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS);
1370 }
1371
Rahul Sharma5a325072012-10-04 20:48:54 +0530[diff] [blame]1372 if (hdata->type == HDMI_TYPE13) {
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1373 /* choose bluescreen (fecal) color */
1374 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
1375 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
1376 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56);
1377
1378 /* enable AVI packet every vsync, fixes purple line problem */
1379 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02);
1380 /* force RGB, look to CEA-861-D, table 7 for more detail */
1381 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5);
1382 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
1383
1384 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02);
1385 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
1386 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
1387 } else {
Sachin Kamatd34d59b2014-02-04 08:40:18 +0530[diff] [blame]1388 infoframe.any.type = HDMI_INFOFRAME_TYPE_AVI;
1389 infoframe.any.version = HDMI_AVI_VERSION;
1390 infoframe.any.length = HDMI_AVI_LENGTH;
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]1391 hdmi_reg_infoframe(hdata, &infoframe);
1392
Sachin Kamatd34d59b2014-02-04 08:40:18 +0530[diff] [blame]1393 infoframe.any.type = HDMI_INFOFRAME_TYPE_AUDIO;
1394 infoframe.any.version = HDMI_AUI_VERSION;
1395 infoframe.any.length = HDMI_AUI_LENGTH;
Rahul Sharmaa144c2e2012-11-26 10:52:57 +0530[diff] [blame]1396 hdmi_reg_infoframe(hdata, &infoframe);
1397
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1398 /* enable AVI packet every vsync, fixes purple line problem */
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1399 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
1400 }
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1401}
1402
Rahul Sharma16844fb2013-06-10 14:50:00 +0530[diff] [blame]1403static void hdmi_v13_mode_apply(struct hdmi_context *hdata)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1404{
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1405 const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg;
1406 const struct hdmi_v13_core_regs *core =
1407 &hdata->mode_conf.conf.v13_conf.core;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1408 int tries;
1409
1410 /* setting core registers */
1411 hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1412 hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1413 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_0, core->v_blank[0]);
1414 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_1, core->v_blank[1]);
1415 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_2, core->v_blank[2]);
1416 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_0, core->h_v_line[0]);
1417 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_1, core->h_v_line[1]);
1418 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_2, core->h_v_line[2]);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1419 hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1420 hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1421 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_0, core->v_blank_f[0]);
1422 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_1, core->v_blank_f[1]);
1423 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_2, core->v_blank_f[2]);
1424 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_0, core->h_sync_gen[0]);
1425 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_1, core->h_sync_gen[1]);
1426 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_2, core->h_sync_gen[2]);
1427 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_0, core->v_sync_gen1[0]);
1428 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_1, core->v_sync_gen1[1]);
1429 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_2, core->v_sync_gen1[2]);
1430 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_0, core->v_sync_gen2[0]);
1431 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_1, core->v_sync_gen2[1]);
1432 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_2, core->v_sync_gen2[2]);
1433 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_0, core->v_sync_gen3[0]);
1434 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_1, core->v_sync_gen3[1]);
1435 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_2, core->v_sync_gen3[2]);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1436 /* Timing generator registers */
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1437 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1438 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1439 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1440 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1441 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1442 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1443 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1444 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1445 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1446 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1447 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1448 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1449 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1450 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1451 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1452 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1453 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1454 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1455 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1456 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1457 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1458 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1459 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1460 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1461 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1462 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1463 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1464 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1465
1466 /* waiting for HDMIPHY's PLL to get to steady state */
1467 for (tries = 100; tries; --tries) {
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1468 u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1469 if (val & HDMI_PHY_STATUS_READY)
1470 break;
Sean Paul09760ea2013-01-14 17:03:20 -0500[diff] [blame]1471 usleep_range(1000, 2000);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1472 }
1473 /* steady state not achieved */
1474 if (tries == 0) {
1475 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1476 hdmi_regs_dump(hdata, "timing apply");
1477 }
1478
Sean Paul0bfb1f82013-06-11 12:24:02 +0530[diff] [blame]1479 clk_disable_unprepare(hdata->res.sclk_hdmi);
Rahul Sharma59956d32013-06-11 12:24:03 +0530[diff] [blame]1480 clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy);
Sean Paul0bfb1f82013-06-11 12:24:02 +0530[diff] [blame]1481 clk_prepare_enable(hdata->res.sclk_hdmi);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1482
1483 /* enable HDMI and timing generator */
Rahul Sharmabfa48422014-04-03 20:41:04 +0530[diff] [blame]1484 hdmi_start(hdata, true);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1485}
1486
Rahul Sharma16844fb2013-06-10 14:50:00 +0530[diff] [blame]1487static void hdmi_v14_mode_apply(struct hdmi_context *hdata)
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1488{
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1489 const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg;
1490 const struct hdmi_v14_core_regs *core =
1491 &hdata->mode_conf.conf.v14_conf.core;
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1492 int tries;
1493
1494 /* setting core registers */
1495 hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1496 hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1497 hdmi_reg_writeb(hdata, HDMI_V2_BLANK_0, core->v2_blank[0]);
1498 hdmi_reg_writeb(hdata, HDMI_V2_BLANK_1, core->v2_blank[1]);
1499 hdmi_reg_writeb(hdata, HDMI_V1_BLANK_0, core->v1_blank[0]);
1500 hdmi_reg_writeb(hdata, HDMI_V1_BLANK_1, core->v1_blank[1]);
1501 hdmi_reg_writeb(hdata, HDMI_V_LINE_0, core->v_line[0]);
1502 hdmi_reg_writeb(hdata, HDMI_V_LINE_1, core->v_line[1]);
1503 hdmi_reg_writeb(hdata, HDMI_H_LINE_0, core->h_line[0]);
1504 hdmi_reg_writeb(hdata, HDMI_H_LINE_1, core->h_line[1]);
1505 hdmi_reg_writeb(hdata, HDMI_HSYNC_POL, core->hsync_pol[0]);
1506 hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1507 hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1508 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_0, core->v_blank_f0[0]);
1509 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_1, core->v_blank_f0[1]);
1510 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_0, core->v_blank_f1[0]);
1511 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_1, core->v_blank_f1[1]);
1512 hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_0, core->h_sync_start[0]);
1513 hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_1, core->h_sync_start[1]);
1514 hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_0, core->h_sync_end[0]);
1515 hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_1, core->h_sync_end[1]);
1516 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_0,
1517 core->v_sync_line_bef_2[0]);
1518 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_1,
1519 core->v_sync_line_bef_2[1]);
1520 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_0,
1521 core->v_sync_line_bef_1[0]);
1522 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_1,
1523 core->v_sync_line_bef_1[1]);
1524 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_0,
1525 core->v_sync_line_aft_2[0]);
1526 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_1,
1527 core->v_sync_line_aft_2[1]);
1528 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_0,
1529 core->v_sync_line_aft_1[0]);
1530 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_1,
1531 core->v_sync_line_aft_1[1]);
1532 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0,
1533 core->v_sync_line_aft_pxl_2[0]);
1534 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_1,
1535 core->v_sync_line_aft_pxl_2[1]);
1536 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0,
1537 core->v_sync_line_aft_pxl_1[0]);
1538 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_1,
1539 core->v_sync_line_aft_pxl_1[1]);
1540 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_0, core->v_blank_f2[0]);
1541 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_1, core->v_blank_f2[1]);
1542 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_0, core->v_blank_f3[0]);
1543 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_1, core->v_blank_f3[1]);
1544 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_0, core->v_blank_f4[0]);
1545 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_1, core->v_blank_f4[1]);
1546 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_0, core->v_blank_f5[0]);
1547 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_1, core->v_blank_f5[1]);
1548 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_0,
1549 core->v_sync_line_aft_3[0]);
1550 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_1,
1551 core->v_sync_line_aft_3[1]);
1552 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_0,
1553 core->v_sync_line_aft_4[0]);
1554 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_1,
1555 core->v_sync_line_aft_4[1]);
1556 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_0,
1557 core->v_sync_line_aft_5[0]);
1558 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_1,
1559 core->v_sync_line_aft_5[1]);
1560 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_0,
1561 core->v_sync_line_aft_6[0]);
1562 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_1,
1563 core->v_sync_line_aft_6[1]);
1564 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0,
1565 core->v_sync_line_aft_pxl_3[0]);
1566 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_1,
1567 core->v_sync_line_aft_pxl_3[1]);
1568 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0,
1569 core->v_sync_line_aft_pxl_4[0]);
1570 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_1,
1571 core->v_sync_line_aft_pxl_4[1]);
1572 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0,
1573 core->v_sync_line_aft_pxl_5[0]);
1574 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_1,
1575 core->v_sync_line_aft_pxl_5[1]);
1576 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0,
1577 core->v_sync_line_aft_pxl_6[0]);
1578 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_1,
1579 core->v_sync_line_aft_pxl_6[1]);
1580 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_0, core->vact_space_1[0]);
1581 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_1, core->vact_space_1[1]);
1582 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_0, core->vact_space_2[0]);
1583 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_1, core->vact_space_2[1]);
1584 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_0, core->vact_space_3[0]);
1585 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_1, core->vact_space_3[1]);
1586 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_0, core->vact_space_4[0]);
1587 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_1, core->vact_space_4[1]);
1588 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_0, core->vact_space_5[0]);
1589 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_1, core->vact_space_5[1]);
1590 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_0, core->vact_space_6[0]);
1591 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_1, core->vact_space_6[1]);
1592
1593 /* Timing generator registers */
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1594 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1595 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1596 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1597 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1598 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1599 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1600 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1601 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1602 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1603 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1604 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1605 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1606 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1607 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1608 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1609 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1610 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1611 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1612 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1613 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1614 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_L, tg->vact_st3[0]);
1615 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_H, tg->vact_st3[1]);
1616 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_L, tg->vact_st4[0]);
1617 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_H, tg->vact_st4[1]);
1618 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1619 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1620 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1621 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1622 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1623 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1624 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1625 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
1626 hdmi_reg_writeb(hdata, HDMI_TG_3D, tg->tg_3d[0]);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1627
1628 /* waiting for HDMIPHY's PLL to get to steady state */
1629 for (tries = 100; tries; --tries) {
1630 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0);
1631 if (val & HDMI_PHY_STATUS_READY)
1632 break;
Sean Paul09760ea2013-01-14 17:03:20 -0500[diff] [blame]1633 usleep_range(1000, 2000);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1634 }
1635 /* steady state not achieved */
1636 if (tries == 0) {
1637 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1638 hdmi_regs_dump(hdata, "timing apply");
1639 }
1640
Sean Paul0bfb1f82013-06-11 12:24:02 +0530[diff] [blame]1641 clk_disable_unprepare(hdata->res.sclk_hdmi);
Rahul Sharma59956d32013-06-11 12:24:03 +0530[diff] [blame]1642 clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy);
Sean Paul0bfb1f82013-06-11 12:24:02 +0530[diff] [blame]1643 clk_prepare_enable(hdata->res.sclk_hdmi);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1644
1645 /* enable HDMI and timing generator */
Rahul Sharmabfa48422014-04-03 20:41:04 +0530[diff] [blame]1646 hdmi_start(hdata, true);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1647}
1648
Rahul Sharma16844fb2013-06-10 14:50:00 +0530[diff] [blame]1649static void hdmi_mode_apply(struct hdmi_context *hdata)
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1650{
Rahul Sharma5a325072012-10-04 20:48:54 +0530[diff] [blame]1651 if (hdata->type == HDMI_TYPE13)
Rahul Sharma16844fb2013-06-10 14:50:00 +0530[diff] [blame]1652 hdmi_v13_mode_apply(hdata);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1653 else
Rahul Sharma16844fb2013-06-10 14:50:00 +0530[diff] [blame]1654 hdmi_v14_mode_apply(hdata);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1655}
1656
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1657static void hdmiphy_conf_reset(struct hdmi_context *hdata)
1658{
1659 u8 buffer[2];
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1660 u32 reg;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1661
Sean Paul0bfb1f82013-06-11 12:24:02 +0530[diff] [blame]1662 clk_disable_unprepare(hdata->res.sclk_hdmi);
Rahul Sharma59956d32013-06-11 12:24:03 +0530[diff] [blame]1663 clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_pixel);
Sean Paul0bfb1f82013-06-11 12:24:02 +0530[diff] [blame]1664 clk_prepare_enable(hdata->res.sclk_hdmi);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1665
1666 /* operation mode */
1667 buffer[0] = 0x1f;
1668 buffer[1] = 0x00;
1669
1670 if (hdata->hdmiphy_port)
1671 i2c_master_send(hdata->hdmiphy_port, buffer, 2);
1672
Rahul Sharma5a325072012-10-04 20:48:54 +0530[diff] [blame]1673 if (hdata->type == HDMI_TYPE13)
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1674 reg = HDMI_V13_PHY_RSTOUT;
1675 else
1676 reg = HDMI_PHY_RSTOUT;
1677
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1678 /* reset hdmiphy */
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1679 hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT);
Sean Paul09760ea2013-01-14 17:03:20 -0500[diff] [blame]1680 usleep_range(10000, 12000);
Joonyoung Shim3ecd70b2012-03-16 18:47:03 +0900[diff] [blame]1681 hdmi_reg_writemask(hdata, reg, 0, HDMI_PHY_SW_RSTOUT);
Sean Paul09760ea2013-01-14 17:03:20 -0500[diff] [blame]1682 usleep_range(10000, 12000);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1683}
1684
Rahul Sharmaa5562252012-11-28 11:30:25 +0530[diff] [blame]1685static void hdmiphy_poweron(struct hdmi_context *hdata)
1686{
Rahul Sharmaa5562252012-11-28 11:30:25 +0530[diff] [blame]1687 if (hdata->type == HDMI_TYPE14)
1688 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, 0,
1689 HDMI_PHY_POWER_OFF_EN);
1690}
1691
1692static void hdmiphy_poweroff(struct hdmi_context *hdata)
1693{
Rahul Sharmaa5562252012-11-28 11:30:25 +0530[diff] [blame]1694 if (hdata->type == HDMI_TYPE14)
1695 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0,
1696 HDMI_PHY_POWER_OFF_EN);
1697}
1698
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1699static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1700{
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1701 int ret;
1702 int i;
1703
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1704 /* pixel clock */
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1705 i = hdmi_find_phy_conf(hdata, hdata->mode_conf.pixel_clock);
1706 if (i < 0) {
1707 DRM_ERROR("failed to find hdmiphy conf\n");
1708 return;
1709 }
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1710
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]1711 ret = hdmiphy_reg_write_buf(hdata, 0, hdata->phy_confs[i].conf, 32);
1712 if (ret) {
1713 DRM_ERROR("failed to configure hdmiphy\n");
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1714 return;
1715 }
1716
Sean Paul09760ea2013-01-14 17:03:20 -0500[diff] [blame]1717 usleep_range(10000, 12000);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1718
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]1719 ret = hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1720 HDMI_PHY_DISABLE_MODE_SET);
1721 if (ret) {
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1722 DRM_ERROR("failed to enable hdmiphy\n");
1723 return;
1724 }
1725
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1726}
1727
1728static void hdmi_conf_apply(struct hdmi_context *hdata)
1729{
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1730 hdmiphy_conf_reset(hdata);
1731 hdmiphy_conf_apply(hdata);
1732
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]1733 mutex_lock(&hdata->hdmi_mutex);
Rahul Sharmabfa48422014-04-03 20:41:04 +0530[diff] [blame]1734 hdmi_start(hdata, false);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1735 hdmi_conf_init(hdata);
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]1736 mutex_unlock(&hdata->hdmi_mutex);
1737
Seung-Woo Kim3e148ba2012-03-16 18:47:16 +0900[diff] [blame]1738 hdmi_audio_init(hdata);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1739
1740 /* setting core registers */
Rahul Sharma16844fb2013-06-10 14:50:00 +0530[diff] [blame]1741 hdmi_mode_apply(hdata);
Seung-Woo Kim3e148ba2012-03-16 18:47:16 +0900[diff] [blame]1742 hdmi_audio_control(hdata, true);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1743
1744 hdmi_regs_dump(hdata, "start");
1745}
1746
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1747static void hdmi_set_reg(u8 *reg_pair, int num_bytes, u32 value)
1748{
1749 int i;
1750 BUG_ON(num_bytes > 4);
1751 for (i = 0; i < num_bytes; i++)
1752 reg_pair[i] = (value >> (8 * i)) & 0xff;
1753}
1754
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1755static void hdmi_v13_mode_set(struct hdmi_context *hdata,
1756 struct drm_display_mode *m)
1757{
1758 struct hdmi_v13_core_regs *core = &hdata->mode_conf.conf.v13_conf.core;
1759 struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg;
1760 unsigned int val;
1761
1762 hdata->mode_conf.cea_video_id =
1763 drm_match_cea_mode((struct drm_display_mode *)m);
1764 hdata->mode_conf.pixel_clock = m->clock * 1000;
Shirish S46154152014-03-13 10:58:28 +0530[diff] [blame]1765 hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio;
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1766
1767 hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1768 hdmi_set_reg(core->h_v_line, 3, (m->htotal << 12) | m->vtotal);
1769
1770 val = (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
1771 hdmi_set_reg(core->vsync_pol, 1, val);
1772
1773 val = (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0;
1774 hdmi_set_reg(core->int_pro_mode, 1, val);
1775
1776 val = (m->hsync_start - m->hdisplay - 2);
1777 val |= ((m->hsync_end - m->hdisplay - 2) << 10);
1778 val |= ((m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0)<<20;
1779 hdmi_set_reg(core->h_sync_gen, 3, val);
1780
1781 /*
1782 * Quirk requirement for exynos HDMI IP design,
1783 * 2 pixels less than the actual calculation for hsync_start
1784 * and end.
1785 */
1786
1787 /* Following values & calculations differ for different type of modes */
1788 if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1789 /* Interlaced Mode */
1790 val = ((m->vsync_end - m->vdisplay) / 2);
1791 val |= ((m->vsync_start - m->vdisplay) / 2) << 12;
1792 hdmi_set_reg(core->v_sync_gen1, 3, val);
1793
1794 val = m->vtotal / 2;
1795 val |= ((m->vtotal - m->vdisplay) / 2) << 11;
1796 hdmi_set_reg(core->v_blank, 3, val);
1797
1798 val = (m->vtotal +
1799 ((m->vsync_end - m->vsync_start) * 4) + 5) / 2;
1800 val |= m->vtotal << 11;
1801 hdmi_set_reg(core->v_blank_f, 3, val);
1802
1803 val = ((m->vtotal / 2) + 7);
1804 val |= ((m->vtotal / 2) + 2) << 12;
1805 hdmi_set_reg(core->v_sync_gen2, 3, val);
1806
1807 val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay));
1808 val |= ((m->htotal / 2) +
1809 (m->hsync_start - m->hdisplay)) << 12;
1810 hdmi_set_reg(core->v_sync_gen3, 3, val);
1811
1812 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
1813 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
1814
1815 hdmi_set_reg(tg->vact_st2, 2, 0x249);/* Reset value + 1*/
1816 } else {
1817 /* Progressive Mode */
1818
1819 val = m->vtotal;
1820 val |= (m->vtotal - m->vdisplay) << 11;
1821 hdmi_set_reg(core->v_blank, 3, val);
1822
1823 hdmi_set_reg(core->v_blank_f, 3, 0);
1824
1825 val = (m->vsync_end - m->vdisplay);
1826 val |= ((m->vsync_start - m->vdisplay) << 12);
1827 hdmi_set_reg(core->v_sync_gen1, 3, val);
1828
1829 hdmi_set_reg(core->v_sync_gen2, 3, 0x1001);/* Reset value */
1830 hdmi_set_reg(core->v_sync_gen3, 3, 0x1001);/* Reset value */
1831 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1832 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1833 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1834 }
1835
1836 /* Timing generator registers */
1837 hdmi_set_reg(tg->cmd, 1, 0x0);
1838 hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1839 hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1840 hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1841 hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1842 hdmi_set_reg(tg->vsync, 2, 0x1);
1843 hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1844 hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1845 hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
1846 hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1847 hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
1848 hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
1849 hdmi_set_reg(tg->tg_3d, 1, 0x0); /* Not used */
1850}
1851
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1852static void hdmi_v14_mode_set(struct hdmi_context *hdata,
1853 struct drm_display_mode *m)
1854{
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1855 struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg;
1856 struct hdmi_v14_core_regs *core =
1857 &hdata->mode_conf.conf.v14_conf.core;
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1858
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1859 hdata->mode_conf.cea_video_id =
1860 drm_match_cea_mode((struct drm_display_mode *)m);
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1861 hdata->mode_conf.pixel_clock = m->clock * 1000;
Shirish S46154152014-03-13 10:58:28 +0530[diff] [blame]1862 hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio;
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1863
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1864 hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1865 hdmi_set_reg(core->v_line, 2, m->vtotal);
1866 hdmi_set_reg(core->h_line, 2, m->htotal);
1867 hdmi_set_reg(core->hsync_pol, 1,
1868 (m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0);
1869 hdmi_set_reg(core->vsync_pol, 1,
1870 (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0);
1871 hdmi_set_reg(core->int_pro_mode, 1,
1872 (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
1873
1874 /*
1875 * Quirk requirement for exynos 5 HDMI IP design,
1876 * 2 pixels less than the actual calculation for hsync_start
1877 * and end.
1878 */
1879
1880 /* Following values & calculations differ for different type of modes */
1881 if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1882 /* Interlaced Mode */
1883 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1884 (m->vsync_end - m->vdisplay) / 2);
1885 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1886 (m->vsync_start - m->vdisplay) / 2);
1887 hdmi_set_reg(core->v2_blank, 2, m->vtotal / 2);
1888 hdmi_set_reg(core->v1_blank, 2, (m->vtotal - m->vdisplay) / 2);
Rahul Sharma14829952013-06-18 18:19:37 +0530[diff] [blame]1889 hdmi_set_reg(core->v_blank_f0, 2, m->vtotal - m->vdisplay / 2);
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1890 hdmi_set_reg(core->v_blank_f1, 2, m->vtotal);
1891 hdmi_set_reg(core->v_sync_line_aft_2, 2, (m->vtotal / 2) + 7);
1892 hdmi_set_reg(core->v_sync_line_aft_1, 2, (m->vtotal / 2) + 2);
1893 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2,
1894 (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1895 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2,
1896 (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1897 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
1898 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
Rahul Sharma14829952013-06-18 18:19:37 +0530[diff] [blame]1899 hdmi_set_reg(tg->vact_st2, 2, m->vtotal - m->vdisplay / 2);
1900 hdmi_set_reg(tg->vsync2, 2, (m->vtotal / 2) + 1);
1901 hdmi_set_reg(tg->vsync_bot_hdmi, 2, (m->vtotal / 2) + 1);
1902 hdmi_set_reg(tg->field_bot_hdmi, 2, (m->vtotal / 2) + 1);
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1903 hdmi_set_reg(tg->vact_st3, 2, 0x0);
1904 hdmi_set_reg(tg->vact_st4, 2, 0x0);
1905 } else {
1906 /* Progressive Mode */
1907 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1908 m->vsync_end - m->vdisplay);
1909 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1910 m->vsync_start - m->vdisplay);
1911 hdmi_set_reg(core->v2_blank, 2, m->vtotal);
1912 hdmi_set_reg(core->v1_blank, 2, m->vtotal - m->vdisplay);
1913 hdmi_set_reg(core->v_blank_f0, 2, 0xffff);
1914 hdmi_set_reg(core->v_blank_f1, 2, 0xffff);
1915 hdmi_set_reg(core->v_sync_line_aft_2, 2, 0xffff);
1916 hdmi_set_reg(core->v_sync_line_aft_1, 2, 0xffff);
1917 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2, 0xffff);
1918 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2, 0xffff);
1919 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1920 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1921 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1922 hdmi_set_reg(tg->vact_st3, 2, 0x47b); /* Reset value */
1923 hdmi_set_reg(tg->vact_st4, 2, 0x6ae); /* Reset value */
Rahul Sharma14829952013-06-18 18:19:37 +0530[diff] [blame]1924 hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1925 hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1926 hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1927 }
1928
1929 /* Following values & calculations are same irrespective of mode type */
1930 hdmi_set_reg(core->h_sync_start, 2, m->hsync_start - m->hdisplay - 2);
1931 hdmi_set_reg(core->h_sync_end, 2, m->hsync_end - m->hdisplay - 2);
1932 hdmi_set_reg(core->vact_space_1, 2, 0xffff);
1933 hdmi_set_reg(core->vact_space_2, 2, 0xffff);
1934 hdmi_set_reg(core->vact_space_3, 2, 0xffff);
1935 hdmi_set_reg(core->vact_space_4, 2, 0xffff);
1936 hdmi_set_reg(core->vact_space_5, 2, 0xffff);
1937 hdmi_set_reg(core->vact_space_6, 2, 0xffff);
1938 hdmi_set_reg(core->v_blank_f2, 2, 0xffff);
1939 hdmi_set_reg(core->v_blank_f3, 2, 0xffff);
1940 hdmi_set_reg(core->v_blank_f4, 2, 0xffff);
1941 hdmi_set_reg(core->v_blank_f5, 2, 0xffff);
1942 hdmi_set_reg(core->v_sync_line_aft_3, 2, 0xffff);
1943 hdmi_set_reg(core->v_sync_line_aft_4, 2, 0xffff);
1944 hdmi_set_reg(core->v_sync_line_aft_5, 2, 0xffff);
1945 hdmi_set_reg(core->v_sync_line_aft_6, 2, 0xffff);
1946 hdmi_set_reg(core->v_sync_line_aft_pxl_3, 2, 0xffff);
1947 hdmi_set_reg(core->v_sync_line_aft_pxl_4, 2, 0xffff);
1948 hdmi_set_reg(core->v_sync_line_aft_pxl_5, 2, 0xffff);
1949 hdmi_set_reg(core->v_sync_line_aft_pxl_6, 2, 0xffff);
1950
1951 /* Timing generator registers */
1952 hdmi_set_reg(tg->cmd, 1, 0x0);
1953 hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1954 hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1955 hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1956 hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1957 hdmi_set_reg(tg->vsync, 2, 0x1);
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1958 hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1959 hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1960 hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1961 hdmi_set_reg(tg->tg_3d, 1, 0x0);
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1962}
1963
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]1964static void hdmi_mode_set(struct exynos_drm_display *display,
1965 struct drm_display_mode *mode)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1966{
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]1967 struct hdmi_context *hdata = display->ctx;
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1968 struct drm_display_mode *m = mode;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1969
YoungJun Chocbc4c332013-06-12 10:44:40 +0900[diff] [blame]1970 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%s\n",
1971 m->hdisplay, m->vdisplay,
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1972 m->vrefresh, (m->flags & DRM_MODE_FLAG_INTERLACE) ?
1973 "INTERLACED" : "PROGERESSIVE");
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1974
Rahul Sharmabfa48422014-04-03 20:41:04 +0530[diff] [blame]1975 /* preserve mode information for later use. */
1976 drm_mode_copy(&hdata->current_mode, mode);
1977
Sachin Kamat5f46c332013-04-26 11:29:00 +0530[diff] [blame]1978 if (hdata->type == HDMI_TYPE13)
Rahul Sharma6b986ed2013-03-06 17:33:29 +0900[diff] [blame]1979 hdmi_v13_mode_set(hdata, mode);
Sachin Kamat5f46c332013-04-26 11:29:00 +0530[diff] [blame]1980 else
Sean Paul2f7e2ed2013-01-15 08:11:08 -0500[diff] [blame]1981 hdmi_v14_mode_set(hdata, mode);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1982}
1983
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]1984static void hdmi_commit(struct exynos_drm_display *display)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1985{
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]1986 struct hdmi_context *hdata = display->ctx;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1987
Shirish Sdda90122013-01-23 22:03:18 -0500[diff] [blame]1988 mutex_lock(&hdata->hdmi_mutex);
1989 if (!hdata->powered) {
1990 mutex_unlock(&hdata->hdmi_mutex);
1991 return;
1992 }
1993 mutex_unlock(&hdata->hdmi_mutex);
1994
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1995 hdmi_conf_apply(hdata);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]1996}
1997
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]1998static void hdmi_poweron(struct exynos_drm_display *display)
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]1999{
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]2000 struct hdmi_context *hdata = display->ctx;
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2001 struct hdmi_resources *res = &hdata->res;
2002
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2003 mutex_lock(&hdata->hdmi_mutex);
2004 if (hdata->powered) {
2005 mutex_unlock(&hdata->hdmi_mutex);
2006 return;
2007 }
2008
2009 hdata->powered = true;
2010
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2011 mutex_unlock(&hdata->hdmi_mutex);
2012
Sean Paulaf65c802014-01-30 16:19:27 -0500[diff] [blame]2013 pm_runtime_get_sync(hdata->dev);
2014
Seung-Woo Kimad079452013-06-05 14:34:38 +0900[diff] [blame]2015 if (regulator_bulk_enable(res->regul_count, res->regul_bulk))
2016 DRM_DEBUG_KMS("failed to enable regulator bulk\n");
2017
Rahul Sharma049d34e2014-05-20 10:36:05 +0530[diff] [blame^]2018 /* set pmu hdmiphy control bit to enable hdmiphy */
2019 regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
2020 PMU_HDMI_PHY_ENABLE_BIT, 1);
2021
Sean Paul0bfb1f82013-06-11 12:24:02 +0530[diff] [blame]2022 clk_prepare_enable(res->hdmi);
2023 clk_prepare_enable(res->sclk_hdmi);
Rahul Sharmaa5562252012-11-28 11:30:25 +0530[diff] [blame]2024
2025 hdmiphy_poweron(hdata);
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]2026 hdmi_commit(display);
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2027}
2028
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]2029static void hdmi_poweroff(struct exynos_drm_display *display)
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2030{
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]2031 struct hdmi_context *hdata = display->ctx;
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2032 struct hdmi_resources *res = &hdata->res;
2033
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2034 mutex_lock(&hdata->hdmi_mutex);
2035 if (!hdata->powered)
2036 goto out;
2037 mutex_unlock(&hdata->hdmi_mutex);
2038
Rahul Sharmabfa48422014-04-03 20:41:04 +0530[diff] [blame]2039 /* HDMI System Disable */
2040 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_EN);
2041
Rahul Sharmaa5562252012-11-28 11:30:25 +0530[diff] [blame]2042 hdmiphy_poweroff(hdata);
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2043
Sean Paul724fd142014-05-09 15:05:10 +0900[diff] [blame]2044 cancel_delayed_work(&hdata->hotplug_work);
2045
Sean Paul0bfb1f82013-06-11 12:24:02 +0530[diff] [blame]2046 clk_disable_unprepare(res->sclk_hdmi);
2047 clk_disable_unprepare(res->hdmi);
Rahul Sharma049d34e2014-05-20 10:36:05 +0530[diff] [blame^]2048
2049 /* reset pmu hdmiphy control bit to disable hdmiphy */
2050 regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
2051 PMU_HDMI_PHY_ENABLE_BIT, 0);
2052
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2053 regulator_bulk_disable(res->regul_count, res->regul_bulk);
2054
Sean Paulaf65c802014-01-30 16:19:27 -0500[diff] [blame]2055 pm_runtime_put_sync(hdata->dev);
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2056
Sean Paulaf65c802014-01-30 16:19:27 -0500[diff] [blame]2057 mutex_lock(&hdata->hdmi_mutex);
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2058 hdata->powered = false;
2059
2060out:
2061 mutex_unlock(&hdata->hdmi_mutex);
2062}
2063
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]2064static void hdmi_dpms(struct exynos_drm_display *display, int mode)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2065{
YoungJun Chocbc4c332013-06-12 10:44:40 +0900[diff] [blame]2066 DRM_DEBUG_KMS("mode %d\n", mode);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2067
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2068 switch (mode) {
2069 case DRM_MODE_DPMS_ON:
Sean Paulaf65c802014-01-30 16:19:27 -0500[diff] [blame]2070 hdmi_poweron(display);
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2071 break;
2072 case DRM_MODE_DPMS_STANDBY:
2073 case DRM_MODE_DPMS_SUSPEND:
2074 case DRM_MODE_DPMS_OFF:
Sean Paulaf65c802014-01-30 16:19:27 -0500[diff] [blame]2075 hdmi_poweroff(display);
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2076 break;
2077 default:
2078 DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode);
2079 break;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2080 }
2081}
2082
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]2083static struct exynos_drm_display_ops hdmi_display_ops = {
Sean Pauld9716ee2014-01-30 16:19:29 -0500[diff] [blame]2084 .create_connector = hdmi_create_connector,
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]2085 .mode_fixup = hdmi_mode_fixup,
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2086 .mode_set = hdmi_mode_set,
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]2087 .dpms = hdmi_dpms,
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2088 .commit = hdmi_commit,
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2089};
2090
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]2091static struct exynos_drm_display hdmi_display = {
2092 .type = EXYNOS_DISPLAY_TYPE_HDMI,
2093 .ops = &hdmi_display_ops,
2094};
2095
Sean Paul724fd142014-05-09 15:05:10 +0900[diff] [blame]2096static void hdmi_hotplug_work_func(struct work_struct *work)
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2097{
Sean Paul724fd142014-05-09 15:05:10 +0900[diff] [blame]2098 struct hdmi_context *hdata;
2099
2100 hdata = container_of(work, struct hdmi_context, hotplug_work.work);
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2101
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2102 mutex_lock(&hdata->hdmi_mutex);
Tomasz Stanislawskifca57122012-10-04 20:48:46 +0530[diff] [blame]2103 hdata->hpd = gpio_get_value(hdata->hpd_gpio);
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2104 mutex_unlock(&hdata->hdmi_mutex);
2105
Sean Paul45517892014-01-30 16:19:05 -0500[diff] [blame]2106 if (hdata->drm_dev)
2107 drm_helper_hpd_irq_event(hdata->drm_dev);
Sean Paul724fd142014-05-09 15:05:10 +0900[diff] [blame]2108}
2109
2110static irqreturn_t hdmi_irq_thread(int irq, void *arg)
2111{
2112 struct hdmi_context *hdata = arg;
2113
2114 mod_delayed_work(system_wq, &hdata->hotplug_work,
2115 msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS));
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2116
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2117 return IRQ_HANDLED;
2118}
2119
Greg Kroah-Hartman56550d92012-12-21 15:09:25 -0800[diff] [blame]2120static int hdmi_resources_init(struct hdmi_context *hdata)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2121{
2122 struct device *dev = hdata->dev;
2123 struct hdmi_resources *res = &hdata->res;
2124 static char *supply[] = {
2125 "hdmi-en",
2126 "vdd",
2127 "vdd_osc",
2128 "vdd_pll",
2129 };
2130 int i, ret;
2131
2132 DRM_DEBUG_KMS("HDMI resource init\n");
2133
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2134 /* get clocks, power */
Sachin Kamat9f49d9f2012-11-23 14:13:27 +0530[diff] [blame]2135 res->hdmi = devm_clk_get(dev, "hdmi");
Sachin Kamatee7cbaf2013-03-21 15:33:57 +0530[diff] [blame]2136 if (IS_ERR(res->hdmi)) {
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2137 DRM_ERROR("failed to get clock 'hdmi'\n");
2138 goto fail;
2139 }
Sachin Kamat9f49d9f2012-11-23 14:13:27 +0530[diff] [blame]2140 res->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi");
Sachin Kamatee7cbaf2013-03-21 15:33:57 +0530[diff] [blame]2141 if (IS_ERR(res->sclk_hdmi)) {
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2142 DRM_ERROR("failed to get clock 'sclk_hdmi'\n");
2143 goto fail;
2144 }
Sachin Kamat9f49d9f2012-11-23 14:13:27 +0530[diff] [blame]2145 res->sclk_pixel = devm_clk_get(dev, "sclk_pixel");
Sachin Kamatee7cbaf2013-03-21 15:33:57 +0530[diff] [blame]2146 if (IS_ERR(res->sclk_pixel)) {
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2147 DRM_ERROR("failed to get clock 'sclk_pixel'\n");
2148 goto fail;
2149 }
Sachin Kamat9f49d9f2012-11-23 14:13:27 +0530[diff] [blame]2150 res->sclk_hdmiphy = devm_clk_get(dev, "sclk_hdmiphy");
Sachin Kamatee7cbaf2013-03-21 15:33:57 +0530[diff] [blame]2151 if (IS_ERR(res->sclk_hdmiphy)) {
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2152 DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n");
2153 goto fail;
2154 }
Rahul Sharma59956d32013-06-11 12:24:03 +0530[diff] [blame]2155 res->mout_hdmi = devm_clk_get(dev, "mout_hdmi");
2156 if (IS_ERR(res->mout_hdmi)) {
2157 DRM_ERROR("failed to get clock 'mout_hdmi'\n");
2158 goto fail;
2159 }
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2160
Rahul Sharma59956d32013-06-11 12:24:03 +0530[diff] [blame]2161 clk_set_parent(res->mout_hdmi, res->sclk_pixel);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2162
Sachin Kamat9f49d9f2012-11-23 14:13:27 +0530[diff] [blame]2163 res->regul_bulk = devm_kzalloc(dev, ARRAY_SIZE(supply) *
Sachin Kamatadc837a2012-08-31 15:50:47 +0530[diff] [blame]2164 sizeof(res->regul_bulk[0]), GFP_KERNEL);
Sachin Kamat38bb5252013-08-19 19:04:55 +0900[diff] [blame]2165 if (!res->regul_bulk)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2166 goto fail;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2167 for (i = 0; i < ARRAY_SIZE(supply); ++i) {
2168 res->regul_bulk[i].supply = supply[i];
2169 res->regul_bulk[i].consumer = NULL;
2170 }
Sachin Kamat9f49d9f2012-11-23 14:13:27 +0530[diff] [blame]2171 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(supply), res->regul_bulk);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2172 if (ret) {
2173 DRM_ERROR("failed to get regulators\n");
2174 goto fail;
2175 }
2176 res->regul_count = ARRAY_SIZE(supply);
2177
2178 return 0;
2179fail:
2180 DRM_ERROR("HDMI resource init - failed\n");
2181 return -ENODEV;
2182}
2183
Rahul Sharma22c4f422012-10-04 20:48:55 +0530[diff] [blame]2184static struct s5p_hdmi_platform_data *drm_hdmi_dt_parse_pdata
2185 (struct device *dev)
2186{
2187 struct device_node *np = dev->of_node;
2188 struct s5p_hdmi_platform_data *pd;
Rahul Sharma22c4f422012-10-04 20:48:55 +0530[diff] [blame]2189 u32 value;
2190
2191 pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
Sachin Kamat38bb5252013-08-19 19:04:55 +0900[diff] [blame]2192 if (!pd)
Rahul Sharma22c4f422012-10-04 20:48:55 +0530[diff] [blame]2193 goto err_data;
Rahul Sharma22c4f422012-10-04 20:48:55 +0530[diff] [blame]2194
2195 if (!of_find_property(np, "hpd-gpio", &value)) {
2196 DRM_ERROR("no hpd gpio property found\n");
2197 goto err_data;
2198 }
2199
Rahul Sharma5f916e22013-06-11 19:41:29 +0530[diff] [blame]2200 pd->hpd_gpio = of_get_named_gpio(np, "hpd-gpio", 0);
Rahul Sharma22c4f422012-10-04 20:48:55 +0530[diff] [blame]2201
2202 return pd;
2203
2204err_data:
2205 return NULL;
2206}
Rahul Sharma22c4f422012-10-04 20:48:55 +0530[diff] [blame]2207
Rahul Sharma22c4f422012-10-04 20:48:55 +0530[diff] [blame]2208static struct of_device_id hdmi_match_types[] = {
2209 {
2210 .compatible = "samsung,exynos5-hdmi",
Inki Daebfe4e842014-03-06 14:18:17 +0900[diff] [blame]2211 .data = &exynos5_hdmi_driver_data,
Tomasz Stanislawskic119ed02012-10-04 20:48:44 +0530[diff] [blame]2212 }, {
Rahul Sharmacc57caf2013-06-19 18:21:07 +0530[diff] [blame]2213 .compatible = "samsung,exynos4212-hdmi",
Inki Daebfe4e842014-03-06 14:18:17 +0900[diff] [blame]2214 .data = &exynos4212_hdmi_driver_data,
Rahul Sharmacc57caf2013-06-19 18:21:07 +0530[diff] [blame]2215 }, {
Rahul Sharmaa18a2dd2014-04-20 15:51:17 +0530[diff] [blame]2216 .compatible = "samsung,exynos5420-hdmi",
2217 .data = &exynos5420_hdmi_driver_data,
2218 }, {
Tomasz Stanislawskic119ed02012-10-04 20:48:44 +0530[diff] [blame]2219 /* end node */
2220 }
2221};
2222
Inki Daef37cd5e2014-05-09 14:25:20 +0900[diff] [blame]2223static int hdmi_bind(struct device *dev, struct device *master, void *data)
2224{
2225 struct drm_device *drm_dev = data;
2226 struct hdmi_context *hdata;
2227
2228 hdata = hdmi_display.ctx;
2229 hdata->drm_dev = drm_dev;
2230
2231 return exynos_drm_create_enc_conn(drm_dev, &hdmi_display);
2232}
2233
2234static void hdmi_unbind(struct device *dev, struct device *master, void *data)
2235{
2236 struct exynos_drm_display *display = get_hdmi_display(dev);
2237 struct drm_encoder *encoder = display->encoder;
2238 struct hdmi_context *hdata = display->ctx;
2239
2240 encoder->funcs->destroy(encoder);
2241 drm_connector_cleanup(&hdata->connector);
2242}
2243
2244static const struct component_ops hdmi_component_ops = {
2245 .bind = hdmi_bind,
2246 .unbind = hdmi_unbind,
2247};
2248
Inki Daee2a562d2014-05-09 16:46:10 +0900[diff] [blame]2249static struct device_node *hdmi_legacy_ddc_dt_binding(struct device *dev)
2250{
2251 const char *compatible_str = "samsung,exynos4210-hdmiddc";
2252 struct device_node *np;
2253
2254 np = of_find_compatible_node(NULL, NULL, compatible_str);
2255 if (np)
2256 return of_get_next_parent(np);
2257
2258 return NULL;
2259}
2260
2261static struct device_node *hdmi_legacy_phy_dt_binding(struct device *dev)
2262{
2263 const char *compatible_str = "samsung,exynos4212-hdmiphy";
2264
2265 return of_find_compatible_node(NULL, NULL, compatible_str);
2266}
2267
Greg Kroah-Hartman56550d92012-12-21 15:09:25 -0800[diff] [blame]2268static int hdmi_probe(struct platform_device *pdev)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2269{
Inki Daef37cd5e2014-05-09 14:25:20 +0900[diff] [blame]2270 struct device_node *ddc_node, *phy_node;
2271 struct s5p_hdmi_platform_data *pdata;
2272 struct hdmi_driver_data *drv_data;
2273 const struct of_device_id *match;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2274 struct device *dev = &pdev->dev;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2275 struct hdmi_context *hdata;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2276 struct resource *res;
2277 int ret;
2278
Inki Daef37cd5e2014-05-09 14:25:20 +0900[diff] [blame]2279 if (!dev->of_node)
Sachin Kamat88c49812013-08-28 10:47:57 +0530[diff] [blame]2280 return -ENODEV;
Rahul Sharma22c4f422012-10-04 20:48:55 +0530[diff] [blame]2281
Sachin Kamat88c49812013-08-28 10:47:57 +0530[diff] [blame]2282 pdata = drm_hdmi_dt_parse_pdata(dev);
2283 if (!pdata)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2284 return -EINVAL;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2285
Sachin Kamat88c49812013-08-28 10:47:57 +0530[diff] [blame]2286 hdata = devm_kzalloc(dev, sizeof(struct hdmi_context), GFP_KERNEL);
Sachin Kamat38bb5252013-08-19 19:04:55 +0900[diff] [blame]2287 if (!hdata)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2288 return -ENOMEM;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2289
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2290 mutex_init(&hdata->hdmi_mutex);
2291
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]2292 platform_set_drvdata(pdev, &hdmi_display);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2293
Sachin Kamat88c49812013-08-28 10:47:57 +0530[diff] [blame]2294 match = of_match_node(hdmi_match_types, dev->of_node);
2295 if (!match)
2296 return -ENODEV;
Inki Daebfe4e842014-03-06 14:18:17 +0900[diff] [blame]2297
2298 drv_data = (struct hdmi_driver_data *)match->data;
2299 hdata->type = drv_data->type;
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]2300 hdata->phy_confs = drv_data->phy_confs;
2301 hdata->phy_conf_count = drv_data->phy_conf_count;
Rahul Sharma22c4f422012-10-04 20:48:55 +0530[diff] [blame]2302
Tomasz Stanislawskifca57122012-10-04 20:48:46 +0530[diff] [blame]2303 hdata->hpd_gpio = pdata->hpd_gpio;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2304 hdata->dev = dev;
2305
2306 ret = hdmi_resources_init(hdata);
2307 if (ret) {
Rahul Sharma22c4f422012-10-04 20:48:55 +0530[diff] [blame]2308 DRM_ERROR("hdmi_resources_init failed\n");
Sachin Kamat9f49d9f2012-11-23 14:13:27 +0530[diff] [blame]2309 return -EINVAL;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2310 }
2311
2312 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Seung-Woo Kimd873ab92013-05-22 21:14:14 +0900[diff] [blame]2313 hdata->regs = devm_ioremap_resource(dev, res);
Thierry Redingd4ed6022013-01-21 11:09:02 +0100[diff] [blame]2314 if (IS_ERR(hdata->regs))
2315 return PTR_ERR(hdata->regs);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2316
Seung-Woo Kimd873ab92013-05-22 21:14:14 +0900[diff] [blame]2317 ret = devm_gpio_request(dev, hdata->hpd_gpio, "HPD");
Tomasz Stanislawskifca57122012-10-04 20:48:46 +0530[diff] [blame]2318 if (ret) {
2319 DRM_ERROR("failed to request HPD gpio\n");
Sachin Kamat9f49d9f2012-11-23 14:13:27 +0530[diff] [blame]2320 return ret;
Tomasz Stanislawskifca57122012-10-04 20:48:46 +0530[diff] [blame]2321 }
2322
Inki Daee2a562d2014-05-09 16:46:10 +0900[diff] [blame]2323 ddc_node = hdmi_legacy_ddc_dt_binding(dev);
2324 if (ddc_node)
2325 goto out_get_ddc_adpt;
2326
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2327 /* DDC i2c driver */
Daniel Kurtz2b768132014-02-24 18:52:51 +0900[diff] [blame]2328 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2329 if (!ddc_node) {
2330 DRM_ERROR("Failed to find ddc node in device tree\n");
2331 return -ENODEV;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2332 }
Inki Daee2a562d2014-05-09 16:46:10 +0900[diff] [blame]2333
2334out_get_ddc_adpt:
Inki Dae8fa04aa2014-03-13 16:38:31 +0900[diff] [blame]2335 hdata->ddc_adpt = of_find_i2c_adapter_by_node(ddc_node);
2336 if (!hdata->ddc_adpt) {
2337 DRM_ERROR("Failed to get ddc i2c adapter by node\n");
Daniel Kurtz2b768132014-02-24 18:52:51 +0900[diff] [blame]2338 return -ENODEV;
2339 }
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2340
Inki Daee2a562d2014-05-09 16:46:10 +0900[diff] [blame]2341 phy_node = hdmi_legacy_phy_dt_binding(dev);
2342 if (phy_node)
2343 goto out_get_phy_port;
2344
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2345 /* hdmiphy i2c driver */
Daniel Kurtz2b768132014-02-24 18:52:51 +0900[diff] [blame]2346 phy_node = of_parse_phandle(dev->of_node, "phy", 0);
2347 if (!phy_node) {
2348 DRM_ERROR("Failed to find hdmiphy node in device tree\n");
2349 ret = -ENODEV;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2350 goto err_ddc;
2351 }
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]2352
Inki Daee2a562d2014-05-09 16:46:10 +0900[diff] [blame]2353out_get_phy_port:
Rahul Sharmad5e9ca42014-05-09 15:34:18 +0900[diff] [blame]2354 if (drv_data->is_apb_phy) {
2355 hdata->regs_hdmiphy = of_iomap(phy_node, 0);
2356 if (!hdata->regs_hdmiphy) {
2357 DRM_ERROR("failed to ioremap hdmi phy\n");
2358 ret = -ENOMEM;
2359 goto err_ddc;
2360 }
2361 } else {
2362 hdata->hdmiphy_port = of_find_i2c_device_by_node(phy_node);
2363 if (!hdata->hdmiphy_port) {
2364 DRM_ERROR("Failed to get hdmi phy i2c client\n");
2365 ret = -ENODEV;
2366 goto err_ddc;
2367 }
Daniel Kurtz2b768132014-02-24 18:52:51 +0900[diff] [blame]2368 }
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2369
Sean Paul77006a72013-01-16 10:17:20 -0500[diff] [blame]2370 hdata->irq = gpio_to_irq(hdata->hpd_gpio);
2371 if (hdata->irq < 0) {
2372 DRM_ERROR("failed to get GPIO irq\n");
2373 ret = hdata->irq;
Joonyoung Shim66265a22012-04-23 19:35:49 +0900[diff] [blame]2374 goto err_hdmiphy;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2375 }
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2376
Tomasz Stanislawskifca57122012-10-04 20:48:46 +0530[diff] [blame]2377 hdata->hpd = gpio_get_value(hdata->hpd_gpio);
2378
Sean Paul724fd142014-05-09 15:05:10 +0900[diff] [blame]2379 INIT_DELAYED_WORK(&hdata->hotplug_work, hdmi_hotplug_work_func);
2380
Seung-Woo Kimdcb9a7c2013-05-22 21:14:17 +0900[diff] [blame]2381 ret = devm_request_threaded_irq(dev, hdata->irq, NULL,
Sean Paul77006a72013-01-16 10:17:20 -0500[diff] [blame]2382 hdmi_irq_thread, IRQF_TRIGGER_RISING |
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2383 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]2384 "hdmi", hdata);
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2385 if (ret) {
Sean Paul77006a72013-01-16 10:17:20 -0500[diff] [blame]2386 DRM_ERROR("failed to register hdmi interrupt\n");
Joonyoung Shimcf8fc4f2012-04-23 19:35:50 +0900[diff] [blame]2387 goto err_hdmiphy;
2388 }
2389
Rahul Sharma049d34e2014-05-20 10:36:05 +0530[diff] [blame^]2390 hdata->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
2391 "samsung,syscon-phandle");
2392 if (IS_ERR(hdata->pmureg)) {
2393 DRM_ERROR("syscon regmap lookup failed.\n");
2394 goto err_hdmiphy;
2395 }
2396
Sean Paulaf65c802014-01-30 16:19:27 -0500[diff] [blame]2397 pm_runtime_enable(dev);
Sean Paulf041b252014-01-30 16:19:15 -0500[diff] [blame]2398 hdmi_display.ctx = hdata;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2399
Inki Daef37cd5e2014-05-09 14:25:20 +0900[diff] [blame]2400 return exynos_drm_component_add(&pdev->dev, &hdmi_component_ops);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2401
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2402err_hdmiphy:
Paul Taysomb21a3bf2014-05-09 15:06:28 +0900[diff] [blame]2403 if (hdata->hdmiphy_port)
2404 put_device(&hdata->hdmiphy_port->dev);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2405err_ddc:
Inki Dae8fa04aa2014-03-13 16:38:31 +0900[diff] [blame]2406 put_device(&hdata->ddc_adpt->dev);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2407 return ret;
2408}
2409
Greg Kroah-Hartman56550d92012-12-21 15:09:25 -0800[diff] [blame]2410static int hdmi_remove(struct platform_device *pdev)
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2411{
Inki Daef37cd5e2014-05-09 14:25:20 +0900[diff] [blame]2412 struct hdmi_context *hdata = hdmi_display.ctx;
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2413
Sean Paul724fd142014-05-09 15:05:10 +0900[diff] [blame]2414 cancel_delayed_work_sync(&hdata->hotplug_work);
2415
Daniel Kurtz2b768132014-02-24 18:52:51 +0900[diff] [blame]2416 put_device(&hdata->hdmiphy_port->dev);
Inki Dae8fa04aa2014-03-13 16:38:31 +0900[diff] [blame]2417 put_device(&hdata->ddc_adpt->dev);
Inki Daef37cd5e2014-05-09 14:25:20 +0900[diff] [blame]2418
Sean Paulaf65c802014-01-30 16:19:27 -0500[diff] [blame]2419 pm_runtime_disable(&pdev->dev);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2420
Inki Daef37cd5e2014-05-09 14:25:20 +0900[diff] [blame]2421 exynos_drm_component_del(&pdev->dev, &hdmi_component_ops);
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2422 return 0;
2423}
2424
2425struct platform_driver hdmi_driver = {
2426 .probe = hdmi_probe,
Greg Kroah-Hartman56550d92012-12-21 15:09:25 -0800[diff] [blame]2427 .remove = hdmi_remove,
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2428 .driver = {
Rahul Sharma22c4f422012-10-04 20:48:55 +0530[diff] [blame]2429 .name = "exynos-hdmi",
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2430 .owner = THIS_MODULE,
Sachin Kamat88c49812013-08-28 10:47:57 +0530[diff] [blame]2431 .of_match_table = hdmi_match_types,
Seung-Woo Kimd8408322011-12-21 17:39:39 +0900[diff] [blame]2432 },
2433};