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Jan Glaubera755a452012-11-29 12:55:21 +01001#ifndef _ASM_S390_PCI_CLP_H
2#define _ASM_S390_PCI_CLP_H
3
4#include <asm/clp.h>
5
6/*
7 * Call Logical Processor - Command Codes
8 */
9#define CLP_LIST_PCI 0x0002
10#define CLP_QUERY_PCI_FN 0x0003
11#define CLP_QUERY_PCI_FNGRP 0x0004
12#define CLP_SET_PCI_FN 0x0005
13
14/* PCI function handle list entry */
15struct clp_fh_list_entry {
16 u16 device_id;
17 u16 vendor_id;
18 u32 config_state : 1;
19 u32 : 31;
20 u32 fid; /* PCI function id */
21 u32 fh; /* PCI function handle */
22} __packed;
23
24#define CLP_RC_SETPCIFN_FH 0x0101 /* Invalid PCI fn handle */
25#define CLP_RC_SETPCIFN_FHOP 0x0102 /* Fn handle not valid for op */
26#define CLP_RC_SETPCIFN_DMAAS 0x0103 /* Invalid DMA addr space */
27#define CLP_RC_SETPCIFN_RES 0x0104 /* Insufficient resources */
28#define CLP_RC_SETPCIFN_ALRDY 0x0105 /* Fn already in requested state */
29#define CLP_RC_SETPCIFN_ERR 0x0106 /* Fn in permanent error state */
30#define CLP_RC_SETPCIFN_RECPND 0x0107 /* Error recovery pending */
31#define CLP_RC_SETPCIFN_BUSY 0x0108 /* Fn busy */
32#define CLP_RC_LISTPCI_BADRT 0x010a /* Resume token not recognized */
33#define CLP_RC_QUERYPCIFG_PFGID 0x010b /* Unrecognized PFGID */
34
35/* request or response block header length */
36#define LIST_PCI_HDR_LEN 32
37
38/* Number of function handles fitting in response block */
39#define CLP_FH_LIST_NR_ENTRIES \
40 ((CLP_BLK_SIZE - 2 * LIST_PCI_HDR_LEN) \
41 / sizeof(struct clp_fh_list_entry))
42
43#define CLP_SET_ENABLE_PCI_FN 0 /* Yes, 0 enables it */
44#define CLP_SET_DISABLE_PCI_FN 1 /* Yes, 1 disables it */
45
46#define CLP_UTIL_STR_LEN 64
Sebastian Ottac4995b2014-04-16 16:12:05 +020047#define CLP_PFIP_NR_SEGMENTS 4
Jan Glaubera755a452012-11-29 12:55:21 +010048
Sebastian Ott5c5afd02016-01-27 13:33:30 +010049extern bool zpci_unique_uid;
50
Jan Glaubera755a452012-11-29 12:55:21 +010051/* List PCI functions request */
52struct clp_req_list_pci {
53 struct clp_req_hdr hdr;
Jan Glaubera755a452012-11-29 12:55:21 +010054 u64 resume_token;
55 u64 reserved2;
56} __packed;
57
58/* List PCI functions response */
59struct clp_rsp_list_pci {
60 struct clp_rsp_hdr hdr;
Jan Glaubera755a452012-11-29 12:55:21 +010061 u64 resume_token;
62 u32 reserved2;
63 u16 max_fn;
Sebastian Ott5c5afd02016-01-27 13:33:30 +010064 u8 : 7;
65 u8 uid_checking : 1;
Jan Glaubera755a452012-11-29 12:55:21 +010066 u8 entry_size;
67 struct clp_fh_list_entry fh_list[CLP_FH_LIST_NR_ENTRIES];
68} __packed;
69
70/* Query PCI function request */
71struct clp_req_query_pci {
72 struct clp_req_hdr hdr;
Jan Glaubera755a452012-11-29 12:55:21 +010073 u32 fh; /* function handle */
74 u32 reserved2;
75 u64 reserved3;
76} __packed;
77
78/* Query PCI function response */
79struct clp_rsp_query_pci {
80 struct clp_rsp_hdr hdr;
Jan Glaubera755a452012-11-29 12:55:21 +010081 u16 vfn; /* virtual fn number */
82 u16 : 7;
83 u16 util_str_avail : 1; /* utility string available? */
84 u16 pfgid : 8; /* pci function group id */
85 u32 fid; /* pci function id */
86 u8 bar_size[PCI_BAR_COUNT];
87 u16 pchid;
88 u32 bar[PCI_BAR_COUNT];
Sebastian Ottac4995b2014-04-16 16:12:05 +020089 u8 pfip[CLP_PFIP_NR_SEGMENTS]; /* pci function internal path */
Sebastian Ott0b7589e2016-06-15 13:07:51 +020090 u32 : 16;
91 u8 fmb_len;
Sebastian Ottac4995b2014-04-16 16:12:05 +020092 u8 pft; /* pci function type */
Jan Glaubera755a452012-11-29 12:55:21 +010093 u64 sdma; /* start dma as */
94 u64 edma; /* end dma as */
Sebastian Ottac4995b2014-04-16 16:12:05 +020095 u32 reserved[11];
96 u32 uid; /* user defined id */
Jan Glaubera755a452012-11-29 12:55:21 +010097 u8 util_str[CLP_UTIL_STR_LEN]; /* utility string */
98} __packed;
99
100/* Query PCI function group request */
101struct clp_req_query_pci_grp {
102 struct clp_req_hdr hdr;
Martin Schwidefsky988b86e62016-01-13 12:54:28 +0100103 u32 reserved2 : 24;
Jan Glaubera755a452012-11-29 12:55:21 +0100104 u32 pfgid : 8; /* function group id */
Martin Schwidefsky988b86e62016-01-13 12:54:28 +0100105 u32 reserved3;
106 u64 reserved4;
Jan Glaubera755a452012-11-29 12:55:21 +0100107} __packed;
108
109/* Query PCI function group response */
110struct clp_rsp_query_pci_grp {
111 struct clp_rsp_hdr hdr;
Jan Glaubera755a452012-11-29 12:55:21 +0100112 u16 : 4;
113 u16 noi : 12; /* number of interrupts */
114 u8 version;
115 u8 : 6;
116 u8 frame : 1;
117 u8 refresh : 1; /* TLB refresh mode */
118 u16 reserved2;
119 u16 mui;
120 u64 reserved3;
121 u64 dasm; /* dma address space mask */
122 u64 msia; /* MSI address */
123 u64 reserved4;
124 u64 reserved5;
125} __packed;
126
127/* Set PCI function request */
128struct clp_req_set_pci {
129 struct clp_req_hdr hdr;
Jan Glaubera755a452012-11-29 12:55:21 +0100130 u32 fh; /* function handle */
131 u16 reserved2;
132 u8 oc; /* operation controls */
133 u8 ndas; /* number of dma spaces */
134 u64 reserved3;
135} __packed;
136
137/* Set PCI function response */
138struct clp_rsp_set_pci {
139 struct clp_rsp_hdr hdr;
Jan Glaubera755a452012-11-29 12:55:21 +0100140 u32 fh; /* function handle */
141 u32 reserved3;
142 u64 reserved4;
143} __packed;
144
145/* Combined request/response block structures used by clp insn */
146struct clp_req_rsp_list_pci {
147 struct clp_req_list_pci request;
148 struct clp_rsp_list_pci response;
149} __packed;
150
151struct clp_req_rsp_set_pci {
152 struct clp_req_set_pci request;
153 struct clp_rsp_set_pci response;
154} __packed;
155
156struct clp_req_rsp_query_pci {
157 struct clp_req_query_pci request;
158 struct clp_rsp_query_pci response;
159} __packed;
160
161struct clp_req_rsp_query_pci_grp {
162 struct clp_req_query_pci_grp request;
163 struct clp_rsp_query_pci_grp response;
164} __packed;
165
166#endif