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Bjorn Helgaas8cfab3c2018-01-26 12:50:27 -06001/* SPDX-License-Identifier: GPL-2.0 */
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -06002/*
3 * Keystone PCI Controller's common includes
4 *
5 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
6 * http://www.ti.com
7 *
8 * Author: Murali Karicheri <m-karicheri2@ti.com>
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -06009 */
10
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -060011#define MAX_MSI_HOST_IRQS 8
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -060012
13struct keystone_pcie {
Kishon Vijay Abraham I442ec4c2017-02-15 18:48:14 +053014 struct dw_pcie *pci;
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -060015 struct clk *clk;
Murali Karicheri8665a482014-09-10 13:12:39 -040016 /* PCI Device ID */
17 u32 device_id;
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -060018 int num_legacy_host_irqs;
Bjorn Helgaasda4c4be2017-08-15 16:27:57 -050019 int legacy_host_irqs[PCI_NUM_INTX];
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -060020 struct device_node *legacy_intc_np;
21
22 int num_msi_host_irqs;
23 int msi_host_irqs[MAX_MSI_HOST_IRQS];
24 struct device_node *msi_intc_np;
25 struct irq_domain *legacy_irq_domain;
Murali Karicheri025dd3d2016-04-11 10:50:30 -040026 struct device_node *np;
27
28 int error_irq;
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -060029
30 /* Application register space */
Bjorn Helgaas4841f3ad2016-10-06 13:36:57 -050031 void __iomem *va_app_base; /* DT 1st resource */
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -060032 struct resource app;
33};
34
35/* Keystone DW specific MSI controller APIs/definitions */
36void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset);
Lucas Stach98a97e62015-09-18 13:58:35 -050037phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp);
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -060038
39/* Keystone specific PCI controller APIs */
40void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie);
41void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset);
Bjorn Helgaas5649e4c2016-10-06 13:36:56 -050042void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie);
43irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie);
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -060044int ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
45 struct device_node *msi_intc_np);
46int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
47 unsigned int devfn, int where, int size, u32 val);
48int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
49 unsigned int devfn, int where, int size, u32 *val);
50void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie);
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -060051void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie);
Gustavo Pimentel7c5925a2018-03-06 11:54:53 +000052void ks_dw_pcie_msi_irq_ack(int i, struct pcie_port *pp);
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -060053void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq);
54void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq);
55void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp);
Gustavo Pimentel3f43ccc2018-03-06 11:54:54 +000056int ks_dw_pcie_msi_host_init(struct pcie_port *pp);
Kishon Vijay Abraham I442ec4c2017-02-15 18:48:14 +053057int ks_dw_pcie_link_up(struct dw_pcie *pci);