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Maxime Ripardd3ae0782013-06-09 10:40:53 +02001/*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
Maxime Ripard1d86b4b2014-09-02 19:25:26 +02006 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
Maxime Ripardd3ae0782013-06-09 10:40:53 +020010 *
Maxime Ripard1d86b4b2014-09-02 19:25:26 +020011 * a) This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
Maxime Ripard1d86b4b2014-09-02 19:25:26 +020021 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
Maxime Ripardd3ae0782013-06-09 10:40:53 +020043 */
44
Maxime Ripard71455702014-12-16 22:59:54 +010045#include "skeleton.dtsi"
Maxime Ripardd3ae0782013-06-09 10:40:53 +020046
Maxime Ripard903b2d72015-01-30 16:42:13 +010047#include "sun5i.dtsi"
48
Maxime Ripard1f9f6a72014-12-16 22:59:56 +010049#include <dt-bindings/dma/sun4i-a10.h>
Maxime Ripard092a0c32014-12-16 22:59:57 +010050#include <dt-bindings/pinctrl/sun4i-a10.h>
Maxime Ripardd3ae0782013-06-09 10:40:53 +020051
52/ {
53 interrupt-parent = <&intc>;
54
Emilio Lópeze751cce2013-11-16 15:17:29 -030055 aliases {
56 ethernet0 = &emac;
57 };
58
Hans de Goeded5018412014-11-14 16:34:35 +010059 chosen {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 ranges;
63
Hans de Goedea9f8cda2014-11-18 12:07:13 +010064 framebuffer@0 {
Maxime Ripardd8cacaa2015-05-03 11:53:07 +020065 compatible = "allwinner,simple-framebuffer",
66 "simple-framebuffer";
Hans de Goedea9f8cda2014-11-18 12:07:13 +010067 allwinner,pipeline = "de_be0-lcd0-hdmi";
Hans de Goede678e75d2014-11-16 17:09:32 +010068 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
69 <&ahb_gates 44>;
Hans de Goeded5018412014-11-14 16:34:35 +010070 status = "disabled";
71 };
Hans de Goedefd18c7e2015-01-19 14:05:12 +010072
73 framebuffer@1 {
74 compatible = "allwinner,simple-framebuffer",
75 "simple-framebuffer";
76 allwinner,pipeline = "de_be0-lcd0";
77 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
78 status = "disabled";
79 };
Hans de Goeded5018412014-11-14 16:34:35 +010080 };
81
Maxime Ripardd3ae0782013-06-09 10:40:53 +020082 clocks {
Chen-Yu Tsai3dce8322014-02-03 09:51:42 +080083 ahb_gates: clk@01c20060 {
Maxime Ripardd3ae0782013-06-09 10:40:53 +020084 #clock-cells = <1>;
Maxime Ripard29bb8052013-07-16 11:28:58 +020085 compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
Maxime Ripardd3ae0782013-06-09 10:40:53 +020086 reg = <0x01c20060 0x8>;
87 clocks = <&ahb>;
Maxime Ripardd8cacaa2015-05-03 11:53:07 +020088 clock-output-names = "ahb_usbotg", "ahb_ehci",
89 "ahb_ohci", "ahb_ss", "ahb_dma",
90 "ahb_bist", "ahb_mmc0", "ahb_mmc1",
91 "ahb_mmc2", "ahb_nand",
92 "ahb_sdram", "ahb_emac", "ahb_ts",
93 "ahb_spi0", "ahb_spi1", "ahb_spi2",
94 "ahb_gps", "ahb_stimer", "ahb_ve",
95 "ahb_tve", "ahb_lcd", "ahb_csi",
96 "ahb_hdmi", "ahb_de_be",
97 "ahb_de_fe", "ahb_iep",
98 "ahb_mali400";
Maxime Ripardd3ae0782013-06-09 10:40:53 +020099 };
100
Chen-Yu Tsai3dce8322014-02-03 09:51:42 +0800101 apb0_gates: clk@01c20068 {
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200102 #clock-cells = <1>;
Maxime Ripard29bb8052013-07-16 11:28:58 +0200103 compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200104 reg = <0x01c20068 0x4>;
105 clocks = <&apb0>;
Maxime Ripardd8cacaa2015-05-03 11:53:07 +0200106 clock-output-names = "apb0_codec", "apb0_iis",
107 "apb0_pio", "apb0_ir",
108 "apb0_keypad";
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200109 };
110
Chen-Yu Tsai3dce8322014-02-03 09:51:42 +0800111 apb1_gates: clk@01c2006c {
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200112 #clock-cells = <1>;
Maxime Ripard29bb8052013-07-16 11:28:58 +0200113 compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200114 reg = <0x01c2006c 0x4>;
115 clocks = <&apb1>;
116 clock-output-names = "apb1_i2c0", "apb1_i2c1",
Maxime Ripard29bb8052013-07-16 11:28:58 +0200117 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
118 "apb1_uart2", "apb1_uart3";
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200119 };
120 };
121
Maxime Ripard9e199292013-08-03 16:07:36 +0200122 soc@01c00000 {
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200123 emac: ethernet@01c0b000 {
Maxime Ripard1c70e092014-02-02 14:49:13 +0100124 compatible = "allwinner,sun4i-a10-emac";
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200125 reg = <0x01c0b000 0x1000>;
126 interrupts = <55>;
127 clocks = <&ahb_gates 17>;
Maxime Ripard00f69ba2015-03-26 15:53:44 +0100128 allwinner,sram = <&emac_sram 1>;
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200129 status = "disabled";
130 };
131
Aleksei Mamlin92395f52015-01-19 22:35:22 +0300132 mdio: mdio@01c0b080 {
Maxime Ripard1c70e092014-02-02 14:49:13 +0100133 compatible = "allwinner,sun4i-a10-mdio";
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200134 reg = <0x01c0b080 0x14>;
135 status = "disabled";
136 #address-cells = <1>;
137 #size-cells = <0>;
138 };
139
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200140 uart0: serial@01c28000 {
141 compatible = "snps,dw-apb-uart";
142 reg = <0x01c28000 0x400>;
143 interrupts = <1>;
144 reg-shift = <2>;
145 reg-io-width = <4>;
146 clocks = <&apb1_gates 16>;
147 status = "disabled";
148 };
149
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200150 uart2: serial@01c28800 {
151 compatible = "snps,dw-apb-uart";
152 reg = <0x01c28800 0x400>;
153 interrupts = <3>;
154 reg-shift = <2>;
155 reg-io-width = <4>;
156 clocks = <&apb1_gates 18>;
157 status = "disabled";
158 };
Maxime Ripard903b2d72015-01-30 16:42:13 +0100159 };
160};
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200161
Maxime Ripard903b2d72015-01-30 16:42:13 +0100162&pio {
163 compatible = "allwinner,sun5i-a10s-pinctrl";
Emilio Lópezca3d4ed2013-07-07 18:31:57 -0300164
Maxime Ripard903b2d72015-01-30 16:42:13 +0100165 uart0_pins_a: uart0@0 {
166 allwinner,pins = "PB19", "PB20";
167 allwinner,function = "uart0";
168 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
169 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
170 };
Maxime Ripardf2b50022013-11-07 12:01:48 +0100171
Maxime Ripard903b2d72015-01-30 16:42:13 +0100172 uart2_pins_a: uart2@0 {
173 allwinner,pins = "PC18", "PC19";
174 allwinner,function = "uart2";
175 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
176 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
177 };
178
179 uart3_pins_a: uart3@0 {
180 allwinner,pins = "PG9", "PG10";
181 allwinner,function = "uart3";
182 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
183 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
184 };
185
186 emac_pins_a: emac0@0 {
187 allwinner,pins = "PA0", "PA1", "PA2",
188 "PA3", "PA4", "PA5", "PA6",
189 "PA7", "PA8", "PA9", "PA10",
190 "PA11", "PA12", "PA13", "PA14",
191 "PA15", "PA16";
192 allwinner,function = "emac";
193 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
194 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
195 };
196
197 mmc1_pins_a: mmc1@0 {
Maxime Ripardd8cacaa2015-05-03 11:53:07 +0200198 allwinner,pins = "PG3", "PG4", "PG5",
199 "PG6", "PG7", "PG8";
Maxime Ripard903b2d72015-01-30 16:42:13 +0100200 allwinner,function = "mmc1";
201 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
202 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200203 };
204};
Maxime Ripard00f69ba2015-03-26 15:53:44 +0100205
206&sram_a {
207 emac_sram: sram-section@8000 {
208 compatible = "allwinner,sun4i-a10-sram-a3-a4";
209 reg = <0x8000 0x4000>;
210 status = "disabled";
211 };
212};