blob: 340d81108df1a232fcefe64c81bdb9372a4c814c [file] [log] [blame]
Stephen Warrenc80efba2012-04-20 16:57:38 -06001/dts-v1/;
2
Laxman Dewangan6bccbd52013-12-02 18:39:57 +05303#include <dt-bindings/input/input.h>
Stephen Warren1bd0bd42012-10-17 16:38:21 -06004#include "tegra20.dtsi"
Stephen Warrenc80efba2012-04-20 16:57:38 -06005
6/ {
Bryan Wu8fef5df2012-12-20 09:41:29 +00007 model = "NVIDIA Tegra20 Whistler evaluation board";
Stephen Warrenc80efba2012-04-20 16:57:38 -06008 compatible = "nvidia,whistler", "nvidia,tegra20";
9
Stephen Warren553c0a22013-12-09 14:43:59 -070010 aliases {
11 rtc0 = "/i2c@7000d000/max8907@3c";
12 rtc1 = "/rtc@7000e000";
Olof Johanssonc4574aa2014-11-11 12:49:30 -080013 serial0 = &uarta;
Stephen Warren553c0a22013-12-09 14:43:59 -070014 };
15
Stephen Warrenc80efba2012-04-20 16:57:38 -060016 memory {
17 reg = <0x00000000 0x20000000>;
18 };
19
Stephen Warren58ecb232013-11-25 17:53:16 -070020 host1x@50000000 {
21 hdmi@54280000 {
Stephen Warren2658ef12012-11-16 10:53:04 -070022 status = "okay";
23
24 vdd-supply = <&hdmi_vdd_reg>;
25 pll-supply = <&hdmi_pll_reg>;
26
27 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -070028 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
29 GPIO_ACTIVE_HIGH>;
Stephen Warren2658ef12012-11-16 10:53:04 -070030 };
31 };
32
Stephen Warren58ecb232013-11-25 17:53:16 -070033 pinmux@70000014 {
Stephen Warrenc80efba2012-04-20 16:57:38 -060034 pinctrl-names = "default";
35 pinctrl-0 = <&state_default>;
36
37 state_default: pinmux {
38 ata {
39 nvidia,pins = "ata", "atb", "ate", "gma", "gmb",
40 "gmc", "gmd", "gpu";
41 nvidia,function = "gmi";
42 };
43 atc {
44 nvidia,pins = "atc", "atd";
45 nvidia,function = "sdio4";
46 };
47 cdev1 {
48 nvidia,pins = "cdev1";
49 nvidia,function = "plla_out";
50 };
51 cdev2 {
52 nvidia,pins = "cdev2";
53 nvidia,function = "osc";
54 };
55 crtp {
56 nvidia,pins = "crtp";
57 nvidia,function = "crt";
58 };
59 csus {
60 nvidia,pins = "csus";
61 nvidia,function = "vi_sensor_clk";
62 };
63 dap1 {
64 nvidia,pins = "dap1";
65 nvidia,function = "dap1";
66 };
67 dap2 {
68 nvidia,pins = "dap2";
69 nvidia,function = "dap2";
70 };
71 dap3 {
72 nvidia,pins = "dap3";
73 nvidia,function = "dap3";
74 };
75 dap4 {
76 nvidia,pins = "dap4";
77 nvidia,function = "dap4";
78 };
79 ddc {
80 nvidia,pins = "ddc";
81 nvidia,function = "i2c2";
82 };
83 dta {
84 nvidia,pins = "dta", "dtb", "dtc", "dtd";
85 nvidia,function = "vi";
86 };
87 dte {
88 nvidia,pins = "dte";
89 nvidia,function = "rsvd1";
90 };
91 dtf {
92 nvidia,pins = "dtf";
93 nvidia,function = "i2c3";
94 };
95 gme {
96 nvidia,pins = "gme";
97 nvidia,function = "dap5";
98 };
99 gpu7 {
100 nvidia,pins = "gpu7";
101 nvidia,function = "rtck";
102 };
103 gpv {
104 nvidia,pins = "gpv";
105 nvidia,function = "pcie";
106 };
107 hdint {
108 nvidia,pins = "hdint", "pta";
109 nvidia,function = "hdmi";
110 };
111 i2cp {
112 nvidia,pins = "i2cp";
113 nvidia,function = "i2cp";
114 };
115 irrx {
116 nvidia,pins = "irrx", "irtx";
117 nvidia,function = "uartb";
118 };
119 kbca {
120 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
121 nvidia,function = "kbc";
122 };
123 kbcb {
124 nvidia,pins = "kbcb", "kbcd";
125 nvidia,function = "sdio2";
126 };
127 lcsn {
128 nvidia,pins = "lcsn", "lsck", "lsda", "lsdi",
129 "spia", "spib", "spic";
130 nvidia,function = "spi3";
131 };
132 ld0 {
133 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
134 "ld5", "ld6", "ld7", "ld8", "ld9",
135 "ld10", "ld11", "ld12", "ld13", "ld14",
136 "ld15", "ld16", "ld17", "ldc", "ldi",
137 "lhp0", "lhp1", "lhp2", "lhs", "lm0",
138 "lm1", "lpp", "lpw0", "lpw1", "lpw2",
139 "lsc0", "lsc1", "lspi", "lvp0", "lvp1",
140 "lvs";
141 nvidia,function = "displaya";
142 };
143 owc {
144 nvidia,pins = "owc", "uac";
145 nvidia,function = "owr";
146 };
147 pmc {
148 nvidia,pins = "pmc";
149 nvidia,function = "pwr_on";
150 };
151 rm {
152 nvidia,pins = "rm";
153 nvidia,function = "i2c1";
154 };
155 sdb {
156 nvidia,pins = "sdb", "sdc", "sdd", "slxa",
157 "slxc", "slxd", "slxk";
158 nvidia,function = "sdio3";
159 };
160 sdio1 {
161 nvidia,pins = "sdio1";
162 nvidia,function = "sdio1";
163 };
164 spdi {
165 nvidia,pins = "spdi", "spdo";
166 nvidia,function = "rsvd2";
167 };
168 spid {
169 nvidia,pins = "spid", "spie", "spig", "spih";
170 nvidia,function = "spi2_alt";
171 };
172 spif {
173 nvidia,pins = "spif";
174 nvidia,function = "spi2";
175 };
176 uaa {
177 nvidia,pins = "uaa", "uab";
178 nvidia,function = "uarta";
179 };
180 uad {
181 nvidia,pins = "uad";
182 nvidia,function = "irda";
183 };
184 uca {
185 nvidia,pins = "uca", "ucb";
186 nvidia,function = "uartc";
187 };
188 uda {
189 nvidia,pins = "uda";
190 nvidia,function = "spi1";
191 };
192 conf_ata {
193 nvidia,pins = "ata", "atb", "atc", "ddc", "gma",
194 "gmb", "gmc", "gmd", "irrx", "irtx",
195 "kbca", "kbcb", "kbcc", "kbcd", "kbce",
196 "kbcf", "sdc", "sdd", "spie", "spig",
197 "spih", "uaa", "uab", "uad", "uca",
198 "ucb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530199 nvidia,pull = <TEGRA_PIN_PULL_UP>;
200 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600201 };
202 conf_atd {
203 nvidia,pins = "atd", "ate", "cdev1", "csus",
204 "dap1", "dap2", "dap3", "dap4", "dte",
205 "dtf", "gpu", "gpu7", "gpv", "i2cp",
206 "rm", "sdio1", "slxa", "slxc", "slxd",
207 "slxk", "spdi", "spdo", "uac", "uda";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530208 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
209 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600210 };
211 conf_cdev2 {
212 nvidia,pins = "cdev2", "spia", "spib";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530213 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
214 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600215 };
216 conf_ck32 {
217 nvidia,pins = "ck32", "ddrc", "lc", "pmca",
218 "pmcb", "pmcc", "pmcd", "xm2c",
219 "xm2d";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530220 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600221 };
222 conf_crtp {
223 nvidia,pins = "crtp";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530224 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
225 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600226 };
227 conf_dta {
228 nvidia,pins = "dta", "dtb", "dtc", "dtd",
229 "spid", "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530230 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
231 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600232 };
233 conf_gme {
234 nvidia,pins = "gme", "owc", "pta", "spic";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530235 nvidia,pull = <TEGRA_PIN_PULL_UP>;
236 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600237 };
238 conf_ld17_0 {
239 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
240 "ld23_22";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530241 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600242 };
243 conf_ls {
244 nvidia,pins = "ls", "pmce";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530245 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600246 };
247 drive_dap1 {
248 nvidia,pins = "drive_dap1";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530249 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
250 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
251 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_8>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600252 nvidia,pull-down-strength = <0>;
253 nvidia,pull-up-strength = <0>;
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530254 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
255 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600256 };
257 };
258 };
259
260 i2s@70002800 {
261 status = "okay";
262 };
263
264 serial@70006000 {
265 status = "okay";
Stephen Warrenc80efba2012-04-20 16:57:38 -0600266 };
267
Stephen Warren2658ef12012-11-16 10:53:04 -0700268 hdmi_ddc: i2c@7000c400 {
269 status = "okay";
270 clock-frequency = <100000>;
271 };
272
Stephen Warrenc80efba2012-04-20 16:57:38 -0600273 i2c@7000d000 {
274 status = "okay";
275 clock-frequency = <100000>;
276
277 codec: codec@1a {
278 compatible = "wlf,wm8753";
279 reg = <0x1a>;
280 };
281
282 tca6416: gpio@20 {
283 compatible = "ti,tca6416";
284 reg = <0x20>;
285 gpio-controller;
286 #gpio-cells = <2>;
287 };
Stephen Warrene7765b32012-06-25 16:41:25 -0600288
289 max8907@3c {
290 compatible = "maxim,max8907";
291 reg = <0x3c>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700292 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Stephen Warrene7765b32012-06-25 16:41:25 -0600293
Stephen Warrenb37ed4a2012-09-11 13:13:05 -0600294 maxim,system-power-controller;
295
Stephen Warrene7765b32012-06-25 16:41:25 -0600296 mbatt-supply = <&usb0_vbus_reg>;
297 in-v1-supply = <&mbatt_reg>;
298 in-v2-supply = <&mbatt_reg>;
299 in-v3-supply = <&mbatt_reg>;
300 in1-supply = <&mbatt_reg>;
301 in2-supply = <&nvvdd_sv3_reg>;
302 in3-supply = <&mbatt_reg>;
303 in4-supply = <&mbatt_reg>;
304 in5-supply = <&mbatt_reg>;
305 in6-supply = <&mbatt_reg>;
306 in7-supply = <&mbatt_reg>;
307 in8-supply = <&mbatt_reg>;
308 in9-supply = <&mbatt_reg>;
309 in10-supply = <&mbatt_reg>;
310 in11-supply = <&mbatt_reg>;
311 in12-supply = <&mbatt_reg>;
312 in13-supply = <&mbatt_reg>;
313 in14-supply = <&mbatt_reg>;
314 in15-supply = <&mbatt_reg>;
315 in16-supply = <&mbatt_reg>;
316 in17-supply = <&nvvdd_sv3_reg>;
317 in18-supply = <&nvvdd_sv3_reg>;
318 in19-supply = <&mbatt_reg>;
319 in20-supply = <&mbatt_reg>;
320
321 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600322 mbatt_reg: mbatt {
Stephen Warrene7765b32012-06-25 16:41:25 -0600323 regulator-name = "vbat_pmu";
324 regulator-always-on;
325 };
326
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600327 sd1 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600328 regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
329 regulator-min-microvolt = <1000000>;
330 regulator-max-microvolt = <1000000>;
331 regulator-always-on;
332 };
333
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600334 sd2 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600335 regulator-name = "nvvdd_sv2,vdd_core";
336 regulator-min-microvolt = <1200000>;
337 regulator-max-microvolt = <1200000>;
338 regulator-always-on;
339 };
340
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600341 nvvdd_sv3_reg: sd3 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600342 regulator-name = "nvvdd_sv3";
343 regulator-min-microvolt = <1800000>;
344 regulator-max-microvolt = <1800000>;
345 regulator-always-on;
346 };
347
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600348 ldo1 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600349 regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
350 regulator-min-microvolt = <3300000>;
351 regulator-max-microvolt = <3300000>;
352 regulator-always-on;
353 };
354
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600355 ldo2 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600356 regulator-name = "nvvdd_ldo2,avdd_pll*";
357 regulator-min-microvolt = <1100000>;
358 regulator-max-microvolt = <1100000>;
359 regulator-always-on;
360 };
361
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600362 ldo3 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600363 regulator-name = "nvvdd_ldo3,vcom_1v8b";
364 regulator-min-microvolt = <1800000>;
365 regulator-max-microvolt = <1800000>;
366 regulator-always-on;
367 };
368
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600369 ldo4 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600370 regulator-name = "nvvdd_ldo4,avdd_usb*";
371 regulator-min-microvolt = <3300000>;
372 regulator-max-microvolt = <3300000>;
373 regulator-always-on;
374 };
375
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600376 ldo5 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600377 regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
378 regulator-min-microvolt = <2800000>;
379 regulator-max-microvolt = <2800000>;
380 regulator-always-on;
381 };
382
Stephen Warren2658ef12012-11-16 10:53:04 -0700383 hdmi_pll_reg: ldo6 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600384 regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
385 regulator-min-microvolt = <1800000>;
386 regulator-max-microvolt = <1800000>;
387 };
388
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600389 ldo7 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600390 regulator-name = "nvvdd_ldo7,avddio_audio";
391 regulator-min-microvolt = <2800000>;
392 regulator-max-microvolt = <2800000>;
393 regulator-always-on;
394 };
395
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600396 ldo8 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600397 regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
398 regulator-min-microvolt = <3000000>;
399 regulator-max-microvolt = <3000000>;
400 };
401
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600402 ldo9 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600403 regulator-name = "nvvdd_ldo9,avdd_cam*";
404 regulator-min-microvolt = <2800000>;
405 regulator-max-microvolt = <2800000>;
406 };
407
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600408 ldo10 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600409 regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
410 regulator-min-microvolt = <3000000>;
411 regulator-max-microvolt = <3000000>;
412 regulator-always-on;
413 };
414
Stephen Warren2658ef12012-11-16 10:53:04 -0700415 hdmi_vdd_reg: ldo11 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600416 regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
417 regulator-min-microvolt = <3300000>;
418 regulator-max-microvolt = <3300000>;
419 };
420
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600421 ldo12 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600422 regulator-name = "nvvdd_ldo12,vddio_sdio";
423 regulator-min-microvolt = <2800000>;
424 regulator-max-microvolt = <2800000>;
425 regulator-always-on;
426 };
427
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600428 ldo13 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600429 regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
430 regulator-min-microvolt = <2800000>;
431 regulator-max-microvolt = <2800000>;
432 };
433
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600434 ldo14 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600435 regulator-name = "nvvdd_ldo14,avdd_vdac";
436 regulator-min-microvolt = <2800000>;
437 regulator-max-microvolt = <2800000>;
438 };
439
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600440 ldo15 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600441 regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
442 regulator-min-microvolt = <3300000>;
443 regulator-max-microvolt = <3300000>;
444 };
445
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600446 ldo16 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600447 regulator-name = "nvvdd_ldo16,vdd_dbrtr";
448 regulator-min-microvolt = <1300000>;
449 regulator-max-microvolt = <1300000>;
450 };
451
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600452 ldo17 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600453 regulator-name = "nvvdd_ldo17,vddio_mipi";
454 regulator-min-microvolt = <1200000>;
455 regulator-max-microvolt = <1200000>;
456 };
457
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600458 ldo18 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600459 regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
460 regulator-min-microvolt = <1800000>;
461 regulator-max-microvolt = <1800000>;
462 };
463
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600464 ldo19 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600465 regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
466 regulator-min-microvolt = <2800000>;
467 regulator-max-microvolt = <2800000>;
468 };
469
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600470 ldo20 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600471 regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
472 regulator-min-microvolt = <1200000>;
473 regulator-max-microvolt = <1200000>;
474 regulator-always-on;
475 };
476
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600477 out5v {
Stephen Warrene7765b32012-06-25 16:41:25 -0600478 regulator-name = "usb0_vbus_reg";
479 };
480
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600481 out33v {
Stephen Warrene7765b32012-06-25 16:41:25 -0600482 regulator-name = "pmu_out3v3";
483 };
484
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600485 bbat {
Stephen Warrene7765b32012-06-25 16:41:25 -0600486 regulator-name = "pmu_bbat";
487 regulator-min-microvolt = <2400000>;
488 regulator-max-microvolt = <2400000>;
489 regulator-always-on;
490 };
491
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600492 sdby {
Stephen Warrene7765b32012-06-25 16:41:25 -0600493 regulator-name = "vdd_aon";
494 regulator-always-on;
495 };
496
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600497 vrtc {
Stephen Warrene7765b32012-06-25 16:41:25 -0600498 regulator-name = "vrtc,pmu_vccadc";
499 regulator-always-on;
500 };
501 };
502 };
503 };
504
Stephen Warren57899052013-11-26 14:43:45 -0700505 kbc@7000e200 {
506 status = "okay";
507 nvidia,debounce-delay-ms = <20>;
508 nvidia,repeat-delay-ms = <160>;
509 nvidia,kbc-row-pins = <0 1 2>;
510 nvidia,kbc-col-pins = <16 17>;
511 nvidia,wakeup-source;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530512 linux,keymap = <MATRIX_KEY(0x00, 0x00, KEY_POWER)
513 MATRIX_KEY(0x01, 0x00, KEY_HOME)
514 MATRIX_KEY(0x01, 0x01, KEY_BACK)
515 MATRIX_KEY(0x02, 0x01, KEY_MENU)>;
Stephen Warren57899052013-11-26 14:43:45 -0700516 };
517
Stephen Warren58ecb232013-11-25 17:53:16 -0700518 pmc@7000e400 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600519 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800520 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800521 nvidia,cpu-pwr-good-time = <2000>;
522 nvidia,cpu-pwr-off-time = <1000>;
523 nvidia,core-pwr-good-time = <0 3845>;
524 nvidia,core-pwr-off-time = <93727>;
525 nvidia,core-power-req-active-high;
526 nvidia,sys-clock-req-active-high;
527 nvidia,combined-power-req;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600528 };
529
530 usb@c5000000 {
531 status = "okay";
Stephen Warrenc80efba2012-04-20 16:57:38 -0600532 };
533
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530534 usb-phy@c5000000 {
535 status = "okay";
536 vbus-supply = <&vbus1_reg>;
537 };
538
Stephen Warrenc80efba2012-04-20 16:57:38 -0600539 usb@c5008000 {
540 status = "okay";
Stephen Warrenc80efba2012-04-20 16:57:38 -0600541 };
542
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530543 usb-phy@c5008000 {
544 status = "okay";
545 vbus-supply = <&vbus3_reg>;
546 };
547
Stephen Warrenc80efba2012-04-20 16:57:38 -0600548 sdhci@c8000400 {
549 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700550 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
551 wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600552 bus-width = <8>;
553 };
554
555 sdhci@c8000600 {
556 status = "okay";
557 bus-width = <8>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600558 non-removable;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600559 };
560
Joseph Lo7021d122013-04-03 19:31:27 +0800561 clocks {
562 compatible = "simple-bus";
563 #address-cells = <1>;
564 #size-cells = <0>;
565
Stephen Warren58ecb232013-11-25 17:53:16 -0700566 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800567 compatible = "fixed-clock";
568 reg=<0>;
569 #clock-cells = <0>;
570 clock-frequency = <32768>;
571 };
572 };
573
Stephen Warrene7765b32012-06-25 16:41:25 -0600574 regulators {
575 compatible = "simple-bus";
576 #address-cells = <1>;
577 #size-cells = <0>;
578
Stephen Warren58ecb232013-11-25 17:53:16 -0700579 usb0_vbus_reg: regulator@0 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600580 compatible = "regulator-fixed";
581 reg = <0>;
582 regulator-name = "usb0_vbus";
583 regulator-min-microvolt = <5000000>;
584 regulator-max-microvolt = <5000000>;
585 regulator-always-on;
586 };
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530587
588 vbus1_reg: regulator@2 {
589 compatible = "regulator-fixed";
590 reg = <2>;
591 regulator-name = "vbus1";
592 regulator-min-microvolt = <5000000>;
593 regulator-max-microvolt = <5000000>;
Stephen Warren9f310de2013-07-01 15:07:05 -0600594 enable-active-high;
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530595 gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
Stephen Warren30ca2222013-08-20 14:00:13 -0600596 regulator-always-on;
597 regulator-boot-on;
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530598 };
599
600 vbus3_reg: regulator@3 {
601 compatible = "regulator-fixed";
602 reg = <3>;
603 regulator-name = "vbus3";
604 regulator-min-microvolt = <5000000>;
605 regulator-max-microvolt = <5000000>;
Stephen Warren9f310de2013-07-01 15:07:05 -0600606 enable-active-high;
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530607 gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
Stephen Warren30ca2222013-08-20 14:00:13 -0600608 regulator-always-on;
609 regulator-boot-on;
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530610 };
Stephen Warrene7765b32012-06-25 16:41:25 -0600611 };
612
Stephen Warrenc80efba2012-04-20 16:57:38 -0600613 sound {
614 compatible = "nvidia,tegra-audio-wm8753-whistler",
615 "nvidia,tegra-audio-wm8753";
616 nvidia,model = "NVIDIA Tegra Whistler";
617
618 nvidia,audio-routing =
619 "Headphone Jack", "LOUT1",
620 "Headphone Jack", "ROUT1",
621 "MIC2", "Mic Jack",
622 "MIC2N", "Mic Jack";
623
624 nvidia,i2s-controller = <&tegra_i2s1>;
625 nvidia,audio-codec = <&codec>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600626
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300627 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
628 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
629 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600630 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warrenc80efba2012-04-20 16:57:38 -0600631 };
632};