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gerrit-public.fairphone.software / kernel / msm-5.4 / 08ff924e7fa7b826396f5ef1cb15656db7fb6545 / . / arch / mips / include / asm / asmmacro.h
blob: 867f924b05c79522a2d397d0002bc8a1397319e2 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 Ralf Baechle
7 */
8#ifndef _ASM_ASMMACRO_H
9#define _ASM_ASMMACRO_H
Ralf Baechle42a3b4f2005-09-03 15:56:17 -0700[diff] [blame]10
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]11#include <asm/hazards.h>
Jim Quinlan71ca7582013-11-27 15:34:50 -0500[diff] [blame]12#include <asm/asm-offsets.h>
Paul Burtonf7a46fa2014-07-11 16:44:28 +0100[diff] [blame]13#include <asm/msa.h>
Ralf Baechle42a3b4f2005-09-03 15:56:17 -0700[diff] [blame]14
Ralf Baechle875d43e2005-09-03 15:56:16 -0700[diff] [blame]15#ifdef CONFIG_32BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]16#include <asm/asmmacro-32.h>
17#endif
Ralf Baechle875d43e2005-09-03 15:56:16 -0700[diff] [blame]18#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]19#include <asm/asmmacro-64.h>
20#endif
21
Leonid Yegoshin226da552014-11-05 12:56:40 +0000[diff] [blame]22#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
David Daneyb6354db2008-12-10 08:37:25 -0800[diff] [blame]23 .macro local_irq_enable reg=t0
24 ei
25 irq_enable_hazard
26 .endm
27
28 .macro local_irq_disable reg=t0
29 di
30 irq_disable_hazard
31 .endm
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]32#else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]33 .macro local_irq_enable reg=t0
34 mfc0 \reg, CP0_STATUS
35 ori \reg, \reg, 1
36 mtc0 \reg, CP0_STATUS
37 irq_enable_hazard
38 .endm
39
40 .macro local_irq_disable reg=t0
Jim Quinlan71ca7582013-11-27 15:34:50 -0500[diff] [blame]41#ifdef CONFIG_PREEMPT
42 lw \reg, TI_PRE_COUNT($28)
43 addi \reg, \reg, 1
44 sw \reg, TI_PRE_COUNT($28)
45#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]46 mfc0 \reg, CP0_STATUS
47 ori \reg, \reg, 1
48 xori \reg, \reg, 1
49 mtc0 \reg, CP0_STATUS
50 irq_disable_hazard
Jim Quinlan71ca7582013-11-27 15:34:50 -0500[diff] [blame]51#ifdef CONFIG_PREEMPT
52 lw \reg, TI_PRE_COUNT($28)
53 addi \reg, \reg, -1
54 sw \reg, TI_PRE_COUNT($28)
55#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]56 .endm
Ralf Baechleb6336482014-05-23 16:29:44 +0200[diff] [blame]57#endif /* CONFIG_CPU_MIPSR2 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]58
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]59 .macro fpu_save_16even thread tmp=t0
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]60 .set push
61 SET_HARDFLOAT
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]62 cfc1 \tmp, fcr31
James Hogan466aec52015-01-30 12:09:38 +0000[diff] [blame]63 sdc1 $f0, THREAD_FPR0(\thread)
64 sdc1 $f2, THREAD_FPR2(\thread)
65 sdc1 $f4, THREAD_FPR4(\thread)
66 sdc1 $f6, THREAD_FPR6(\thread)
67 sdc1 $f8, THREAD_FPR8(\thread)
68 sdc1 $f10, THREAD_FPR10(\thread)
69 sdc1 $f12, THREAD_FPR12(\thread)
70 sdc1 $f14, THREAD_FPR14(\thread)
71 sdc1 $f16, THREAD_FPR16(\thread)
72 sdc1 $f18, THREAD_FPR18(\thread)
73 sdc1 $f20, THREAD_FPR20(\thread)
74 sdc1 $f22, THREAD_FPR22(\thread)
75 sdc1 $f24, THREAD_FPR24(\thread)
76 sdc1 $f26, THREAD_FPR26(\thread)
77 sdc1 $f28, THREAD_FPR28(\thread)
78 sdc1 $f30, THREAD_FPR30(\thread)
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]79 sw \tmp, THREAD_FCR31(\thread)
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]80 .set pop
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]81 .endm
82
83 .macro fpu_save_16odd thread
84 .set push
85 .set mips64r2
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]86 SET_HARDFLOAT
James Hogan466aec52015-01-30 12:09:38 +0000[diff] [blame]87 sdc1 $f1, THREAD_FPR1(\thread)
88 sdc1 $f3, THREAD_FPR3(\thread)
89 sdc1 $f5, THREAD_FPR5(\thread)
90 sdc1 $f7, THREAD_FPR7(\thread)
91 sdc1 $f9, THREAD_FPR9(\thread)
92 sdc1 $f11, THREAD_FPR11(\thread)
93 sdc1 $f13, THREAD_FPR13(\thread)
94 sdc1 $f15, THREAD_FPR15(\thread)
95 sdc1 $f17, THREAD_FPR17(\thread)
96 sdc1 $f19, THREAD_FPR19(\thread)
97 sdc1 $f21, THREAD_FPR21(\thread)
98 sdc1 $f23, THREAD_FPR23(\thread)
99 sdc1 $f25, THREAD_FPR25(\thread)
100 sdc1 $f27, THREAD_FPR27(\thread)
101 sdc1 $f29, THREAD_FPR29(\thread)
102 sdc1 $f31, THREAD_FPR31(\thread)
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]103 .set pop
104 .endm
105
106 .macro fpu_save_double thread status tmp
Leonid Yegoshin207083b2014-11-24 11:54:19 +0000[diff] [blame]107#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
108 defined(CONFIG_CPU_MIPS32_R6)
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]109 sll \tmp, \status, 5
110 bgez \tmp, 10f
111 fpu_save_16odd \thread
11210:
113#endif
114 fpu_save_16even \thread \tmp
115 .endm
116
117 .macro fpu_restore_16even thread tmp=t0
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]118 .set push
119 SET_HARDFLOAT
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]120 lw \tmp, THREAD_FCR31(\thread)
James Hogan466aec52015-01-30 12:09:38 +0000[diff] [blame]121 ldc1 $f0, THREAD_FPR0(\thread)
122 ldc1 $f2, THREAD_FPR2(\thread)
123 ldc1 $f4, THREAD_FPR4(\thread)
124 ldc1 $f6, THREAD_FPR6(\thread)
125 ldc1 $f8, THREAD_FPR8(\thread)
126 ldc1 $f10, THREAD_FPR10(\thread)
127 ldc1 $f12, THREAD_FPR12(\thread)
128 ldc1 $f14, THREAD_FPR14(\thread)
129 ldc1 $f16, THREAD_FPR16(\thread)
130 ldc1 $f18, THREAD_FPR18(\thread)
131 ldc1 $f20, THREAD_FPR20(\thread)
132 ldc1 $f22, THREAD_FPR22(\thread)
133 ldc1 $f24, THREAD_FPR24(\thread)
134 ldc1 $f26, THREAD_FPR26(\thread)
135 ldc1 $f28, THREAD_FPR28(\thread)
136 ldc1 $f30, THREAD_FPR30(\thread)
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]137 ctc1 \tmp, fcr31
138 .endm
139
140 .macro fpu_restore_16odd thread
141 .set push
142 .set mips64r2
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]143 SET_HARDFLOAT
James Hogan466aec52015-01-30 12:09:38 +0000[diff] [blame]144 ldc1 $f1, THREAD_FPR1(\thread)
145 ldc1 $f3, THREAD_FPR3(\thread)
146 ldc1 $f5, THREAD_FPR5(\thread)
147 ldc1 $f7, THREAD_FPR7(\thread)
148 ldc1 $f9, THREAD_FPR9(\thread)
149 ldc1 $f11, THREAD_FPR11(\thread)
150 ldc1 $f13, THREAD_FPR13(\thread)
151 ldc1 $f15, THREAD_FPR15(\thread)
152 ldc1 $f17, THREAD_FPR17(\thread)
153 ldc1 $f19, THREAD_FPR19(\thread)
154 ldc1 $f21, THREAD_FPR21(\thread)
155 ldc1 $f23, THREAD_FPR23(\thread)
156 ldc1 $f25, THREAD_FPR25(\thread)
157 ldc1 $f27, THREAD_FPR27(\thread)
158 ldc1 $f29, THREAD_FPR29(\thread)
159 ldc1 $f31, THREAD_FPR31(\thread)
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]160 .set pop
161 .endm
162
163 .macro fpu_restore_double thread status tmp
Leonid Yegoshin207083b2014-11-24 11:54:19 +0000[diff] [blame]164#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
165 defined(CONFIG_CPU_MIPS32_R6)
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]166 sll \tmp, \status, 5
167 bgez \tmp, 10f # 16 register mode?
168
169 fpu_restore_16odd \thread
17010:
171#endif
172 fpu_restore_16even \thread \tmp
173 .endm
174
Leonid Yegoshin207083b2014-11-24 11:54:19 +0000[diff] [blame]175#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
Paul Burton1d688082014-01-15 10:31:49 +0000[diff] [blame]176 .macro _EXT rd, rs, p, s
177 ext \rd, \rs, \p, \s
178 .endm
Leonid Yegoshin207083b2014-11-24 11:54:19 +0000[diff] [blame]179#else /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
Paul Burton1d688082014-01-15 10:31:49 +0000[diff] [blame]180 .macro _EXT rd, rs, p, s
181 srl \rd, \rs, \p
182 andi \rd, \rd, (1 << \s) - 1
183 .endm
Leonid Yegoshin207083b2014-11-24 11:54:19 +0000[diff] [blame]184#endif /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
Paul Burton1d688082014-01-15 10:31:49 +0000[diff] [blame]185
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]186/*
187 * Temporary until all gas have MT ASE support
188 */
189 .macro DMT reg=0
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100[diff] [blame]190 .word 0x41600bc1 | (\reg << 16)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]191 .endm
192
193 .macro EMT reg=0
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100[diff] [blame]194 .word 0x41600be1 | (\reg << 16)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]195 .endm
196
197 .macro DVPE reg=0
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100[diff] [blame]198 .word 0x41600001 | (\reg << 16)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]199 .endm
200
201 .macro EVPE reg=0
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100[diff] [blame]202 .word 0x41600021 | (\reg << 16)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]203 .endm
204
205 .macro MFTR rt=0, rd=0, u=0, sel=0
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100[diff] [blame]206 .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]207 .endm
208
209 .macro MTTR rt=0, rd=0, u=0, sel=0
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100[diff] [blame]210 .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]211 .endm
212
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]213#ifdef TOOLCHAIN_SUPPORTS_MSA
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]214/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
215#undef fp
216
Paul Burtone1bebba2015-01-30 12:09:33 +0000[diff] [blame]217 .macro _cfcmsa rd, cs
218 .set push
219 .set mips32r2
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]220 .set fp=64
Paul Burtone1bebba2015-01-30 12:09:33 +0000[diff] [blame]221 .set msa
222 cfcmsa \rd, $\cs
223 .set pop
224 .endm
225
226 .macro _ctcmsa cd, rs
227 .set push
228 .set mips32r2
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]229 .set fp=64
Paul Burtone1bebba2015-01-30 12:09:33 +0000[diff] [blame]230 .set msa
231 ctcmsa $\cd, \rs
232 .set pop
233 .endm
234
Paul Burton6b35e112015-06-22 12:20:59 +0100[diff] [blame]235 .macro ld_b wd, off, base
236 .set push
237 .set mips32r2
238 .set msa
239 ld.b $w\wd, \off(\base)
240 .set pop
241 .endm
242
243 .macro ld_h wd, off, base
244 .set push
245 .set mips32r2
246 .set msa
247 ld.h $w\wd, \off(\base)
248 .set pop
249 .endm
250
251 .macro ld_w wd, off, base
252 .set push
253 .set mips32r2
254 .set msa
255 ld.w $w\wd, \off(\base)
256 .set pop
257 .endm
258
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]259 .macro ld_d wd, off, base
260 .set push
261 .set mips32r2
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]262 .set fp=64
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]263 .set msa
264 ld.d $w\wd, \off(\base)
265 .set pop
266 .endm
267
Paul Burton6b35e112015-06-22 12:20:59 +0100[diff] [blame]268 .macro st_b wd, off, base
269 .set push
270 .set mips32r2
271 .set msa
272 st.b $w\wd, \off(\base)
273 .set pop
274 .endm
275
276 .macro st_h wd, off, base
277 .set push
278 .set mips32r2
279 .set msa
280 st.h $w\wd, \off(\base)
281 .set pop
282 .endm
283
284 .macro st_w wd, off, base
285 .set push
286 .set mips32r2
287 .set msa
288 st.w $w\wd, \off(\base)
289 .set pop
290 .endm
291
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]292 .macro st_d wd, off, base
293 .set push
294 .set mips32r2
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]295 .set fp=64
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]296 .set msa
297 st.d $w\wd, \off(\base)
298 .set pop
299 .endm
300
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]301 .macro copy_u_w ws, n
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]302 .set push
303 .set mips32r2
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]304 .set fp=64
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]305 .set msa
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]306 copy_u.w $1, $w\ws[\n]
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]307 .set pop
308 .endm
309
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]310 .macro copy_u_d ws, n
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]311 .set push
312 .set mips64r2
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]313 .set fp=64
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]314 .set msa
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]315 copy_u.d $1, $w\ws[\n]
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]316 .set pop
317 .endm
318
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]319 .macro insert_w wd, n
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]320 .set push
321 .set mips32r2
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]322 .set fp=64
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]323 .set msa
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]324 insert.w $w\wd[\n], $1
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]325 .set pop
326 .endm
327
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]328 .macro insert_d wd, n
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]329 .set push
330 .set mips64r2
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]331 .set fp=64
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]332 .set msa
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]333 insert.d $w\wd[\n], $1
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]334 .set pop
335 .endm
336#else
Steven J. Hilld96cc3d2014-04-15 16:06:49 -0500[diff] [blame]337
338#ifdef CONFIG_CPU_MICROMIPS
339#define CFC_MSA_INSN 0x587e0056
340#define CTC_MSA_INSN 0x583e0816
Paul Burton6b35e112015-06-22 12:20:59 +0100[diff] [blame]341#define LDB_MSA_INSN 0x58000807
342#define LDH_MSA_INSN 0x58000817
343#define LDW_MSA_INSN 0x58000827
Steven J. Hilld96cc3d2014-04-15 16:06:49 -0500[diff] [blame]344#define LDD_MSA_INSN 0x58000837
Paul Burton6b35e112015-06-22 12:20:59 +0100[diff] [blame]345#define STB_MSA_INSN 0x5800080f
346#define STH_MSA_INSN 0x5800081f
347#define STW_MSA_INSN 0x5800082f
Steven J. Hilld96cc3d2014-04-15 16:06:49 -0500[diff] [blame]348#define STD_MSA_INSN 0x5800083f
349#define COPY_UW_MSA_INSN 0x58f00056
350#define COPY_UD_MSA_INSN 0x58f80056
351#define INSERT_W_MSA_INSN 0x59300816
352#define INSERT_D_MSA_INSN 0x59380816
353#else
354#define CFC_MSA_INSN 0x787e0059
355#define CTC_MSA_INSN 0x783e0819
Paul Burton6b35e112015-06-22 12:20:59 +0100[diff] [blame]356#define LDB_MSA_INSN 0x78000820
357#define LDH_MSA_INSN 0x78000821
358#define LDW_MSA_INSN 0x78000822
Steven J. Hilld96cc3d2014-04-15 16:06:49 -0500[diff] [blame]359#define LDD_MSA_INSN 0x78000823
Paul Burton6b35e112015-06-22 12:20:59 +0100[diff] [blame]360#define STB_MSA_INSN 0x78000824
361#define STH_MSA_INSN 0x78000825
362#define STW_MSA_INSN 0x78000826
Steven J. Hilld96cc3d2014-04-15 16:06:49 -0500[diff] [blame]363#define STD_MSA_INSN 0x78000827
364#define COPY_UW_MSA_INSN 0x78f00059
365#define COPY_UD_MSA_INSN 0x78f80059
366#define INSERT_W_MSA_INSN 0x79300819
367#define INSERT_D_MSA_INSN 0x79380819
368#endif
369
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]370 /*
371 * Temporary until all toolchains in use include MSA support.
372 */
Paul Burtone1bebba2015-01-30 12:09:33 +0000[diff] [blame]373 .macro _cfcmsa rd, cs
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]374 .set push
375 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]376 SET_HARDFLOAT
Steven J. Hilld96cc3d2014-04-15 16:06:49 -0500[diff] [blame]377 .insn
378 .word CFC_MSA_INSN | (\cs << 11)
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]379 move \rd, $1
380 .set pop
381 .endm
382
Paul Burtone1bebba2015-01-30 12:09:33 +0000[diff] [blame]383 .macro _ctcmsa cd, rs
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]384 .set push
385 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]386 SET_HARDFLOAT
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]387 move $1, \rs
Steven J. Hilld96cc3d2014-04-15 16:06:49 -0500[diff] [blame]388 .word CTC_MSA_INSN | (\cd << 6)
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]389 .set pop
390 .endm
391
Paul Burton6b35e112015-06-22 12:20:59 +0100[diff] [blame]392 .macro ld_b wd, off, base
393 .set push
394 .set noat
395 SET_HARDFLOAT
396 addu $1, \base, \off
397 .word LDB_MSA_INSN | (\wd << 6)
398 .set pop
399 .endm
400
401 .macro ld_h wd, off, base
402 .set push
403 .set noat
404 SET_HARDFLOAT
405 addu $1, \base, \off
406 .word LDH_MSA_INSN | (\wd << 6)
407 .set pop
408 .endm
409
410 .macro ld_w wd, off, base
411 .set push
412 .set noat
413 SET_HARDFLOAT
414 addu $1, \base, \off
415 .word LDW_MSA_INSN | (\wd << 6)
416 .set pop
417 .endm
418
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]419 .macro ld_d wd, off, base
420 .set push
421 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]422 SET_HARDFLOAT
Markos Chandras98a833c12014-11-05 14:17:52 +0000[diff] [blame]423 addu $1, \base, \off
Steven J. Hilld96cc3d2014-04-15 16:06:49 -0500[diff] [blame]424 .word LDD_MSA_INSN | (\wd << 6)
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]425 .set pop
426 .endm
427
Paul Burton6b35e112015-06-22 12:20:59 +0100[diff] [blame]428 .macro st_b wd, off, base
429 .set push
430 .set noat
431 SET_HARDFLOAT
432 addu $1, \base, \off
433 .word STB_MSA_INSN | (\wd << 6)
434 .set pop
435 .endm
436
437 .macro st_h wd, off, base
438 .set push
439 .set noat
440 SET_HARDFLOAT
441 addu $1, \base, \off
442 .word STH_MSA_INSN | (\wd << 6)
443 .set pop
444 .endm
445
446 .macro st_w wd, off, base
447 .set push
448 .set noat
449 SET_HARDFLOAT
450 addu $1, \base, \off
451 .word STW_MSA_INSN | (\wd << 6)
452 .set pop
453 .endm
454
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]455 .macro st_d wd, off, base
456 .set push
457 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]458 SET_HARDFLOAT
Markos Chandras98a833c12014-11-05 14:17:52 +0000[diff] [blame]459 addu $1, \base, \off
Steven J. Hilld96cc3d2014-04-15 16:06:49 -0500[diff] [blame]460 .word STD_MSA_INSN | (\wd << 6)
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]461 .set pop
462 .endm
463
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]464 .macro copy_u_w ws, n
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]465 .set push
466 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]467 SET_HARDFLOAT
Steven J. Hilld96cc3d2014-04-15 16:06:49 -0500[diff] [blame]468 .insn
469 .word COPY_UW_MSA_INSN | (\n << 16) | (\ws << 11)
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]470 .set pop
471 .endm
472
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]473 .macro copy_u_d ws, n
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]474 .set push
475 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]476 SET_HARDFLOAT
Steven J. Hilld96cc3d2014-04-15 16:06:49 -0500[diff] [blame]477 .insn
478 .word COPY_UD_MSA_INSN | (\n << 16) | (\ws << 11)
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]479 .set pop
480 .endm
481
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]482 .macro insert_w wd, n
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]483 .set push
484 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]485 SET_HARDFLOAT
Steven J. Hilld96cc3d2014-04-15 16:06:49 -0500[diff] [blame]486 .word INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6)
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]487 .set pop
488 .endm
489
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]490 .macro insert_d wd, n
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]491 .set push
492 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]493 SET_HARDFLOAT
Steven J. Hilld96cc3d2014-04-15 16:06:49 -0500[diff] [blame]494 .word INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6)
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]495 .set pop
496 .endm
497#endif
498
Paul Burton1db1af82014-01-27 15:23:11 +0000[diff] [blame]499 .macro msa_save_all thread
500 st_d 0, THREAD_FPR0, \thread
501 st_d 1, THREAD_FPR1, \thread
502 st_d 2, THREAD_FPR2, \thread
503 st_d 3, THREAD_FPR3, \thread
504 st_d 4, THREAD_FPR4, \thread
505 st_d 5, THREAD_FPR5, \thread
506 st_d 6, THREAD_FPR6, \thread
507 st_d 7, THREAD_FPR7, \thread
508 st_d 8, THREAD_FPR8, \thread
509 st_d 9, THREAD_FPR9, \thread
510 st_d 10, THREAD_FPR10, \thread
511 st_d 11, THREAD_FPR11, \thread
512 st_d 12, THREAD_FPR12, \thread
513 st_d 13, THREAD_FPR13, \thread
514 st_d 14, THREAD_FPR14, \thread
515 st_d 15, THREAD_FPR15, \thread
516 st_d 16, THREAD_FPR16, \thread
517 st_d 17, THREAD_FPR17, \thread
518 st_d 18, THREAD_FPR18, \thread
519 st_d 19, THREAD_FPR19, \thread
520 st_d 20, THREAD_FPR20, \thread
521 st_d 21, THREAD_FPR21, \thread
522 st_d 22, THREAD_FPR22, \thread
523 st_d 23, THREAD_FPR23, \thread
524 st_d 24, THREAD_FPR24, \thread
525 st_d 25, THREAD_FPR25, \thread
526 st_d 26, THREAD_FPR26, \thread
527 st_d 27, THREAD_FPR27, \thread
528 st_d 28, THREAD_FPR28, \thread
529 st_d 29, THREAD_FPR29, \thread
530 st_d 30, THREAD_FPR30, \thread
531 st_d 31, THREAD_FPR31, \thread
Paul Burtonf7a46fa2014-07-11 16:44:28 +0100[diff] [blame]532 .set push
533 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]534 SET_HARDFLOAT
Paul Burtone1bebba2015-01-30 12:09:33 +0000[diff] [blame]535 _cfcmsa $1, MSA_CSR
Paul Burtonf7a46fa2014-07-11 16:44:28 +0100[diff] [blame]536 sw $1, THREAD_MSA_CSR(\thread)
537 .set pop
Paul Burton1db1af82014-01-27 15:23:11 +0000[diff] [blame]538 .endm
539
540 .macro msa_restore_all thread
Paul Burtonf7a46fa2014-07-11 16:44:28 +0100[diff] [blame]541 .set push
542 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]543 SET_HARDFLOAT
Paul Burtonf7a46fa2014-07-11 16:44:28 +0100[diff] [blame]544 lw $1, THREAD_MSA_CSR(\thread)
Paul Burtone1bebba2015-01-30 12:09:33 +0000[diff] [blame]545 _ctcmsa MSA_CSR, $1
Paul Burtonf7a46fa2014-07-11 16:44:28 +0100[diff] [blame]546 .set pop
Paul Burton1db1af82014-01-27 15:23:11 +0000[diff] [blame]547 ld_d 0, THREAD_FPR0, \thread
548 ld_d 1, THREAD_FPR1, \thread
549 ld_d 2, THREAD_FPR2, \thread
550 ld_d 3, THREAD_FPR3, \thread
551 ld_d 4, THREAD_FPR4, \thread
552 ld_d 5, THREAD_FPR5, \thread
553 ld_d 6, THREAD_FPR6, \thread
554 ld_d 7, THREAD_FPR7, \thread
555 ld_d 8, THREAD_FPR8, \thread
556 ld_d 9, THREAD_FPR9, \thread
557 ld_d 10, THREAD_FPR10, \thread
558 ld_d 11, THREAD_FPR11, \thread
559 ld_d 12, THREAD_FPR12, \thread
560 ld_d 13, THREAD_FPR13, \thread
561 ld_d 14, THREAD_FPR14, \thread
562 ld_d 15, THREAD_FPR15, \thread
563 ld_d 16, THREAD_FPR16, \thread
564 ld_d 17, THREAD_FPR17, \thread
565 ld_d 18, THREAD_FPR18, \thread
566 ld_d 19, THREAD_FPR19, \thread
567 ld_d 20, THREAD_FPR20, \thread
568 ld_d 21, THREAD_FPR21, \thread
569 ld_d 22, THREAD_FPR22, \thread
570 ld_d 23, THREAD_FPR23, \thread
571 ld_d 24, THREAD_FPR24, \thread
572 ld_d 25, THREAD_FPR25, \thread
573 ld_d 26, THREAD_FPR26, \thread
574 ld_d 27, THREAD_FPR27, \thread
575 ld_d 28, THREAD_FPR28, \thread
576 ld_d 29, THREAD_FPR29, \thread
577 ld_d 30, THREAD_FPR30, \thread
578 ld_d 31, THREAD_FPR31, \thread
579 .endm
580
Paul Burtonc9017752014-07-30 08:53:20 +0100[diff] [blame]581 .macro msa_init_upper wd
582#ifdef CONFIG_64BIT
583 insert_d \wd, 1
584#else
585 insert_w \wd, 2
586 insert_w \wd, 3
587#endif
Paul Burtonc9017752014-07-30 08:53:20 +0100[diff] [blame]588 .endm
589
590 .macro msa_init_all_upper
591 .set push
592 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]593 SET_HARDFLOAT
Paul Burtonc9017752014-07-30 08:53:20 +0100[diff] [blame]594 not $1, zero
595 msa_init_upper 0
Paul Burtona3a498102015-01-30 12:09:32 +0000[diff] [blame]596 msa_init_upper 1
597 msa_init_upper 2
598 msa_init_upper 3
599 msa_init_upper 4
600 msa_init_upper 5
601 msa_init_upper 6
602 msa_init_upper 7
603 msa_init_upper 8
604 msa_init_upper 9
605 msa_init_upper 10
606 msa_init_upper 11
607 msa_init_upper 12
608 msa_init_upper 13
609 msa_init_upper 14
610 msa_init_upper 15
611 msa_init_upper 16
612 msa_init_upper 17
613 msa_init_upper 18
614 msa_init_upper 19
615 msa_init_upper 20
616 msa_init_upper 21
617 msa_init_upper 22
618 msa_init_upper 23
619 msa_init_upper 24
620 msa_init_upper 25
621 msa_init_upper 26
622 msa_init_upper 27
623 msa_init_upper 28
624 msa_init_upper 29
625 msa_init_upper 30
626 msa_init_upper 31
Paul Burtonc9017752014-07-30 08:53:20 +0100[diff] [blame]627 .set pop
628 .endm
629
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]630#endif /* _ASM_ASMMACRO_H */