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gerrit-public.fairphone.software / kernel / msm-5.4 / 0b29de4a6ac0936f56b974a3c19bd9c24ac5b5d7 / . / include / asm-arm / hardware / iop3xx.h
blob: 98b7cbc405e6baf945339e06cd095bf83f253f51 [file] [log] [blame]
Lennert Buytenhek7ae1f7e2006-09-18 23:12:53 +0100[diff] [blame]1/*
2 * include/asm-arm/hardware/iop3xx.h
3 *
4 * Intel IOP32X and IOP33X register definitions
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright (C) 2004 Intel Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __IOP3XX_H
16#define __IOP3XX_H
17
18/*
19 * IOP3XX processor registers
20 */
21#define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000
22#define IOP3XX_PERIPHERAL_VIRT_BASE 0xfeffe000
23#define IOP3XX_PERIPHERAL_SIZE 0x00002000
24#define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
25
Lennert Buytenhek0cb015f2006-09-18 23:16:23 +0100[diff] [blame]26/* Address Translation Unit */
27#define IOP3XX_ATUVID (volatile u16 *)IOP3XX_REG_ADDR(0x0100)
28#define IOP3XX_ATUDID (volatile u16 *)IOP3XX_REG_ADDR(0x0102)
29#define IOP3XX_ATUCMD (volatile u16 *)IOP3XX_REG_ADDR(0x0104)
30#define IOP3XX_ATUSR (volatile u16 *)IOP3XX_REG_ADDR(0x0106)
31#define IOP3XX_ATURID (volatile u8 *)IOP3XX_REG_ADDR(0x0108)
32#define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109)
33#define IOP3XX_ATUCLSR (volatile u8 *)IOP3XX_REG_ADDR(0x010c)
34#define IOP3XX_ATULT (volatile u8 *)IOP3XX_REG_ADDR(0x010d)
35#define IOP3XX_ATUHTR (volatile u8 *)IOP3XX_REG_ADDR(0x010e)
36#define IOP3XX_ATUBIST (volatile u8 *)IOP3XX_REG_ADDR(0x010f)
37#define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110)
38#define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114)
39#define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118)
40#define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c)
41#define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120)
42#define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124)
43#define IOP3XX_ASVIR (volatile u16 *)IOP3XX_REG_ADDR(0x012c)
44#define IOP3XX_ASIR (volatile u16 *)IOP3XX_REG_ADDR(0x012e)
45#define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130)
46#define IOP3XX_ATUILR (volatile u8 *)IOP3XX_REG_ADDR(0x013c)
47#define IOP3XX_ATUIPR (volatile u8 *)IOP3XX_REG_ADDR(0x013d)
48#define IOP3XX_ATUMGNT (volatile u8 *)IOP3XX_REG_ADDR(0x013e)
49#define IOP3XX_ATUMLAT (volatile u8 *)IOP3XX_REG_ADDR(0x013f)
50#define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140)
51#define IOP3XX_IATVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0144)
52#define IOP3XX_ERLR (volatile u32 *)IOP3XX_REG_ADDR(0x0148)
53#define IOP3XX_ERTVR (volatile u32 *)IOP3XX_REG_ADDR(0x014c)
54#define IOP3XX_IALR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0150)
55#define IOP3XX_IALR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0154)
56#define IOP3XX_IATVR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0158)
57#define IOP3XX_OIOWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x015c)
58#define IOP3XX_OMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0160)
59#define IOP3XX_OUMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0164)
60#define IOP3XX_OMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0168)
61#define IOP3XX_OUMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x016c)
62#define IOP3XX_OUDWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x0178)
63#define IOP3XX_ATUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0180)
64#define IOP3XX_PCSR (volatile u32 *)IOP3XX_REG_ADDR(0x0184)
65#define IOP3XX_ATUISR (volatile u32 *)IOP3XX_REG_ADDR(0x0188)
66#define IOP3XX_ATUIMR (volatile u32 *)IOP3XX_REG_ADDR(0x018c)
67#define IOP3XX_IABAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0190)
68#define IOP3XX_IAUBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0194)
69#define IOP3XX_IALR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0198)
70#define IOP3XX_IATVR3 (volatile u32 *)IOP3XX_REG_ADDR(0x019c)
71#define IOP3XX_OCCAR (volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
72#define IOP3XX_OCCDR (volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
73#define IOP3XX_PDSCR (volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
74#define IOP3XX_PMCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01c0)
75#define IOP3XX_PMNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01c1)
76#define IOP3XX_APMCR (volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
77#define IOP3XX_APMCSR (volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
78#define IOP3XX_PCIXCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01e0)
79#define IOP3XX_PCIXNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01e1)
80#define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
81#define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
82#define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
83
Lennert Buytenhek48388b22006-09-18 23:18:16 +0100[diff] [blame]84/* Timers */
85#define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000)
86#define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004)
87#define IOP3XX_TU_TCR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0008)
88#define IOP3XX_TU_TCR1 (volatile u32 *)IOP3XX_TIMER_REG(0x000c)
89#define IOP3XX_TU_TRR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0010)
90#define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014)
91#define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018)
92#define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c)
93#define IOP3XX_TMR_TC 0x01
94#define IOP3XX_TMR_EN 0x02
95#define IOP3XX_TMR_RELOAD 0x04
96#define IOP3XX_TMR_PRIVILEGED 0x09
97#define IOP3XX_TMR_RATIO_1_1 0x00
98#define IOP3XX_TMR_RATIO_4_1 0x10
99#define IOP3XX_TMR_RATIO_8_1 0x20
100#define IOP3XX_TMR_RATIO_16_1 0x30
101
Lennert Buytenheke25d64f2006-09-18 23:15:21 +0100[diff] [blame]102/* I2C bus interface unit */
103#define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680)
104#define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684)
105#define IOP3XX_ISAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1688)
106#define IOP3XX_IDBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x168c)
107#define IOP3XX_IBMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1694)
108#define IOP3XX_ICR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
109#define IOP3XX_ISR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
110#define IOP3XX_ISAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
111#define IOP3XX_IDBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
112#define IOP3XX_IBMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16b4)
113
Lennert Buytenhek7ae1f7e2006-09-18 23:12:53 +0100[diff] [blame]114
115/*
116 * IOP3XX I/O and Mem space regions for PCI autoconfiguration
117 */
118#define IOP3XX_PCI_MEM_WINDOW_SIZE 0x04000000
119#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
Lennert Buytenhek0cb015f2006-09-18 23:16:23 +0100[diff] [blame]120#define IOP3XX_PCI_LOWER_MEM_BA (*IOP3XX_OMWTVR0)
Lennert Buytenhek7ae1f7e2006-09-18 23:12:53 +0100[diff] [blame]121
122#define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000
123#define IOP3XX_PCI_LOWER_IO_PA 0x90000000
124#define IOP3XX_PCI_LOWER_IO_VA 0xfe000000
Lennert Buytenhek0cb015f2006-09-18 23:16:23 +0100[diff] [blame]125#define IOP3XX_PCI_LOWER_IO_BA (*IOP3XX_OIOWTVR)
Lennert Buytenhek7ae1f7e2006-09-18 23:12:53 +0100[diff] [blame]126
127
128#ifndef __ASSEMBLY__
129void iop3xx_map_io(void);
Lennert Buytenhek48388b22006-09-18 23:18:16 +0100[diff] [blame]130void iop3xx_init_time(unsigned long);
131unsigned long iop3xx_gettimeoffset(void);
Lennert Buytenheke25d64f2006-09-18 23:15:21 +0100[diff] [blame]132
133extern struct platform_device iop3xx_i2c0_device;
134extern struct platform_device iop3xx_i2c1_device;
Lennert Buytenhek0b29de42006-09-18 23:20:55 +0100[diff] [blame^]135
136extern inline void iop3xx_cp6_enable(void)
137{
138 u32 temp;
139
140 asm volatile (
141 "mrc p15, 0, %0, c15, c1, 0\n\t"
142 "orr %0, %0, #(1 << 6)\n\t"
143 "mcr p15, 0, %0, c15, c1, 0\n\t"
144 "mrc p15, 0, %0, c15, c1, 0\n\t"
145 "mov %0, %0\n\t"
146 "sub pc, pc, #4\n\t"
147 : "=r" (temp) );
148}
149
150extern inline void iop3xx_cp6_disable(void)
151{
152 u32 temp;
153
154 asm volatile (
155 "mrc p15, 0, %0, c15, c1, 0\n\t"
156 "bic %0, %0, #(1 << 6)\n\t"
157 "mcr p15, 0, %0, c15, c1, 0\n\t"
158 "mrc p15, 0, %0, c15, c1, 0\n\t"
159 "mov %0, %0\n\t"
160 "sub pc, pc, #4\n\t"
161 : "=r" (temp) );
162}
Lennert Buytenhek7ae1f7e2006-09-18 23:12:53 +0100[diff] [blame]163#endif
164
165
166#endif