blob: 3cdca006be2a520a58d63d167fb0b8b6d296a9ec [file] [log] [blame]
Larry Finger0c817332010-12-08 11:12:31 -06001/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../core.h"
32#include "../pci.h"
33#include "rtl8192c-reg.h"
34#include "rtl8192c-def.h"
35#include "rtl8192c-phy.h"
36#include "rtl8192c-dm.h"
37#include "rtl8192c-hw.h"
38#include "rtl8192c-sw.h"
39#include "rtl8192c-trx.h"
40#include "rtl8192c-led.h"
41
42int rtl92c_init_sw_vars(struct ieee80211_hw *hw)
43{
44 struct rtl_priv *rtlpriv = rtl_priv(hw);
45 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
46
47 rtlpriv->dm.b_dm_initialgain_enable = 1;
48 rtlpriv->dm.dm_flag = 0;
49 rtlpriv->dm.b_disable_framebursting = 0;;
50 rtlpriv->dm.thermalvalue = 0;
51 rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
52
53 rtlpci->receive_config = (RCR_APPFCS |
54 RCR_AMF |
55 RCR_ADF |
56 RCR_APP_MIC |
57 RCR_APP_ICV |
58 RCR_AICV |
59 RCR_ACRC32 |
60 RCR_AB |
61 RCR_AM |
62 RCR_APM |
63 RCR_APP_PHYST_RXFF | RCR_HTC_LOC_CTRL | 0);
64
65 rtlpci->irq_mask[0] =
66 (u32) (IMR_ROK |
67 IMR_VODOK |
68 IMR_VIDOK |
69 IMR_BEDOK |
70 IMR_BKDOK |
71 IMR_MGNTDOK |
72 IMR_HIGHDOK | IMR_BDOK | IMR_RDU | IMR_RXFOVW | 0);
73
74 rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD | 0);
75
76 rtlpriv->rtlhal.pfirmware = (u8 *) vmalloc(0x4000);
77 if (!rtlpriv->rtlhal.pfirmware) {
78 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
79 ("Can't alloc buffer for fw.\n"));
80 return 1;
81 }
82
83 return 0;
84}
85
86void rtl92c_deinit_sw_vars(struct ieee80211_hw *hw)
87{
88 struct rtl_priv *rtlpriv = rtl_priv(hw);
89
90 if (rtlpriv->rtlhal.pfirmware) {
91 vfree(rtlpriv->rtlhal.pfirmware);
92 rtlpriv->rtlhal.pfirmware = NULL;
93 }
94}
95
96static struct rtl_hal_ops rtl8192ce_hal_ops = {
97 .init_sw_vars = rtl92c_init_sw_vars,
98 .deinit_sw_vars = rtl92c_deinit_sw_vars,
99 .read_eeprom_info = rtl92ce_read_eeprom_info,
100 .interrupt_recognized = rtl92ce_interrupt_recognized,
101 .hw_init = rtl92ce_hw_init,
102 .hw_disable = rtl92ce_card_disable,
103 .enable_interrupt = rtl92ce_enable_interrupt,
104 .disable_interrupt = rtl92ce_disable_interrupt,
105 .set_network_type = rtl92ce_set_network_type,
106 .set_qos = rtl92ce_set_qos,
107 .set_bcn_reg = rtl92ce_set_beacon_related_registers,
108 .set_bcn_intv = rtl92ce_set_beacon_interval,
109 .update_interrupt_mask = rtl92ce_update_interrupt_mask,
110 .get_hw_reg = rtl92ce_get_hw_reg,
111 .set_hw_reg = rtl92ce_set_hw_reg,
112 .update_rate_table = rtl92ce_update_hal_rate_table,
113 .update_rate_mask = rtl92ce_update_hal_rate_mask,
114 .fill_tx_desc = rtl92ce_tx_fill_desc,
115 .fill_tx_cmddesc = rtl92ce_tx_fill_cmddesc,
116 .query_rx_desc = rtl92ce_rx_query_desc,
117 .set_channel_access = rtl92ce_update_channel_access_setting,
118 .radio_onoff_checking = rtl92ce_gpio_radio_on_off_checking,
119 .set_bw_mode = rtl92c_phy_set_bw_mode,
120 .switch_channel = rtl92c_phy_sw_chnl,
121 .dm_watchdog = rtl92c_dm_watchdog,
122 .scan_operation_backup = rtl92c_phy_scan_operation_backup,
123 .set_rf_power_state = rtl92c_phy_set_rf_power_state,
124 .led_control = rtl92ce_led_control,
125 .set_desc = rtl92ce_set_desc,
126 .get_desc = rtl92ce_get_desc,
127 .tx_polling = rtl92ce_tx_polling,
128 .enable_hw_sec = rtl92ce_enable_hw_security_config,
129 .set_key = rtl92ce_set_key,
130 .init_sw_leds = rtl92ce_init_sw_leds,
131 .deinit_sw_leds = rtl92ce_deinit_sw_leds,
132 .get_bbreg = rtl92c_phy_query_bb_reg,
133 .set_bbreg = rtl92c_phy_set_bb_reg,
134 .get_rfreg = rtl92c_phy_query_rf_reg,
135 .set_rfreg = rtl92c_phy_set_rf_reg,
136};
137
138static struct rtl_mod_params rtl92ce_mod_params = {
139 .sw_crypto = 0,
140};
141
142static struct rtl_hal_cfg rtl92ce_hal_cfg = {
143 .name = "rtl92c_pci",
144 .fw_name = "rtlwifi/rtl8192cfw.bin",
145 .ops = &rtl8192ce_hal_ops,
146 .mod_params = &rtl92ce_mod_params,
147
148 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
149 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
150 .maps[SYS_CLK] = REG_SYS_CLKR,
151 .maps[MAC_RCR_AM] = AM,
152 .maps[MAC_RCR_AB] = AB,
153 .maps[MAC_RCR_ACRC32] = ACRC32,
154 .maps[MAC_RCR_ACF] = ACF,
155 .maps[MAC_RCR_AAP] = AAP,
156
157 .maps[EFUSE_TEST] = REG_EFUSE_TEST,
158 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
159 .maps[EFUSE_CLK] = 0,
160 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
161 .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
162 .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
163 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
164 .maps[EFUSE_ANA8M] = EFUSE_ANA8M,
165 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
166
167 .maps[RWCAM] = REG_CAMCMD,
168 .maps[WCAMI] = REG_CAMWRITE,
169 .maps[RCAMO] = REG_CAMREAD,
170 .maps[CAMDBG] = REG_CAMDBG,
171 .maps[SECR] = REG_SECCFG,
172 .maps[SEC_CAM_NONE] = CAM_NONE,
173 .maps[SEC_CAM_WEP40] = CAM_WEP40,
174 .maps[SEC_CAM_TKIP] = CAM_TKIP,
175 .maps[SEC_CAM_AES] = CAM_AES,
176 .maps[SEC_CAM_WEP104] = CAM_WEP104,
177
178 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
179 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
180 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
181 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
182 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
183 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
184 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
185 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
186 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
187 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
188 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
189 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
190 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
191 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
192 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
193 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
194
195 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
196 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
197 .maps[RTL_IMR_BcnInt] = IMR_BCNINT,
198 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
199 .maps[RTL_IMR_RDU] = IMR_RDU,
200 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
201 .maps[RTL_IMR_BDOK] = IMR_BDOK,
202 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
203 .maps[RTL_IMR_TBDER] = IMR_TBDER,
204 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
205 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
206 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
207 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
208 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
209 .maps[RTL_IMR_VODOK] = IMR_VODOK,
210 .maps[RTL_IMR_ROK] = IMR_ROK,
211 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
212
213 .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
214 .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
215 .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
216 .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
217 .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
218 .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
219 .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
220 .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
221 .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
222 .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
223 .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
224 .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
225
226 .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
227 .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
228};
229
230static struct pci_device_id rtl92ce_pci_ids[] __devinitdata = {
231 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8191, rtl92ce_hal_cfg)},
232 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8178, rtl92ce_hal_cfg)},
233 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8177, rtl92ce_hal_cfg)},
234 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8176, rtl92ce_hal_cfg)},
235 {},
236};
237
238MODULE_DEVICE_TABLE(pci, rtl92ce_pci_ids);
239
240MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
241MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
242MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
243MODULE_LICENSE("GPL");
244MODULE_DESCRIPTION("Realtek 8192C/8188C 802.11n PCI wireless");
245MODULE_FIRMWARE("rtlwifi/rtl8192cfw.bin");
246
247module_param_named(swenc, rtl92ce_mod_params.sw_crypto, bool, 0444);
248MODULE_PARM_DESC(swenc, "using hardware crypto (default 0 [hardware])\n");
249
250static struct pci_driver rtl92ce_driver = {
251 .name = KBUILD_MODNAME,
252 .id_table = rtl92ce_pci_ids,
253 .probe = rtl_pci_probe,
254 .remove = rtl_pci_disconnect,
255
256#ifdef CONFIG_PM
257 .suspend = rtl_pci_suspend,
258 .resume = rtl_pci_resume,
259#endif
260
261};
262
263static int __init rtl92ce_module_init(void)
264{
265 int ret;
266
267 ret = pci_register_driver(&rtl92ce_driver);
268 if (ret)
269 RT_ASSERT(false, (": No device found\n"));
270
271 return ret;
272}
273
274static void __exit rtl92ce_module_exit(void)
275{
276 pci_unregister_driver(&rtl92ce_driver);
277}
278
279module_init(rtl92ce_module_init);
280module_exit(rtl92ce_module_exit);